drm/i915/dg2: add TRANS_DP2_VFREQHIGH and TRANS_DP2_VFREQLOW

Add the registers for specifying the lower and higher 24 bits of the DP
2.0 pixel clock frequency in Hz.

Bspec: 53326
Reviewed-by: Manasi Navare <manasi.d.navare@intel.com>
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/9047f10318a30bc03ce8516ee3f5512437a95663.1629735412.git.jani.nikula@intel.com

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 9498852..d5177c7 100644 (file)
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -9106,6 +9106,20 @@ enum {
 #define  TRANS_DP2_PANEL_REPLAY_ENABLE         REG_BIT(30)
 #define  TRANS_DP2_DEBUG_ENABLE                        REG_BIT(23)
 
+#define _TRANS_DP2_VFREQHIGH_A                 0x600a4
+#define _TRANS_DP2_VFREQHIGH_B                 0x610a4
+#define _TRANS_DP2_VFREQHIGH_C                 0x620a4
+#define _TRANS_DP2_VFREQHIGH_D                 0x630a4
+#define TRANS_DP2_VFREQHIGH(trans)             _MMIO_TRANS(trans, _TRANS_DP2_VFREQHIGH_A, _TRANS_DP2_VFREQHIGH_B)
+#define  TRANS_DP2_VFREQ_PIXEL_CLOCK_MASK      REG_GENMASK(31, 8)
+#define  TRANS_DP2_VFREQ_PIXEL_CLOCK(clk_hz)   REG_FIELD_PREP(TRANS_DP2_VFREQ_PIXEL_CLOCK_MASK, (clk_hz))
+
+#define _TRANS_DP2_VFREQLOW_A                  0x600a8
+#define _TRANS_DP2_VFREQLOW_B                  0x610a8
+#define _TRANS_DP2_VFREQLOW_C                  0x620a8
+#define _TRANS_DP2_VFREQLOW_D                  0x630a8
+#define TRANS_DP2_VFREQLOW(trans)              _MMIO_TRANS(trans, _TRANS_DP2_VFREQLOW_A, _TRANS_DP2_VFREQLOW_B)
+
 /* SNB eDP training params */
 /* SNB A-stepping */
 #define  EDP_LINK_TRAIN_400MV_0DB_SNB_A                (0x38 << 22)