gallium/radeon: allow allocating textures >= 4 GB

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>

diff --git a/src/gallium/drivers/radeon/r600_buffer_common.c b/src/gallium/drivers/radeon/r600_buffer_common.c
index 606b1fc..0f892c0 100644 (file)
--- a/src/gallium/drivers/radeon/r600_buffer_common.c
+++ b/src/gallium/drivers/radeon/r600_buffer_common.c
@@ -102,7 +102,7 @@ void *r600_buffer_map_sync_with_rings(struct r600_common_context *ctx,
 
 bool r600_init_resource(struct r600_common_screen *rscreen,
                        struct r600_resource *res,
-                       unsigned size, unsigned alignment,
+                       uint64_t size, unsigned alignment,
                        bool use_reusable_pool)
 {
        struct r600_texture *rtex = (struct r600_texture*)res;

diff --git a/src/gallium/drivers/radeon/r600_pipe_common.h b/src/gallium/drivers/radeon/r600_pipe_common.h
index c387922..9b28758 100644 (file)
--- a/src/gallium/drivers/radeon/r600_pipe_common.h
+++ b/src/gallium/drivers/radeon/r600_pipe_common.h
@@ -140,6 +140,9 @@ struct radeon_shader_binary {
 void radeon_shader_binary_init(struct radeon_shader_binary *b);
 void radeon_shader_binary_clean(struct radeon_shader_binary *b);
 
+/* Only 32-bit buffer allocations are supported, gallium doesn't support more
+ * at the moment.
+ */
 struct r600_resource {
        struct u_resource               b;
 
@@ -184,8 +187,8 @@ struct r600_transfer {
 };
 
 struct r600_fmask_info {
-       unsigned offset;
-       unsigned size;
+       uint64_t offset;
+       uint64_t size;
        unsigned alignment;
        unsigned pitch_in_pixels;
        unsigned bank_height;
@@ -194,8 +197,8 @@ struct r600_fmask_info {
 };
 
 struct r600_cmask_info {
-       unsigned offset;
-       unsigned size;
+       uint64_t offset;
+       uint64_t size;
        unsigned alignment;
        unsigned pitch;
        unsigned height;
@@ -215,7 +218,7 @@ struct r600_htile_info {
 struct r600_texture {
        struct r600_resource            resource;
 
-       unsigned                        size;
+       uint64_t                        size;
        bool                            is_depth;
        unsigned                        dirty_level_mask; /* each bit says if that mipmap is compressed */
        unsigned                        stencil_dirty_level_mask; /* each bit says if that mipmap is compressed */
@@ -227,7 +230,7 @@ struct r600_texture {
        struct r600_fmask_info          fmask;
        struct r600_cmask_info          cmask;
        struct r600_resource            *cmask_buffer;
-       unsigned                        dcc_offset; /* 0 = disabled */
+       uint64_t                        dcc_offset; /* 0 = disabled */
        unsigned                        cb_color_info; /* fast clear enable bit */
        unsigned                        color_clear_value[2];
 
@@ -509,7 +512,7 @@ void *r600_buffer_map_sync_with_rings(struct r600_common_context *ctx,
                                       unsigned usage);
 bool r600_init_resource(struct r600_common_screen *rscreen,
                        struct r600_resource *res,
-                       unsigned size, unsigned alignment,
+                       uint64_t size, unsigned alignment,
                        bool use_reusable_pool);
 struct pipe_resource *r600_buffer_create(struct pipe_screen *screen,
                                         const struct pipe_resource *templ,

diff --git a/src/gallium/drivers/radeon/r600_texture.c b/src/gallium/drivers/radeon/r600_texture.c
index 4850b73..9391685 100644 (file)
--- a/src/gallium/drivers/radeon/r600_texture.c
+++ b/src/gallium/drivers/radeon/r600_texture.c
@@ -482,7 +482,7 @@ static void r600_texture_allocate_fmask(struct r600_common_screen *rscreen,
        r600_texture_get_fmask_info(rscreen, rtex,
                                    rtex->resource.b.b.nr_samples, &rtex->fmask);
 
-       rtex->fmask.offset = align(rtex->size, rtex->fmask.alignment);
+       rtex->fmask.offset = align64(rtex->size, rtex->fmask.alignment);
        rtex->size = rtex->fmask.offset + rtex->fmask.size;
 }
 
@@ -585,7 +585,7 @@ static void r600_texture_allocate_cmask(struct r600_common_screen *rscreen,
                r600_texture_get_cmask_info(rscreen, rtex, &rtex->cmask);
        }
 
-       rtex->cmask.offset = align(rtex->size, rtex->cmask.alignment);
+       rtex->cmask.offset = align64(rtex->size, rtex->cmask.alignment);
        rtex->size = rtex->cmask.offset + rtex->cmask.size;
 
        if (rscreen->chip_class >= SI)
@@ -747,14 +747,14 @@ void r600_print_texture_info(struct r600_texture *rtex, FILE *f)
                (rtex->surface.flags & RADEON_SURF_SCANOUT) != 0);
 
        if (rtex->fmask.size)
-               fprintf(f, "  FMask: offset=%u, size=%u, alignment=%u, pitch_in_pixels=%u, "
+               fprintf(f, "  FMask: offset=%"PRIu64", size=%"PRIu64", alignment=%u, pitch_in_pixels=%u, "
                        "bankh=%u, slice_tile_max=%u, tile_mode_index=%u\n",
                        rtex->fmask.offset, rtex->fmask.size, rtex->fmask.alignment,
                        rtex->fmask.pitch_in_pixels, rtex->fmask.bank_height,
                        rtex->fmask.slice_tile_max, rtex->fmask.tile_mode_index);
 
        if (rtex->cmask.size)
-               fprintf(f, "  CMask: offset=%u, size=%u, alignment=%u, pitch=%u, "
+               fprintf(f, "  CMask: offset=%"PRIu64", size=%"PRIu64", alignment=%u, pitch=%u, "
                        "height=%u, xalign=%u, yalign=%u, slice_tile_max=%u\n",
                        rtex->cmask.offset, rtex->cmask.size, rtex->cmask.alignment,
                        rtex->cmask.pitch, rtex->cmask.height, rtex->cmask.xalign,
@@ -768,7 +768,7 @@ void r600_print_texture_info(struct r600_texture *rtex, FILE *f)
                        rtex->htile.height, rtex->htile.xalign, rtex->htile.yalign);
 
        if (rtex->dcc_offset) {
-               fprintf(f, "  DCC: offset=%u, size=%"PRIu64", alignment=%"PRIu64"\n",
+               fprintf(f, "  DCC: offset=%"PRIu64", size=%"PRIu64", alignment=%"PRIu64"\n",
                        rtex->dcc_offset, rtex->surface.dcc_size,
                        rtex->surface.dcc_alignment);
                for (i = 0; i <= rtex->surface.last_level; i++)
@@ -873,7 +873,7 @@ r600_texture_create_object(struct pipe_screen *screen,
                if (!buf && rtex->surface.dcc_size &&
                    !(rscreen->debug_flags & DBG_NO_DCC)) {
                        /* Reserve space for the DCC buffer. */
-                       rtex->dcc_offset = align(rtex->size, rtex->surface.dcc_alignment);
+                       rtex->dcc_offset = align64(rtex->size, rtex->surface.dcc_alignment);
                        rtex->size = rtex->dcc_offset + rtex->surface.dcc_size;
                        rtex->cb_color_info |= VI_S_028C70_DCC_ENABLE(1);
                }