- internal bus added.
generic ( dsize : integer := 8
);
port (
- clk : in std_logic;
- ah_oe_n : in std_logic;
- al_oe_n : in std_logic;
- base : in std_logic_vector (dsize - 1 downto 0);
+ clk : in std_logic;
+ ea_calc_n : in std_logic;
+ zp_n : in std_logic;
+ pg_next_n : in std_logic;
+ base_l : in std_logic_vector (dsize - 1 downto 0);
+ base_h : in std_logic_vector (dsize - 1 downto 0);
index : in std_logic_vector (dsize - 1 downto 0);
ah_bus : out std_logic_vector (dsize - 1 downto 0);
al_bus : out std_logic_vector (dsize - 1 downto 0);
end effective_adder;
architecture rtl of effective_adder is
- component dff
- generic (
- dsize : integer := 8
- );
- port (
- clk : in std_logic;
- we_n : in std_logic;
- oe_n : in std_logic;
- d : in std_logic_vector (dsize - 1 downto 0);
- q : out std_logic_vector (dsize - 1 downto 0)
- );
- end component;
-signal al_out : std_logic_vector (dsize - 1 downto 0);
-signal ah_out : std_logic_vector (dsize - 1 downto 0);
-signal old_al : std_logic_vector (dsize - 1 downto 0);
signal adc_work : std_logic_vector (dsize downto 0);
begin
- adc_work <= ('0' & base) + ('0' & index);
- carry <= adc_work(dsize);
- al_out <= adc_work(dsize - 1 downto 0);
- ---always remory adl.
- al_buf : dff generic map (dsize)
- port map (clk, '0', '0', al_out, old_al);
-
- --both output means, page boundary crossed.
- --output old effective addr low.
- al_bus <= old_al when al_oe_n = '0' and ah_oe_n = '0' else
- al_out when al_oe_n = '0' else
- (others => 'Z');
+ adc_work <= ('0' & base_l) + ('0' & index);
+ carry <= adc_work(dsize) when ea_calc_n = '0' else
+ 'Z';
+ --if not calc effective adder, pass through input.
+ al_bus <= adc_work(dsize - 1 downto 0) when ea_calc_n = '0' else
+ base_l;
- --ah output means, page boundary crossed.
- ah_bus <= base + '1' when ah_oe_n = '0' else
- (others => 'Z');
+ ah_bus <= "00000000" when ea_calc_n = '0' and zp_n = '0' else
+ base_h + '1' when ea_calc_n = '0' and pg_next_n = '0' else
+ base_h;
end rtl;
dsize : integer := 8
);
port (
- int_al_we_n : in std_logic;
- int_ah_we_n : in std_logic;
- int_dl_oe_n : in std_logic;
- int_dh_oe_n : in std_logic;
- int_al_oe_n : in std_logic;
- int_ah_oe_n : in std_logic;
- int_dbus : inout std_logic_vector (dsize - 1 downto 0);
- int_abus_l : out std_logic_vector (dsize - 1 downto 0);
- int_abus_h : out std_logic_vector (dsize - 1 downto 0)
+ al_we_n : in std_logic;
+ ah_we_n : in std_logic;
+ al_oe_n : in std_logic;
+ ah_oe_n : in std_logic;
+ int_dbus : in std_logic_vector (dsize - 1 downto 0);
+ ea_al : out std_logic_vector (dsize - 1 downto 0);
+ ea_ah : out std_logic_vector (dsize - 1 downto 0)
);
end input_dl;
signal ql : std_logic_vector (dsize - 1 downto 0);
signal qh : std_logic_vector (dsize - 1 downto 0);
begin
- --oe_n <= (int_d_oe_n and int_al_oe_n and int_ah_oe_n);
- ----TODO: must check!! for the time being, output ql.
- int_dbus <= ql when int_dl_oe_n = '0' else
- (others =>'Z');
- int_dbus <= qh when int_dh_oe_n = '0' else
- (others =>'Z');
- int_abus_l <= ql when int_al_oe_n = '0' else
+ ea_al <= ql when al_oe_n = '0' else
(others =>'Z');
- int_abus_h <= qh when int_ah_oe_n = '0' else
+ ea_ah <= qh when ah_oe_n = '0' else
(others =>'Z');
latch_l : latch generic map (dsize)
- port map(int_al_we_n, '0', int_dbus, ql);
+ port map(al_we_n, '0', int_dbus, ql);
latch_h : latch generic map (dsize)
- port map(int_ah_we_n, '0', int_dbus, qh);
+ port map(ah_we_n, '0', int_dbus, qh);
end rtl;
----------------------------------------
port map(clk, we_n, oe_n, d, q);
end rtl;
+----------------------------------------
+--- index register x/y
+----------------------------------------
+
+library ieee;
+use ieee.std_logic_1164.all;
+
+entity index_reg is
+ generic (
+ dsize : integer := 8
+ );
+ port (
+ clk : in std_logic;
+ d_we_n : in std_logic;
+ d_oe_n : in std_logic;
+ ea_oe_n : in std_logic;
+ int_dbus : inout std_logic_vector (dsize - 1 downto 0);
+ ea_bus : out std_logic_vector (dsize - 1 downto 0)
+ );
+end index_reg;
+
+architecture rtl of index_reg is
+component dff
+ generic (
+ dsize : integer := 8
+ );
+ port (
+ clk : in std_logic;
+ we_n : in std_logic;
+ oe_n : in std_logic;
+ d : in std_logic_vector (dsize - 1 downto 0);
+ q : out std_logic_vector (dsize - 1 downto 0)
+ );
+end component;
+
+signal q : std_logic_vector (dsize - 1 downto 0);
+
+begin
+ int_dbus <= q when d_oe_n = '0' else
+ (others => 'Z');
+ ea_bus <= q when ea_oe_n = '0' else
+ (others => 'Z');
+
+ --read from i/o to cpu
+ dff_inst : dff generic map (dsize)
+ port map(clk, d_we_n, '0', int_dbus, q);
+end rtl;
+
+
rdy : in std_logic;
instruction : in std_logic_vector (dsize - 1 downto 0);
status_reg : inout std_logic_vector (dsize - 1 downto 0);
+ inst_we_n : out std_logic;
ad_oe_n : out std_logic;
pcl_d_we_n : out std_logic;
pcl_a_we_n : out std_logic;
pch_d_oe_n : out std_logic;
pch_a_oe_n : out std_logic;
pc_inc_n : out std_logic;
- inst_we_n : out std_logic;
dbuf_int_oe_n : out std_logic;
dl_al_we_n : out std_logic;
dl_ah_we_n : out std_logic;
- dl_dl_oe_n : out std_logic;
- dl_dh_oe_n : out std_logic;
dl_al_oe_n : out std_logic;
dl_ah_oe_n : out std_logic;
sp_we_n : out std_logic;
acc_alu_oe_n : out std_logic;
x_we_n : out std_logic;
x_oe_n : out std_logic;
- x_calc_n : out std_logic;
+ x_ea_oe_n : out std_logic;
y_we_n : out std_logic;
y_oe_n : out std_logic;
- y_calc_n : out std_logic;
- ea_ah_oe_n : out std_logic;
- ea_al_oe_n : out std_logic;
+ y_ea_oe_n : out std_logic;
+ ea_calc_n : out std_logic;
+ ea_zp_n : out std_logic;
+ ea_pg_next_n : out std_logic;
ea_carry : in std_logic;
stat_dec_we_n : out std_logic;
stat_dec_oe_n : out std_logic;
dbuf_int_oe_n <= '1';
dl_al_we_n <= '1';
dl_ah_we_n <= '1';
- dl_dl_oe_n <= '1';
- dl_dh_oe_n <= '1';
dl_al_oe_n <= '1';
dl_ah_oe_n <= '1';
sp_we_n <= '1';
stat_dec_oe_n <= '1';
stat_bus_we_n <= '1';
stat_bus_oe_n <= '1';
- x_calc_n <= '1';
- y_calc_n <= '1';
- ea_ah_oe_n <= '1';
- ea_al_oe_n <= '1';
+ x_ea_oe_n <= '1';
+ y_ea_oe_n <= '1';
+ ea_calc_n <= '1';
+ ea_zp_n <= '1';
+ ea_pg_next_n <= '1';
end if;
inst_we_n <= '0';
pc_inc_n <= '0';
+ --disable the last opration pins.
+ x_oe_n <= '1';
+ y_oe_n <= '1';
x_we_n <= '1';
y_we_n <= '1';
sp_we_n <= '1';
sp_push_n <= '1';
sp_pop_n <= '1';
- x_oe_n <= '1';
r_nw <= '1';
dbuf_int_oe_n <= '1';
stat_dec_we_n <= '1';
pcl_d_we_n <= '1';
acc_d_we_n <= '1';
acc_d_oe_n <= '1';
- dl_dl_oe_n <= '1';
- x_calc_n <= '1';
- ea_al_oe_n <= '1';
- dl_dh_oe_n <= '1';
- ea_ah_oe_n <= '1';
+ x_ea_oe_n <= '1';
+ ea_calc_n <= '1';
cur_cycle <= decode;
cur_cycle <= err_cycle;
end if; --if cur_mode = ad_imm then
- if instruction (1 downto 0) = "01" then
- --d_print("cc=01");
-
- if instruction (7 downto 5) = "000" then
- d_print("ora");
- elsif instruction (7 downto 5) = "001" then
- d_print("and");
- elsif instruction (7 downto 5) = "010" then
- d_print("eor");
- elsif instruction (7 downto 5) = "011" then
- d_print("adc");
- elsif instruction (7 downto 5) = "100" then
- if (cur_mode = ad_imm) then
- d_print("sta");
- end if;
- elsif instruction (7 downto 5) = "101" then
- if (cur_mode = ad_imm) then
+ if (cur_mode = ad_imm) then
+ if instruction (1 downto 0) = "01" then
+ --d_print("cc=01");
+
+ if instruction (7 downto 5) = "000" then
+ d_print("ora");
+ elsif instruction (7 downto 5) = "001" then
+ d_print("and");
+ elsif instruction (7 downto 5) = "010" then
+ d_print("eor");
+ elsif instruction (7 downto 5) = "011" then
+ d_print("adc");
+ elsif instruction (7 downto 5) = "100" then
+ if (cur_mode = ad_imm) then
+ d_print("sta");
+ end if;
+ elsif instruction (7 downto 5) = "101" then
d_print("lda");
acc_d_we_n <= '0';
--status register n/z bit update.
stat_dec_oe_n <= '1';
status_reg <= "10000010";
stat_bus_we_n <= '0';
+ elsif instruction (7 downto 5) = "110" then
+ d_print("cmp");
+ elsif instruction (7 downto 5) = "111" then
+ d_print("sbc");
+ else
+ assert false
+ report ("unknow instruction") severity failure;
+ cur_cycle <= err_cycle;
end if;
- elsif instruction (7 downto 5) = "110" then
- d_print("cmp");
- elsif instruction (7 downto 5) = "111" then
- d_print("sbc");
- else
- assert false
- report ("unknow instruction") severity failure;
- cur_cycle <= err_cycle;
- end if;
- elsif instruction (1 downto 0) = "10" then
- --d_print("cc=10");
-
- if instruction (7 downto 5) = "000" then
- d_print("asl");
- elsif instruction (7 downto 5) = "001" then
- d_print("rol");
- elsif instruction (7 downto 5) = "010" then
- d_print("lsr");
- elsif instruction (7 downto 5) = "011" then
- d_print("ror");
- elsif instruction (7 downto 5) = "100" then
- d_print("stx");
- elsif instruction (7 downto 5) = "101" then
- if (cur_mode = ad_imm) then
+ elsif instruction (1 downto 0) = "10" then
+ --d_print("cc=10");
+
+ if instruction (7 downto 5) = "000" then
+ d_print("asl");
+ elsif instruction (7 downto 5) = "001" then
+ d_print("rol");
+ elsif instruction (7 downto 5) = "010" then
+ d_print("lsr");
+ elsif instruction (7 downto 5) = "011" then
+ d_print("ror");
+ elsif instruction (7 downto 5) = "100" then
+ d_print("stx");
+ elsif instruction (7 downto 5) = "101" then
d_print("ldx");
x_we_n <= '0';
--status register n/z bit update.
stat_dec_oe_n <= '1';
status_reg <= "10000010";
stat_bus_we_n <= '0';
+ elsif instruction (7 downto 5) = "110" then
+ d_print("dec");
+ elsif instruction (7 downto 5) = "111" then
+ d_print("inc");
+ else
+ assert false
+ report ("unknow instruction") severity failure;
+ cur_cycle <= err_cycle;
end if;
- elsif instruction (7 downto 5) = "110" then
- d_print("dec");
- elsif instruction (7 downto 5) = "111" then
- d_print("inc");
- else
- assert false
- report ("unknow instruction") severity failure;
- cur_cycle <= err_cycle;
- end if;
- elsif instruction (1 downto 0) = "00" then
- --d_print("cc=00 group...");
-
- if instruction (7 downto 5) = "001" then
- d_print("bit");
- elsif instruction (7 downto 5) = "010" then
- --jmp always absolute addressing
- --d_print("jmp");
- null;
- elsif instruction (7 downto 5) = "011" then
- --d_print("jmp (abs) 2");
- null;
- elsif instruction (7 downto 5) = "100" then
- d_print("sty");
- elsif instruction (7 downto 5) = "101" then
- if (cur_mode = ad_imm) then
+ elsif instruction (1 downto 0) = "00" then
+ --d_print("cc=00 group...");
+
+ if instruction (7 downto 5) = "001" then
+ d_print("bit");
+ elsif instruction (7 downto 5) = "010" then
+ --jmp always absolute addressing
+ null;
+ elsif instruction (7 downto 5) = "011" then
+ --d_print("jmp (abs) 2");
+ null;
+ elsif instruction (7 downto 5) = "100" then
+ d_print("sty");
+ elsif instruction (7 downto 5) = "101" then
d_print("ldy");
y_we_n <= '0';
--status register n/z bit update.
stat_dec_oe_n <= '1';
status_reg <= "10000010";
stat_bus_we_n <= '0';
- end if;
- elsif instruction (7 downto 5) = "110" then
- d_print("cpy");
- elsif instruction (7 downto 5) = "111" then
- d_print("cpx");
- else
- assert false
- report ("unknow instruction") severity failure;
- cur_cycle <= err_cycle;
- end if; --if instruction (7 downto 5) = "001" then
- end if; --if instruction (1 downto 0) = "01"
+ elsif instruction (7 downto 5) = "110" then
+ d_print("cpy");
+ elsif instruction (7 downto 5) = "111" then
+ d_print("cpx");
+ else
+ assert false
+ report ("unknow instruction") severity failure;
+ cur_cycle <= err_cycle;
+ end if; --if instruction (7 downto 5) = "001" then
+ end if; --if instruction (1 downto 0) = "01"
+ end if; --if (cur_mode = ad_imm)
end if; --if instruction = conv_std_logic_vector(16#00#, dsize)
end if; --if single_inst
dbuf_int_oe_n <= '1';
dl_ah_we_n <= '1';
- -----calucurate and output effective addr low
- dl_dl_oe_n <= '0';
- x_calc_n <= '0';
- ea_al_oe_n <= '0';
+ -----calucurate and output effective addr
+ x_ea_oe_n <= '0';
+ dl_al_oe_n <= '0';
dl_ah_oe_n <= '0';
+ ea_calc_n <= '0';
cur_cycle <= exec4;
end if; --if cur_mode = ad_abs then
- if instruction (1 downto 0) = "00" then
- elsif instruction (1 downto 0) = "01" then
- if instruction (7 downto 5) = "100" then
- d_print("sta 4");
- --output acc memory..
- r_nw <= '0';
- acc_d_oe_n <= '0';
- elsif instruction (7 downto 5) = "101" then
- d_print("lda 4");
- --if page boundary is crossed, redo in the next cycle.
- acc_d_we_n <= '0';
- end if;
- end if; --instruction (1 downto 0) = "00"
+ if cur_mode = ad_abs or cur_mode = ad_absx then
+ if instruction (1 downto 0) = "00" then
+ elsif instruction (1 downto 0) = "01" then
+ if instruction (7 downto 5) = "100" then
+ if cur_mode = ad_abs then
+ d_print("sta 4");
+ --output acc memory..
+ r_nw <= '0';
+ acc_d_oe_n <= '0';
+ end if;
+ elsif instruction (7 downto 5) = "101" then
+ d_print("lda 4");
+ --if page boundary is crossed, redo in the next cycle.
+ r_nw <= '1';
+ dbuf_int_oe_n <= '0';
+ acc_d_we_n <= '0';
+ end if;
+ end if; --instruction (1 downto 0) = "00"
+ end if ; --if cur_mode = ad_absx then
end if; --if instruction = conv_std_logic_vector(16#00#, dsize)
elsif cur_cycle = exec4 then
---conditional branch instruction..
else
if cur_mode = ad_absx then
- if ea_carry = '0' then
+ if ea_carry = '1' then
--case page boundary crossed.
d_print("absx 5 (page boudary crossed.)");
- dl_dl_oe_n <= '1';
+ --dl_dl_oe_n <= '1';
dl_ah_oe_n <= '1';
--increment eah.
-----effective addr low is remorized in the calc.
- dl_dh_oe_n <= '0';
- x_calc_n <= '0';
- ea_al_oe_n <= '0';
- ea_ah_oe_n <= '0';
- cur_cycle <= fetch;
+ --dl_dh_oe_n <= '0';
+ x_ea_oe_n <= '0';
+ --ea_al_oe_n <= '0';
+ --ea_ah_oe_n <= '0';
+ --cur_cycle <= fetch;
else
--case page boundary not crossed. do the fetch op.
d_print("absx 5 (fetch)");
- dl_dl_oe_n <= '1';
- x_calc_n <= '1';
- ea_al_oe_n <= '1';
+ x_ea_oe_n <= '1';
+ dl_al_oe_n <= '1';
dl_ah_oe_n <= '1';
+ ea_calc_n <= '1';
+
+ --disable last operation pin.
acc_d_we_n <= '1';
- dl_al_we_n <= '1';
+ --fetch inst.
+ ad_oe_n <= '0';
pcl_a_oe_n <= '0';
pch_a_oe_n <= '0';
- --cur_cycle <= decode;
+ inst_we_n <= '0';
+ pc_inc_n <= '0';
+ cur_cycle <= decode;
end if;
end if;
- if instruction (1 downto 0) = "00" then
- elsif instruction (1 downto 0) = "01" then
- if instruction (7 downto 5) = "100" then
- d_print("sta 5");
- --output acc memory..
- r_nw <= '0';
- acc_d_oe_n <= '0';
- elsif instruction (7 downto 5) = "101" then
- d_print("lda 5");
- --if page boundary is crossed, redo in the next cycle.
- acc_d_we_n <= '0';
- end if;
- end if; --instruction (1 downto 0) = "00"
+
+ if cur_mode = ad_absx then
+ --case page boundary is crossed
+ if instruction (1 downto 0) = "00" then
+ elsif instruction (1 downto 0) = "01" then
+ if instruction (7 downto 5) = "100" then
+ d_print("sta 5");
+ --output acc memory..
+ r_nw <= '0';
+ acc_d_oe_n <= '0';
+ elsif instruction (7 downto 5) = "101" then
+ if ea_carry = '1' then
+ --redo for page next.
+ d_print("lda 5");
+ acc_d_we_n <= '0';
+ end if;
+ end if;
+ end if; --instruction (1 downto 0) = "00"
+ end if; --if cur_mode = ad_absx and ea_carry = '1'
end if; --if instruction = conv_std_logic_vector(16#00#, dsize)
elsif cur_cycle = exec5 then
rdy : in std_logic;
instruction : in std_logic_vector (dsize - 1 downto 0);
status_reg : inout std_logic_vector (dsize - 1 downto 0);
+ inst_we_n : out std_logic;
ad_oe_n : out std_logic;
pcl_d_we_n : out std_logic;
pcl_a_we_n : out std_logic;
pch_d_oe_n : out std_logic;
pch_a_oe_n : out std_logic;
pc_inc_n : out std_logic;
- inst_we_n : out std_logic;
dbuf_int_oe_n : out std_logic;
dl_al_we_n : out std_logic;
dl_ah_we_n : out std_logic;
- dl_dl_oe_n : out std_logic;
- dl_dh_oe_n : out std_logic;
dl_al_oe_n : out std_logic;
dl_ah_oe_n : out std_logic;
sp_we_n : out std_logic;
acc_alu_oe_n : out std_logic;
x_we_n : out std_logic;
x_oe_n : out std_logic;
- x_calc_n : out std_logic;
+ x_ea_oe_n : out std_logic;
y_we_n : out std_logic;
y_oe_n : out std_logic;
- y_calc_n : out std_logic;
- ea_ah_oe_n : out std_logic;
- ea_al_oe_n : out std_logic;
+ y_ea_oe_n : out std_logic;
+ ea_calc_n : out std_logic;
+ ea_zp_n : out std_logic;
+ ea_pg_next_n : out std_logic;
ea_carry : in std_logic;
stat_dec_we_n : out std_logic;
stat_dec_oe_n : out std_logic;
dsize : integer := 8
);
port (
- int_al_we_n : in std_logic;
- int_ah_we_n : in std_logic;
- int_dl_oe_n : in std_logic;
- int_dh_oe_n : in std_logic;
- int_al_oe_n : in std_logic;
- int_ah_oe_n : in std_logic;
- int_dbus : inout std_logic_vector (dsize - 1 downto 0);
- int_abus_l : out std_logic_vector (dsize - 1 downto 0);
- int_abus_h : out std_logic_vector (dsize - 1 downto 0)
+ al_we_n : in std_logic;
+ ah_we_n : in std_logic;
+ al_oe_n : in std_logic;
+ ah_oe_n : in std_logic;
+ int_dbus : in std_logic_vector (dsize - 1 downto 0);
+ ea_al : out std_logic_vector (dsize - 1 downto 0);
+ ea_ah : out std_logic_vector (dsize - 1 downto 0)
);
end component;
);
end component;
+ component index_reg
+ generic (
+ dsize : integer := 8
+ );
+ port (
+ clk : in std_logic;
+ d_we_n : in std_logic;
+ d_oe_n : in std_logic;
+ ea_oe_n : in std_logic;
+ int_dbus : inout std_logic_vector (dsize - 1 downto 0);
+ ea_bus : out std_logic_vector (dsize - 1 downto 0)
+ );
+ end component;
+
component effective_adder
generic ( dsize : integer := 8
);
port (
- clk : in std_logic;
- ah_oe_n : in std_logic;
- al_oe_n : in std_logic;
- base : in std_logic_vector (dsize - 1 downto 0);
+ clk : in std_logic;
+ ea_calc_n : in std_logic;
+ zp_n : in std_logic;
+ pg_next_n : in std_logic;
+ base_l : in std_logic_vector (dsize - 1 downto 0);
+ base_h : in std_logic_vector (dsize - 1 downto 0);
index : in std_logic_vector (dsize - 1 downto 0);
ah_bus : out std_logic_vector (dsize - 1 downto 0);
al_bus : out std_logic_vector (dsize - 1 downto 0);
signal dbuf_int_oe_n : std_logic;
signal dl_al_we_n : std_logic;
signal dl_ah_we_n : std_logic;
- signal dl_dl_oe_n : std_logic;
- signal dl_dh_oe_n : std_logic;
signal dl_al_oe_n : std_logic;
signal dl_ah_oe_n : std_logic;
signal x_we_n : std_logic;
signal x_oe_n : std_logic;
- signal x_out : std_logic_vector(dsize - 1 downto 0);
signal y_we_n : std_logic;
signal y_oe_n : std_logic;
- signal y_out : std_logic_vector(dsize - 1 downto 0);
- signal ea_ah_oe_n : std_logic;
- signal ea_al_oe_n : std_logic;
+ signal ea_base_l : std_logic_vector(dsize - 1 downto 0);
+ signal ea_base_h : std_logic_vector(dsize - 1 downto 0);
+ signal ea_calc_n : std_logic;
+ signal ea_zp_n : std_logic;
+ signal ea_pg_next_n : std_logic;
signal ea_carry : std_logic;
- signal x_calc_n : std_logic;
- signal y_calc_n : std_logic;
- signal addr_index : std_logic_vector(dsize - 1 downto 0);
+ signal ea_index : std_logic_vector(dsize - 1 downto 0);
+ signal x_ea_oe_n : std_logic;
+ signal y_ea_oe_n : std_logic;
signal stat_dec_we_n : std_logic;
signal stat_dec_oe_n : std_logic;
rdy,
instruction,
status_reg,
+ inst_we_n,
ad_oe_n,
pcl_d_we_n,
pcl_a_we_n,
pch_d_oe_n,
pch_a_oe_n,
pc_inc_n,
- inst_we_n,
dbuf_int_oe_n,
dl_al_we_n,
dl_ah_we_n,
- dl_dl_oe_n,
- dl_dh_oe_n,
dl_al_oe_n,
dl_ah_oe_n,
sp_we_n,
acc_alu_oe_n,
x_we_n,
x_oe_n,
- x_calc_n,
+ x_ea_oe_n,
y_we_n,
y_oe_n,
- y_calc_n,
- ea_ah_oe_n,
- ea_al_oe_n,
+ y_ea_oe_n,
+ ea_calc_n,
+ ea_zp_n,
+ ea_pg_next_n,
ea_carry,
stat_dec_we_n,
stat_dec_oe_n,
data_bus_buffer : dbus_buf generic map (dsize)
port map(set_clk, dbuf_r_nw, dbuf_int_oe_n, internal_dbus, d_io);
- input_data_latch : input_dl generic map (dsize)
- port map(dl_al_we_n, dl_ah_we_n, dl_dl_oe_n, dl_dh_oe_n,
- dl_al_oe_n, dl_ah_oe_n,
- internal_dbus, internal_abus_l, internal_abus_h);
-
stack_pointer : sp generic map (dsize)
port map(trigger_clk, sp_we_n, sp_push_n, sp_pop_n,
sp_int_d_oe_n, sp_int_a_oe_n,
stat_alu_c, stat_alu_v,
status_reg, internal_dbus);
- --x/y output pin is connected to address calcurator
- x_reg : dff generic map (dsize)
- port map(trigger_clk, x_we_n, '0', internal_dbus, x_out);
- x_buf : tsb generic map (dsize)
- port map (x_oe_n, x_out, internal_dbus);
- x_buf_addr : tsb generic map (dsize)
- port map (x_calc_n, x_out, addr_index);
-
- y_reg : dff generic map (dsize)
- port map(trigger_clk, y_we_n, '0', internal_dbus, y_out);
- y_buf : tsb generic map (dsize)
- port map (y_oe_n, y_out, internal_dbus);
- y_buf_addr : tsb generic map (dsize)
- port map (y_calc_n, y_out, addr_index);
+ --x/y output pin is connected to effective address calcurator
+ x_reg : index_reg generic map (dsize)
+ port map(trigger_clk, x_we_n, x_oe_n, x_ea_oe_n, internal_dbus, ea_index);
+
+ y_reg : index_reg generic map (dsize)
+ port map(trigger_clk, y_we_n, y_oe_n, y_ea_oe_n, internal_dbus, ea_index);
+
+ --address operand data latch.
+ input_data_latch : input_dl generic map (dsize)
+ port map(dl_al_we_n, dl_ah_we_n, dl_al_oe_n, dl_ah_oe_n,
+ internal_dbus, ea_base_l, ea_base_h);
---effective addres calcurator.
- addr_calc: effective_adder generic map (dsize)
- port map (trigger_clk, ea_ah_oe_n, ea_al_oe_n,
- internal_dbus, addr_index,
+ ea_calc: effective_adder generic map (dsize)
+ port map (trigger_clk, ea_calc_n, ea_zp_n, ea_pg_next_n,
+ ea_base_l, ea_base_h, ea_index,
internal_abus_h, internal_abus_l, ea_carry);
acc_reg : accumulator generic map (dsize)
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