#define INSTRUCTION_SPECIFIER_FIELDS \
struct OperandSpecifier operands[X86_MAX_OPERANDS]; \
- bool filtered; \
InstructionContext insnContext; \
std::string name; \
\
InstructionSpecifier() { \
- filtered = false; \
insnContext = IC; \
name = ""; \
memset(operands, 0, sizeof(operands)); \
InstructionSpecifier &previousInfo =
InstructionSpecifiers[decision.instructionIDs[index]];
- if(newInfo.filtered)
- continue; // filtered instructions get lowest priority
-
// Instructions such as MOV8ao8 and MOV8ao8_16 differ only in the
// presence of the AdSize prefix. However, the disassembler doesn't
// care about that difference in the instruction definition; it
if (outranks(previousInfo.insnContext, newInfo.insnContext))
continue;
- if (previousInfo.insnContext == newInfo.insnContext &&
- !previousInfo.filtered) {
+ if (previousInfo.insnContext == newInfo.insnContext) {
errs() << "Error: Primary decode conflict: ";
errs() << newInfo.name << " would overwrite " << previousInfo.name;
errs() << "\n";
}
}
+ if (Form == X86Local::Pseudo || (IsCodeGenOnly && !ForceDisassemble)) {
+ ShouldBeEmitted = false;
+ return;
+ }
+
+ // Special case since there is no attribute class for 64-bit and VEX
+ if (Name == "VMASKMOVDQU64") {
+ ShouldBeEmitted = false;
+ return;
+ }
+
ShouldBeEmitted = true;
}
RecognizableInstr recogInstr(tables, insn, uid);
- recogInstr.emitInstructionSpecifier();
-
- if (recogInstr.shouldBeEmitted())
+ if (recogInstr.shouldBeEmitted()) {
+ recogInstr.emitInstructionSpecifier();
recogInstr.emitDecodePath(tables);
+ }
}
#define EVEX_KB(n) (HasEVEX_KZ && HasEVEX_B ? n##_KZ_B : \
return insnContext;
}
-RecognizableInstr::filter_ret RecognizableInstr::filter() const {
- ///////////////////
- // FILTER_STRONG
- //
-
- // Filter out intrinsics
-
- assert(Rec->isSubClassOf("X86Inst") && "Can only filter X86 instructions");
-
- if (Form == X86Local::Pseudo || (IsCodeGenOnly && !ForceDisassemble))
- return FILTER_STRONG;
-
-
- // Filter out artificial instructions but leave in the LOCK_PREFIX so it is
- // printed as a separate "instruction".
-
-
- /////////////////
- // FILTER_WEAK
- //
-
-
- // Special cases.
-
- if (Name == "VMASKMOVDQU64")
- return FILTER_WEAK;
-
- return FILTER_NORMAL;
-}
-
void RecognizableInstr::handleOperand(bool optional, unsigned &operandIndex,
unsigned &physicalOperandIndex,
unsigned &numPhysicalOperands,
void RecognizableInstr::emitInstructionSpecifier() {
Spec->name = Name;
- if (!ShouldBeEmitted)
- return;
-
- switch (filter()) {
- case FILTER_WEAK:
- Spec->filtered = true;
- break;
- case FILTER_STRONG:
- ShouldBeEmitted = false;
- return;
- case FILTER_NORMAL:
- break;
- }
-
Spec->insnContext = insnContext();
const std::vector<CGIOperandList::OperandInfo> &OperandList = *Operands;
///
/// @return - The context in which the instruction is valid.
InstructionContext insnContext() const;
-
- enum filter_ret {
- FILTER_STRONG, // instruction has no place in the instruction tables
- FILTER_WEAK, // instruction may conflict, and should be eliminated if
- // it does
- FILTER_NORMAL // instruction should have high priority and generate an
- // error if it conflcits with any other FILTER_NORMAL
- // instruction
- };
-
- /// filter - Determines whether the instruction should be decodable. Some
- /// instructions are pure intrinsics and use unencodable operands; many
- /// synthetic instructions are duplicates of other instructions; other
- /// instructions only differ in the logical way in which they are used, and
- /// have the same decoding. Because these would cause decode conflicts,
- /// they must be filtered out.
- ///
- /// @return - The degree of filtering to be applied (see filter_ret).
- filter_ret filter() const;
/// hasFROperands - Returns true if any operand is a FR operand.
bool hasFROperands() const;