r600g: convert the remnants of VGT state into immediate register writes/atoms v4

v2: Group vgt register together to avoid lockup
v3: Split multi primitive register and index bias register
v4: Bump R600_NUM_ATOMS

Signed-off-by: Marek Olšák <maraeo@gmail.com>
Signed-off-by: Jerome Glisse <jglisse@redhat.com>

diff --git a/src/gallium/drivers/r600/evergreen_hw_context.c b/src/gallium/drivers/r600/evergreen_hw_context.c
index 483021f..0c2159a 100644 (file)
--- a/src/gallium/drivers/r600/evergreen_hw_context.c
+++ b/src/gallium/drivers/r600/evergreen_hw_context.c
@@ -32,10 +32,6 @@ static const struct r600_reg cayman_config_reg_list[] = {
        {R_00913C_SPI_CONFIG_CNTL_1, REG_FLAG_ENABLE_ALWAYS | REG_FLAG_FLUSH_CHANGE, 0},
 };
 
-static const struct r600_reg evergreen_ctl_const_list[] = {
-       {R_03CFF4_SQ_VTX_START_INST_LOC, 0, 0},
-};
-
 static const struct r600_reg evergreen_context_reg_list[] = {
        {R_028008_DB_DEPTH_VIEW, 0, 0},
        {R_028010_DB_RENDER_OVERRIDE2, 0, 0},
@@ -63,10 +59,6 @@ static const struct r600_reg evergreen_context_reg_list[] = {
        {R_028254_PA_SC_VPORT_SCISSOR_0_BR, 0, 0},
        {R_028350_SX_MISC, 0, 0},
        {GROUP_FORCE_NEW_BLOCK, 0, 0},
-       {R_028408_VGT_INDX_OFFSET, 0, 0},
-       {R_02840C_VGT_MULTI_PRIM_IB_RESET_INDX, 0, 0},
-       {R_028A94_VGT_MULTI_PRIM_IB_RESET_EN, 0, 0},
-       {GROUP_FORCE_NEW_BLOCK, 0, 0},
        {R_02861C_SPI_VS_OUT_ID_0, 0, 0},
        {R_028620_SPI_VS_OUT_ID_1, 0, 0},
        {R_028624_SPI_VS_OUT_ID_2, 0, 0},
@@ -353,10 +345,6 @@ static const struct r600_reg cayman_context_reg_list[] = {
        {R_028254_PA_SC_VPORT_SCISSOR_0_BR, 0, 0},
        {R_028350_SX_MISC, 0, 0},
        {GROUP_FORCE_NEW_BLOCK, 0, 0},
-       {R_028408_VGT_INDX_OFFSET, 0, 0},
-       {R_02840C_VGT_MULTI_PRIM_IB_RESET_INDX, 0, 0},
-       {R_028A94_VGT_MULTI_PRIM_IB_RESET_EN, 0, 0},
-       {GROUP_FORCE_NEW_BLOCK, 0, 0},
        {R_02861C_SPI_VS_OUT_ID_0, 0, 0},
        {R_028620_SPI_VS_OUT_ID_1, 0, 0},
        {R_028624_SPI_VS_OUT_ID_2, 0, 0},
@@ -664,10 +652,6 @@ int evergreen_context_init(struct r600_context *ctx)
                                           Elements(evergreen_context_reg_list), PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET);
        if (r)
                goto out_err;
-       r = r600_context_add_block(ctx, evergreen_ctl_const_list,
-                                  Elements(evergreen_ctl_const_list), PKT3_SET_CTL_CONST, EVERGREEN_CTL_CONST_OFFSET);
-       if (r)
-               goto out_err;
 
        /* PS loop const */
        evergreen_loop_const_init(ctx, 0);

diff --git a/src/gallium/drivers/r600/evergreen_state.c b/src/gallium/drivers/r600/evergreen_state.c
index bd378d9..56df174 100644 (file)
--- a/src/gallium/drivers/r600/evergreen_state.c
+++ b/src/gallium/drivers/r600/evergreen_state.c
@@ -2150,6 +2150,9 @@ void evergreen_init_state_functions(struct r600_context *rctx)
        r600_init_atom(rctx, &rctx->samplers[PIPE_SHADER_GEOMETRY].views.atom, id++, evergreen_emit_gs_sampler_views, 0);
        r600_init_atom(rctx, &rctx->samplers[PIPE_SHADER_FRAGMENT].views.atom, id++, evergreen_emit_ps_sampler_views, 0);
 
+       r600_init_atom(rctx, &rctx->vgt_state.atom, id++, r600_emit_vgt_state, 6);
+       r600_init_atom(rctx, &rctx->vgt2_state.atom, id++, r600_emit_vgt2_state, 3);
+
        if (rctx->chip_class == EVERGREEN) {
                r600_init_atom(rctx, &rctx->sample_mask.atom, id++, evergreen_emit_sample_mask, 3);
        } else {

diff --git a/src/gallium/drivers/r600/r600.h b/src/gallium/drivers/r600/r600.h
index 6363a03..83d21a4 100644 (file)
--- a/src/gallium/drivers/r600/r600.h
+++ b/src/gallium/drivers/r600/r600.h
@@ -228,11 +228,4 @@ void _r600_pipe_state_add_reg(struct r600_context *ctx,
 #define r600_pipe_state_add_reg_bo(state, offset, value, bo, usage) _r600_pipe_state_add_reg_bo(rctx, state, offset, value, CTX_RANGE_ID(offset), CTX_BLOCK_ID(offset), bo, usage)
 #define r600_pipe_state_add_reg(state, offset, value) _r600_pipe_state_add_reg(rctx, state, offset, value, CTX_RANGE_ID(offset), CTX_BLOCK_ID(offset))
 
-static inline void r600_pipe_state_mod_reg(struct r600_pipe_state *state,
-                                          uint32_t value)
-{
-       state->regs[state->nregs].value = value;
-       state->nregs++;
-}
-
 #endif

diff --git a/src/gallium/drivers/r600/r600_hw_context.c b/src/gallium/drivers/r600/r600_hw_context.c
index 57dcc7e..e9369de 100644 (file)
--- a/src/gallium/drivers/r600/r600_hw_context.c
+++ b/src/gallium/drivers/r600/r600_hw_context.c
@@ -233,10 +233,6 @@ static const struct r600_reg r600_config_reg_list[] = {
        {R_008C04_SQ_GPR_RESOURCE_MGMT_1, REG_FLAG_ENABLE_ALWAYS | REG_FLAG_FLUSH_CHANGE, 0},
 };
 
-static const struct r600_reg r600_ctl_const_list[] = {
-       {R_03CFF4_SQ_VTX_START_INST_LOC, 0, 0},
-};
-
 static const struct r600_reg r600_context_reg_list[] = {
        {R_028A4C_PA_SC_MODE_CNTL, 0, 0},
        {GROUP_FORCE_NEW_BLOCK, 0, 0},
@@ -461,9 +457,6 @@ static const struct r600_reg r600_context_reg_list[] = {
        {GROUP_FORCE_NEW_BLOCK, 0, 0},
        {R_028850_SQ_PGM_RESOURCES_PS, 0, 0},
        {R_028854_SQ_PGM_EXPORTS_PS, 0, 0},
-       {R_028408_VGT_INDX_OFFSET, 0, 0},
-       {R_02840C_VGT_MULTI_PRIM_IB_RESET_INDX, 0, 0},
-       {R_028A94_VGT_MULTI_PRIM_IB_RESET_EN, 0, 0},
        {R_028C1C_PA_SC_AA_SAMPLE_LOCS_MCTX, 0, 0},
        {R_028C20_PA_SC_AA_SAMPLE_LOCS_8S_WD1_MCTX, 0, 0},
 };
@@ -555,10 +548,6 @@ int r600_context_init(struct r600_context *ctx)
                                   Elements(r600_context_reg_list), PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET);
        if (r)
                goto out_err;
-       r = r600_context_add_block(ctx, r600_ctl_const_list,
-                                  Elements(r600_ctl_const_list), PKT3_SET_CTL_CONST, R600_CTL_CONST_OFFSET);
-       if (r)
-               goto out_err;
 
        /* PS loop const */
        r600_loop_const_init(ctx, 0);
@@ -1017,6 +1006,8 @@ void r600_begin_new_cs(struct r600_context *ctx)
        r600_atom_dirty(ctx, &ctx->clip_misc_state.atom);
        r600_atom_dirty(ctx, &ctx->clip_state.atom);
        r600_atom_dirty(ctx, &ctx->db_misc_state.atom);
+       r600_atom_dirty(ctx, &ctx->vgt_state.atom);
+       r600_atom_dirty(ctx, &ctx->vgt2_state.atom);
        r600_atom_dirty(ctx, &ctx->sample_mask.atom);
        r600_atom_dirty(ctx, &ctx->stencil_ref.atom);
        r600_atom_dirty(ctx, &ctx->viewport.atom);
@@ -1067,8 +1058,9 @@ void r600_begin_new_cs(struct r600_context *ctx)
                enable_block->nreg_dirty = enable_block->nreg;
        }
 
-       /* Re-emit the primitive type. */
+       /* Re-emit the draw state. */
        ctx->last_primitive_type = -1;
+       ctx->last_start_instance = -1;
 }
 
 void r600_context_emit_fence(struct r600_context *ctx, struct r600_resource *fence_bo, unsigned offset, unsigned value)

diff --git a/src/gallium/drivers/r600/r600_hw_context_priv.h b/src/gallium/drivers/r600/r600_hw_context_priv.h
index 3326963..996bfaa 100644 (file)
--- a/src/gallium/drivers/r600/r600_hw_context_priv.h
+++ b/src/gallium/drivers/r600/r600_hw_context_priv.h
@@ -30,7 +30,7 @@
 
 /* the number of CS dwords for flushing and drawing */
 #define R600_MAX_FLUSH_CS_DWORDS 44
-#define R600_MAX_DRAW_CS_DWORDS 22
+#define R600_MAX_DRAW_CS_DWORDS 34
 
 /* these flags are used in register flags and added into block flags */
 #define REG_FLAG_NEED_BO 1

diff --git a/src/gallium/drivers/r600/r600_pipe.h b/src/gallium/drivers/r600/r600_pipe.h
index 27d57d1..a60a498 100644 (file)
--- a/src/gallium/drivers/r600/r600_pipe.h
+++ b/src/gallium/drivers/r600/r600_pipe.h
@@ -35,7 +35,7 @@
 #include "r600_resource.h"
 #include "evergreen_compute.h"
 
-#define R600_NUM_ATOMS 25
+#define R600_NUM_ATOMS 28
 
 #define R600_MAX_CONST_BUFFERS 2
 #define R600_MAX_CONST_BUFFER_SIZE 4096
@@ -100,6 +100,17 @@ struct r600_alphatest_state {
        bool cb0_export_16bpc; /* from set_framebuffer_state */
 };
 
+struct r600_vgt_state {
+       struct r600_atom atom;
+       uint32_t vgt_multi_prim_ib_reset_en;
+       uint32_t vgt_multi_prim_ib_reset_indx;
+};
+
+struct r600_vgt2_state {
+       struct r600_atom atom;
+       uint32_t vgt_indx_offset;
+};
+
 struct r600_blend_color {
        struct r600_atom atom;
        struct pipe_blend_color state;
@@ -142,7 +153,6 @@ enum r600_pipe_state_id {
        R600_PIPE_STATE_BLEND = 0,
        R600_PIPE_STATE_SCISSOR,
        R600_PIPE_STATE_RASTERIZER,
-       R600_PIPE_STATE_VGT,
        R600_PIPE_STATE_FRAMEBUFFER,
        R600_PIPE_STATE_DSA,
        R600_PIPE_STATE_POLYGON_OFFSET,
@@ -356,7 +366,6 @@ struct r600_context {
        struct r600_pipe_shader_selector        *ps_shader;
        struct r600_pipe_shader_selector        *vs_shader;
        struct r600_pipe_rasterizer     *rasterizer;
-       struct r600_pipe_state          vgt;
        struct r600_pipe_state          spi;
        struct pipe_query               *current_render_cond;
        unsigned                        current_render_cond_mode;
@@ -395,6 +404,8 @@ struct r600_context {
        struct r600_db_misc_state       db_misc_state;
        struct r600_seamless_cube_map   seamless_cube_map;
        struct r600_stencil_ref_state   stencil_ref;
+       struct r600_vgt_state           vgt_state;
+       struct r600_vgt2_state          vgt2_state;
        struct r600_sample_mask         sample_mask;
        struct r600_viewport_state      viewport;
        /* Shaders and shader resources. */
@@ -476,8 +487,9 @@ struct r600_context {
        struct r600_resource *dummy_fmask;
        struct r600_resource *dummy_cmask;
 
-       /* Last primitive type used in draw_vbo. */
-       int last_primitive_type;
+       /* Last draw state (-1 = unset). */
+       int                     last_primitive_type; /* Last primitive type used in draw_vbo. */
+       int                     last_start_instance;
 };
 
 static INLINE void r600_emit_atom(struct r600_context *rctx, struct r600_atom *atom)
@@ -601,6 +613,8 @@ void r600_translate_index_buffer(struct r600_context *r600,
 void r600_init_common_state_functions(struct r600_context *rctx);
 void r600_emit_alphatest_state(struct r600_context *rctx, struct r600_atom *atom);
 void r600_emit_blend_color(struct r600_context *rctx, struct r600_atom *atom);
+void r600_emit_vgt_state(struct r600_context *rctx, struct r600_atom *atom);
+void r600_emit_vgt2_state(struct r600_context *rctx, struct r600_atom *atom);
 void r600_emit_clip_misc_state(struct r600_context *rctx, struct r600_atom *atom);
 void r600_emit_stencil_ref(struct r600_context *rctx, struct r600_atom *atom);
 void r600_emit_viewport_state(struct r600_context *rctx, struct r600_atom *atom);

diff --git a/src/gallium/drivers/r600/r600_state.c b/src/gallium/drivers/r600/r600_state.c
index af25d6d..e299a8b 100644 (file)
--- a/src/gallium/drivers/r600/r600_state.c
+++ b/src/gallium/drivers/r600/r600_state.c
@@ -2034,6 +2034,9 @@ void r600_init_state_functions(struct r600_context *rctx)
        r600_init_atom(rctx, &rctx->samplers[PIPE_SHADER_FRAGMENT].views.atom, id++, r600_emit_ps_sampler_views, 0);
        r600_init_atom(rctx, &rctx->vertex_buffer_state.atom, id++, r600_emit_vertex_buffers, 0);
 
+       r600_init_atom(rctx, &rctx->vgt_state.atom, id++, r600_emit_vgt_state, 6);
+       r600_init_atom(rctx, &rctx->vgt2_state.atom, id++, r600_emit_vgt2_state, 3);
+
        r600_init_atom(rctx, &rctx->seamless_cube_map.atom, id++, r600_emit_seamless_cube_map, 3);
        r600_init_atom(rctx, &rctx->sample_mask.atom, id++, r600_emit_sample_mask, 3);
        rctx->sample_mask.sample_mask = ~0;

diff --git a/src/gallium/drivers/r600/r600_state_common.c b/src/gallium/drivers/r600/r600_state_common.c
index 8ff0cdf..635804c 100644 (file)
--- a/src/gallium/drivers/r600/r600_state_common.c
+++ b/src/gallium/drivers/r600/r600_state_common.c
@@ -188,6 +188,23 @@ void r600_emit_blend_color(struct r600_context *rctx, struct r600_atom *atom)
        r600_write_value(cs, fui(state->color[3])); /* R_028420_CB_BLEND_ALPHA */
 }
 
+void r600_emit_vgt_state(struct r600_context *rctx, struct r600_atom *atom)
+{
+       struct radeon_winsys_cs *cs = rctx->cs;
+       struct r600_vgt_state *a = (struct r600_vgt_state *)atom;
+
+       r600_write_context_reg(cs, R_028A94_VGT_MULTI_PRIM_IB_RESET_EN, a->vgt_multi_prim_ib_reset_en);
+       r600_write_context_reg(cs, R_02840C_VGT_MULTI_PRIM_IB_RESET_INDX, a->vgt_multi_prim_ib_reset_indx);
+}
+
+void r600_emit_vgt2_state(struct r600_context *rctx, struct r600_atom *atom)
+{
+       struct radeon_winsys_cs *cs = rctx->cs;
+       struct r600_vgt2_state *a = (struct r600_vgt2_state *)atom;
+
+       r600_write_context_reg(cs, R_028408_VGT_INDX_OFFSET, a->vgt_indx_offset);
+}
+
 static void r600_set_clip_state(struct pipe_context *ctx,
                                const struct pipe_clip_state *state)
 {
@@ -1197,28 +1214,24 @@ static void r600_draw_vbo(struct pipe_context *ctx, const struct pipe_draw_info
                info.index_bias = info.start;
        }
 
-       if (rctx->vgt.id != R600_PIPE_STATE_VGT) {
-               rctx->vgt.id = R600_PIPE_STATE_VGT;
-               rctx->vgt.nregs = 0;
-               r600_pipe_state_add_reg(&rctx->vgt, R_028408_VGT_INDX_OFFSET, info.index_bias);
-               r600_pipe_state_add_reg(&rctx->vgt, R_02840C_VGT_MULTI_PRIM_IB_RESET_INDX, info.restart_index);
-               r600_pipe_state_add_reg(&rctx->vgt, R_028A94_VGT_MULTI_PRIM_IB_RESET_EN, info.primitive_restart);
-               r600_pipe_state_add_reg(&rctx->vgt, R_03CFF4_SQ_VTX_START_INST_LOC, info.start_instance);
-       }
-
-       rctx->vgt.nregs = 0;
-       r600_pipe_state_mod_reg(&rctx->vgt, info.index_bias);
-       r600_pipe_state_mod_reg(&rctx->vgt, info.restart_index);
-       r600_pipe_state_mod_reg(&rctx->vgt, info.primitive_restart);
-       r600_pipe_state_mod_reg(&rctx->vgt, info.start_instance);
-       r600_context_pipe_state_set(rctx, &rctx->vgt);
-
        /* Enable stream out if needed. */
        if (rctx->streamout_start) {
                r600_context_streamout_begin(rctx);
                rctx->streamout_start = FALSE;
        }
 
+       /* Set the index offset and multi primitive */
+       if (rctx->vgt2_state.vgt_indx_offset != info.index_bias) {
+               rctx->vgt2_state.vgt_indx_offset = info.index_bias;
+               r600_atom_dirty(rctx, &rctx->vgt2_state.atom);
+       }
+       if (rctx->vgt_state.vgt_multi_prim_ib_reset_en != info.primitive_restart ||
+           rctx->vgt_state.vgt_multi_prim_ib_reset_indx != info.restart_index) {
+               rctx->vgt_state.vgt_multi_prim_ib_reset_en = info.primitive_restart;
+               rctx->vgt_state.vgt_multi_prim_ib_reset_indx = info.restart_index;
+               r600_atom_dirty(rctx, &rctx->vgt_state.atom);
+       }
+
        /* Emit states (the function expects that we emit at most 17 dwords here). */
        r600_need_cs_space(rctx, 0, TRUE);
        r600_flush_emit(rctx);
@@ -1234,6 +1247,12 @@ static void r600_draw_vbo(struct pipe_context *ctx, const struct pipe_draw_info
        }
        rctx->pm4_dirty_cdwords = 0;
 
+       /* Update start instance. */
+       if (rctx->last_start_instance != info.start_instance) {
+               r600_write_ctl_const(cs, R_03CFF4_SQ_VTX_START_INST_LOC, info.start_instance);
+               rctx->last_start_instance = info.start_instance;
+       }
+
        /* Update the primitive type. */
        if (rctx->last_primitive_type != info.mode) {
                unsigned ls_mask = 0;