#if 1
// AF送信を開始する。ただし、送信DMA割り込みはまだ発生しない。
*pDMA2_CONFIG |= DMAEN; // TX SPORT DMA Enable
- *pSPORT0_TCR1 |= RSPEN; // TX SPORT Enable
+ *pSPORT0_TCR1 |= TSPEN; // TX SPORT Enable
ssync();
+
+
tslp_tsk(1); // DMAがFIFOを充填するのに十分な時間待つ。
syscall(act_tsk(TASK_AF)); // AFデータ送信タスクをアクティブにする
while(1)
{
tslp_tsk(1000);
- syslog( LOG_INFO, "TX: %d, RX: %d", debug_tx_counter, debug_rx_counter );
+ syslog( LOG_INFO, "TX: %d, RX: %d, lenght: %d", debug_tx_counter, debug_rx_counter, debug_counter );
+ syslog( LOG_NOTICE, "SPORT0_TCR1 %04x", *pSPORT0_TCR1);
+ syslog( LOG_NOTICE, "SPORT0_TCR2 %04x", *pSPORT0_TCR2);
+ syslog( LOG_NOTICE, "SPORT0_STAT %04x", *pSPORT0_STAT);
+ syslog( LOG_NOTICE, "SPORT0_TCLKDIV %04x", *pSPORT0_TCLKDIV);
+ syslog( LOG_NOTICE, "SPORT0_TFSDIV %04x", *pSPORT0_TFSDIV);
}
ssync();
debug_rx_counter++;
- debug_counter-=0;
+ debug_counter+=4;
}
// ペリフェラルへの書き込みを待つ。
ssync();
- debug_counter++;//=AF_BUFSIZE/2;
+ debug_counter-=2;
debug_tx_counter++;
}
0 << 9 | // RSFESE, 0:normal frame sync, 1:LR frame clock
1 << 8 | // RXSE, 0:secondary ch disable, 1:secondary ch enable
29 << 0 ; // SLEN 0-1:not allowed,2-31:Serial word length - 1
+
ssync();
0 << 12 | // LTFS, 0:Active high TFS, 1:Active low TFS
0 << 11 | // DITFS, 0:data dependent TFS generation, 1:data independent TFS generation
1 << 10 | // TFSR, 0:TFS is not required every word, 1:TFS is required every word
- 0 << 9 | // ITFS, 0:external TFS, 1:internal TFS
+ 1 << 9 | // ITFS, 0:external TFS, 1:internal TFS
0 << 4 | // TLSBIT, 0:MSB first transmission, 1:LSB first transmission
0 << 2 | // TDTYPE 0:normal, 1:reserved, 2:u-law, 3:a-law
0 << 1 | // ITCLK, 0:external clock generation, 1:internal clock generation
1 << 8 | // TXSE, 0:secondary ch disable, 1:secondary ch enable
30 << 0 ; // SLEN 0-1:not allowed,2-31:Serial word length - 1
+ *pSPORT0_TFSDIV = 255; // TFS period -1 ( The period is 256 )
+
// 送信DMAデスクリプタを作る
// 注意:制御の都合上、最初はDMA割り込みをオフにしておく。これは