[TableGen] Remove ListInit::size() in favor of getSize() which does the same thing...

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@237341 91177308-0d34-0410-b5e6-96231b3b80d8

diff --git a/include/llvm/TableGen/Record.h b/include/llvm/TableGen/Record.h
index e1f89d1..b20f29c 100644 (file)
--- a/include/llvm/TableGen/Record.h
+++ b/include/llvm/TableGen/Record.h
@@ -842,7 +842,6 @@ public:
   inline const_iterator begin() const { return Values.begin(); }
   inline const_iterator end  () const { return Values.end();   }
 
-  inline size_t         size () const { return Values.size();  }
   inline bool           empty() const { return Values.empty(); }
 
   /// resolveListElementReference - This method is used to implement

diff --git a/utils/TableGen/CodeGenRegisters.cpp b/utils/TableGen/CodeGenRegisters.cpp
index 8d6d3d1..c6940e9 100644 (file)
--- a/utils/TableGen/CodeGenRegisters.cpp
+++ b/utils/TableGen/CodeGenRegisters.cpp
@@ -676,7 +676,7 @@ CodeGenRegisterClass::CodeGenRegisterClass(CodeGenRegBank &RegBank, Record *R)
   // Allocation order 0 is the full set. AltOrders provides others.
   const SetTheory::RecVec *Elements = RegBank.getSets().expand(R);
   ListInit *AltOrders = R->getValueAsListInit("AltOrders");
-  Orders.resize(1 + AltOrders->size());
+  Orders.resize(1 + AltOrders->getSize());
 
   // Default allocation order always contains all registers.
   for (unsigned i = 0, e = Elements->size(); i != e; ++i) {
@@ -689,7 +689,7 @@ CodeGenRegisterClass::CodeGenRegisterClass(CodeGenRegBank &RegBank, Record *R)
 
   // Alternative allocation orders may be subsets.
   SetTheory::RecSet Order;
-  for (unsigned i = 0, e = AltOrders->size(); i != e; ++i) {
+  for (unsigned i = 0, e = AltOrders->getSize(); i != e; ++i) {
     RegBank.getSets().evaluate(AltOrders->getElement(i), Order, R->getLoc());
     Orders[1 + i].append(Order.begin(), Order.end());
     // Verify that all altorder members are regclass members.