OSDN Git Service

e1000e: Add support for the next LOM generation
authorSasha Neftin <sasha.neftin@intel.com>
Tue, 18 Jul 2023 16:28:57 +0000 (19:28 +0300)
committerTony Nguyen <anthony.l.nguyen@intel.com>
Thu, 24 Aug 2023 19:55:25 +0000 (12:55 -0700)
Add devices IDs for the next LOM generations that will be available on the
next Intel Client platforms. This patch provides the initial support for
these devices.

Signed-off-by: Sasha Neftin <sasha.neftin@intel.com>
Tested-by: Naama Meir <naamax.meir@linux.intel.com>
Signed-off-by: Tony Nguyen <anthony.l.nguyen@intel.com>
drivers/net/ethernet/intel/e1000e/ethtool.c
drivers/net/ethernet/intel/e1000e/hw.h
drivers/net/ethernet/intel/e1000e/ich8lan.c
drivers/net/ethernet/intel/e1000e/netdev.c
drivers/net/ethernet/intel/e1000e/ptp.c

index 721f86f..9835e6a 100644 (file)
@@ -917,6 +917,7 @@ static int e1000_reg_test(struct e1000_adapter *adapter, u64 *data)
        case e1000_pch_mtp:
        case e1000_pch_lnp:
        case e1000_pch_ptp:
+       case e1000_pch_nvp:
                mask |= BIT(18);
                break;
        default:
@@ -1585,6 +1586,7 @@ static void e1000_loopback_cleanup(struct e1000_adapter *adapter)
        case e1000_pch_mtp:
        case e1000_pch_lnp:
        case e1000_pch_ptp:
+       case e1000_pch_nvp:
                fext_nvm11 = er32(FEXTNVM11);
                fext_nvm11 &= ~E1000_FEXTNVM11_DISABLE_MULR_FIX;
                ew32(FEXTNVM11, fext_nvm11);
index 29f9fae..1fef6bb 100644 (file)
@@ -122,6 +122,8 @@ struct e1000_hw;
 #define E1000_DEV_ID_PCH_PTP_I219_V26          0x57B6
 #define E1000_DEV_ID_PCH_PTP_I219_LM27         0x57B7
 #define E1000_DEV_ID_PCH_PTP_I219_V27          0x57B8
+#define E1000_DEV_ID_PCH_NVL_I219_LM29         0x57B9
+#define E1000_DEV_ID_PCH_NVL_I219_V29          0x57BA
 
 #define E1000_REVISION_4       4
 
@@ -150,6 +152,7 @@ enum e1000_mac_type {
        e1000_pch_mtp,
        e1000_pch_lnp,
        e1000_pch_ptp,
+       e1000_pch_nvp,
 };
 
 enum e1000_media_type {
index 0c7fd10..39e9fc6 100644 (file)
@@ -323,6 +323,7 @@ static s32 e1000_init_phy_workarounds_pchlan(struct e1000_hw *hw)
        case e1000_pch_mtp:
        case e1000_pch_lnp:
        case e1000_pch_ptp:
+       case e1000_pch_nvp:
                if (e1000_phy_is_accessible_pchlan(hw))
                        break;
 
@@ -470,6 +471,7 @@ static s32 e1000_init_phy_params_pchlan(struct e1000_hw *hw)
                case e1000_pch_mtp:
                case e1000_pch_lnp:
                case e1000_pch_ptp:
+               case e1000_pch_nvp:
                        /* In case the PHY needs to be in mdio slow mode,
                         * set slow mode and try to get the PHY id again.
                         */
@@ -717,6 +719,7 @@ static s32 e1000_init_mac_params_ich8lan(struct e1000_hw *hw)
        case e1000_pch_mtp:
        case e1000_pch_lnp:
        case e1000_pch_ptp:
+       case e1000_pch_nvp:
        case e1000_pchlan:
                /* check management mode */
                mac->ops.check_mng_mode = e1000_check_mng_mode_pchlan;
@@ -1685,6 +1688,7 @@ static s32 e1000_get_variants_ich8lan(struct e1000_adapter *adapter)
        case e1000_pch_mtp:
        case e1000_pch_lnp:
        case e1000_pch_ptp:
+       case e1000_pch_nvp:
                rc = e1000_init_phy_params_pchlan(hw);
                break;
        default:
@@ -2142,6 +2146,7 @@ static s32 e1000_sw_lcd_config_ich8lan(struct e1000_hw *hw)
        case e1000_pch_mtp:
        case e1000_pch_lnp:
        case e1000_pch_ptp:
+       case e1000_pch_nvp:
                sw_cfg_mask = E1000_FEXTNVM_SW_CONFIG_ICH8M;
                break;
        default:
@@ -3188,6 +3193,7 @@ static s32 e1000_valid_nvm_bank_detect_ich8lan(struct e1000_hw *hw, u32 *bank)
        case e1000_pch_mtp:
        case e1000_pch_lnp:
        case e1000_pch_ptp:
+       case e1000_pch_nvp:
                bank1_offset = nvm->flash_bank_size;
                act_offset = E1000_ICH_NVM_SIG_WORD;
 
@@ -4129,6 +4135,7 @@ static s32 e1000_validate_nvm_checksum_ich8lan(struct e1000_hw *hw)
        case e1000_pch_mtp:
        case e1000_pch_lnp:
        case e1000_pch_ptp:
+       case e1000_pch_nvp:
                word = NVM_COMPAT;
                valid_csum_mask = NVM_COMPAT_VALID_CSUM;
                break;
index 18a5e73..f536c85 100644 (file)
@@ -3545,6 +3545,7 @@ s32 e1000e_get_base_timinca(struct e1000_adapter *adapter, u32 *timinca)
        case e1000_pch_mtp:
        case e1000_pch_lnp:
        case e1000_pch_ptp:
+       case e1000_pch_nvp:
                if (er32(TSYNCRXCTL) & E1000_TSYNCRXCTL_SYSCFI) {
                        /* Stable 24MHz frequency */
                        incperiod = INCPERIOD_24MHZ;
@@ -4061,6 +4062,7 @@ void e1000e_reset(struct e1000_adapter *adapter)
        case e1000_pch_mtp:
        case e1000_pch_lnp:
        case e1000_pch_ptp:
+       case e1000_pch_nvp:
                fc->refresh_time = 0xFFFF;
                fc->pause_time = 0xFFFF;
 
@@ -7913,6 +7915,8 @@ static const struct pci_device_id e1000_pci_tbl[] = {
        { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_PTP_I219_V26), board_pch_mtp },
        { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_PTP_I219_LM27), board_pch_mtp },
        { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_PTP_I219_V27), board_pch_mtp },
+       { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_NVL_I219_LM29), board_pch_mtp },
+       { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_NVL_I219_V29), board_pch_mtp },
 
        { 0, 0, 0, 0, 0, 0, 0 } /* terminate list */
 };
index def4566..02d871b 100644 (file)
@@ -288,6 +288,7 @@ void e1000e_ptp_init(struct e1000_adapter *adapter)
        case e1000_pch_mtp:
        case e1000_pch_lnp:
        case e1000_pch_ptp:
+       case e1000_pch_nvp:
                if ((hw->mac.type < e1000_pch_lpt) ||
                    (er32(TSYNCRXCTL) & E1000_TSYNCRXCTL_SYSCFI)) {
                        adapter->ptp_clock_info.max_adj = 24000000 - 1;