drm/amd/display: send pipe set command to dmcu when backlight is set

[Why]
Previously, a change removed code that would send a pipe set command
to dmcu each time the backlight was set, as it was thought to be
superfluous. However, it is possible for the backlight to be set
before a valid pipe has been set, which causes DMCU to hang after a
DPMS restore on some systems.

[How]
Send a pipe set command to DMCU prior to setting the backlight.

Signed-off-by: Josip Pavic <Josip.Pavic@amd.com>
Reviewed-by: Anthony Koo <Anthony.Koo@amd.com>
Acked-by: Leo Li <sunpeng.li@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_abm.c b/drivers/gpu/drm/amd/display/dc/dce/dce_abm.c
index a740bc3..da96229 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/dce/dce_abm.c
+++ b/drivers/gpu/drm/amd/display/dc/dce/dce_abm.c
@@ -53,6 +53,27 @@
 
 #define MCP_DISABLE_ABM_IMMEDIATELY 255
 
+static bool dce_abm_set_pipe(struct abm *abm, uint32_t controller_id)
+{
+       struct dce_abm *abm_dce = TO_DCE_ABM(abm);
+       uint32_t rampingBoundary = 0xFFFF;
+
+       REG_WAIT(MASTER_COMM_CNTL_REG, MASTER_COMM_INTERRUPT, 0,
+                       1, 80000);
+
+       /* set ramping boundary */
+       REG_WRITE(MASTER_COMM_DATA_REG1, rampingBoundary);
+
+       /* setDMCUParam_Pipe */
+       REG_UPDATE_2(MASTER_COMM_CMD_REG,
+                       MASTER_COMM_CMD_REG_BYTE0, MCP_ABM_PIPE_SET,
+                       MASTER_COMM_CMD_REG_BYTE1, controller_id);
+
+       /* notifyDMCUMsg */
+       REG_UPDATE(MASTER_COMM_CNTL_REG, MASTER_COMM_INTERRUPT, 1);
+
+       return true;
+}
 
 static unsigned int calculate_16_bit_backlight_from_pwm(struct dce_abm *abm_dce)
 {
@@ -184,6 +205,8 @@ static void dmcu_set_backlight_level(
                // Take MSB of fractional part since backlight is not max
                backlight_8_bit = (backlight_pwm_u16_16 >> 8) & 0xFF;
 
+       dce_abm_set_pipe(&abm_dce->base, controller_id);
+
        /* waitDMCUReadyForCmd */
        REG_WAIT(MASTER_COMM_CNTL_REG, MASTER_COMM_INTERRUPT,
                        0, 1, 80000);
@@ -293,28 +316,6 @@ static bool dce_abm_set_level(struct abm *abm, uint32_t level)
        return true;
 }
 
-static bool dce_abm_set_pipe(struct abm *abm, uint32_t controller_id)
-{
-       struct dce_abm *abm_dce = TO_DCE_ABM(abm);
-       uint32_t rampingBoundary = 0xFFFF;
-
-       REG_WAIT(MASTER_COMM_CNTL_REG, MASTER_COMM_INTERRUPT, 0,
-                       1, 80000);
-
-       /* set ramping boundary */
-       REG_WRITE(MASTER_COMM_DATA_REG1, rampingBoundary);
-
-       /* setDMCUParam_Pipe */
-       REG_UPDATE_2(MASTER_COMM_CMD_REG,
-                       MASTER_COMM_CMD_REG_BYTE0, MCP_ABM_PIPE_SET,
-                       MASTER_COMM_CMD_REG_BYTE1, controller_id);
-
-       /* notifyDMCUMsg */
-       REG_UPDATE(MASTER_COMM_CNTL_REG, MASTER_COMM_INTERRUPT, 1);
-
-       return true;
-}
-
 static bool dce_abm_immediate_disable(struct abm *abm)
 {
        struct dce_abm *abm_dce = TO_DCE_ABM(abm);