let ResourceCycles = [4];
}
-// FIXME 8/16 bit divisions
+// Worst case (i64 division)
def : WriteRes<WriteIDiv, [JALU1, JDiv]> {
- let Latency = 25;
- let ResourceCycles = [1, 25];
-}
-def : WriteRes<WriteIDivLd, [JALU1, JLAGU, JDiv]> {
let Latency = 41;
- let ResourceCycles = [1, 1, 25];
+ let ResourceCycles = [1, 41];
+ let NumMicroOps = 2;
+}
+def : WriteRes<WriteIDivLd, [JLAGU, JALU1, JDiv]> {
+ let Latency = 44;
+ let ResourceCycles = [1, 1, 41];
+ let NumMicroOps = 2;
}
// This is for simple LEAs with one or two input operands.
// FIXME: SAGU 3-operand LEA
def : WriteRes<WriteLEA, [JALU01]>;
+def JWriteIDiv8 : SchedWriteRes<[JALU1, JDiv]> {
+ let Latency = 12;
+ let ResourceCycles = [1, 12];
+}
+def JWriteIDiv8Ld : SchedWriteRes<[JLAGU, JALU1, JDiv]> {
+ let Latency = 15;
+ let ResourceCycles = [1, 1, 12];
+}
+def : InstRW<[JWriteIDiv8], (instrs DIV8r, IDIV8r)>;
+def : InstRW<[JWriteIDiv8Ld], (instrs DIV8m, IDIV8m)>;
+
+def JWriteIDiv16 : SchedWriteRes<[JALU1, JDiv]> {
+ let Latency = 17;
+ let ResourceCycles = [1, 17];
+ let NumMicroOps = 2;
+}
+def JWriteIDiv16Ld : SchedWriteRes<[JLAGU, JALU1, JDiv]> {
+ let Latency = 20;
+ let ResourceCycles = [1, 1, 17];
+ let NumMicroOps = 2;
+}
+def : InstRW<[JWriteIDiv16], (instrs DIV16r, IDIV16r)>;
+def : InstRW<[JWriteIDiv16Ld], (instrs DIV16m, IDIV16m)>;
+
+def JWriteIDiv32 : SchedWriteRes<[JALU1, JDiv]> {
+ let Latency = 25;
+ let ResourceCycles = [1, 25];
+ let NumMicroOps = 2;
+}
+def JWriteIDiv32Ld : SchedWriteRes<[JLAGU, JALU1, JDiv]> {
+ let Latency = 28;
+ let ResourceCycles = [1, 1, 25];
+ let NumMicroOps = 2;
+}
+def : InstRW<[JWriteIDiv32], (instrs DIV32r, IDIV32r)>;
+def : InstRW<[JWriteIDiv32Ld], (instrs DIV32m, IDIV32m)>;
+
////////////////////////////////////////////////////////////////////////////////
// Integer shifts and rotates.
////////////////////////////////////////////////////////////////////////////////
; BTVER2-NEXT: movq {{[0-9]+}}(%rsp), %r10 # sched: [5:1.00]
; BTVER2-NEXT: movq {{[0-9]+}}(%rsp), %rax # sched: [5:1.00]
; BTVER2-NEXT: #APP
-; BTVER2-NEXT: divb %dil # sched: [25:25.00]
-; BTVER2-NEXT: divb (%r8) # sched: [41:25.00]
-; BTVER2-NEXT: divw %si # sched: [25:25.00]
-; BTVER2-NEXT: divw (%r9) # sched: [41:25.00]
+; BTVER2-NEXT: divb %dil # sched: [12:12.00]
+; BTVER2-NEXT: divb (%r8) # sched: [15:12.00]
+; BTVER2-NEXT: divw %si # sched: [17:17.00]
+; BTVER2-NEXT: divw (%r9) # sched: [20:17.00]
; BTVER2-NEXT: divl %edx # sched: [25:25.00]
-; BTVER2-NEXT: divl (%rax) # sched: [41:25.00]
-; BTVER2-NEXT: divq %rcx # sched: [25:25.00]
-; BTVER2-NEXT: divq (%r10) # sched: [41:25.00]
+; BTVER2-NEXT: divl (%rax) # sched: [28:25.00]
+; BTVER2-NEXT: divq %rcx # sched: [41:41.00]
+; BTVER2-NEXT: divq (%r10) # sched: [44:41.00]
; BTVER2-NEXT: #NO_APP
; BTVER2-NEXT: retq # sched: [4:1.00]
;
; BTVER2-NEXT: movq {{[0-9]+}}(%rsp), %r10 # sched: [5:1.00]
; BTVER2-NEXT: movq {{[0-9]+}}(%rsp), %rax # sched: [5:1.00]
; BTVER2-NEXT: #APP
-; BTVER2-NEXT: idivb %dil # sched: [25:25.00]
-; BTVER2-NEXT: idivb (%r8) # sched: [41:25.00]
-; BTVER2-NEXT: idivw %si # sched: [25:25.00]
-; BTVER2-NEXT: idivw (%r9) # sched: [41:25.00]
+; BTVER2-NEXT: idivb %dil # sched: [12:12.00]
+; BTVER2-NEXT: idivb (%r8) # sched: [15:12.00]
+; BTVER2-NEXT: idivw %si # sched: [17:17.00]
+; BTVER2-NEXT: idivw (%r9) # sched: [20:17.00]
; BTVER2-NEXT: idivl %edx # sched: [25:25.00]
-; BTVER2-NEXT: idivl (%rax) # sched: [41:25.00]
-; BTVER2-NEXT: idivq %rcx # sched: [25:25.00]
-; BTVER2-NEXT: idivq (%r10) # sched: [41:25.00]
+; BTVER2-NEXT: idivl (%rax) # sched: [28:25.00]
+; BTVER2-NEXT: idivq %rcx # sched: [41:41.00]
+; BTVER2-NEXT: idivq (%r10) # sched: [44:41.00]
; BTVER2-NEXT: #NO_APP
; BTVER2-NEXT: retq # sched: [4:1.00]
;