test code update

diff --git a/de1_nes/de1_nes.vhd b/de1_nes/de1_nes.vhd
index 72d2387..d3673f0 100644 (file)
--- a/de1_nes/de1_nes.vhd
+++ b/de1_nes/de1_nes.vhd
@@ -147,6 +147,8 @@ architecture rtl of de1_nes is
         signal dbg_vga_clk                      : out std_logic;
         signal dbg_nes_x                        : out std_logic_vector (8 downto 0);
         signal dbg_vga_x                        : out std_logic_vector (9 downto 0);
+        signal dbg_nes_y                        : out std_logic_vector (8 downto 0);
+        signal dbg_vga_y                        : out std_logic_vector (9 downto 0);
         signal dbg_disp_nt, dbg_disp_attr       : out std_logic_vector (7 downto 0);
         signal dbg_disp_ptn_h, dbg_disp_ptn_l   : out std_logic_vector (15 downto 0);
         signal dbg_plt_ce_rn_wn                 : out std_logic_vector (2 downto 0);
@@ -288,6 +290,8 @@ architecture rtl of de1_nes is
     signal dbg_ppu_addr_dummy               : std_logic_vector (13 downto 0);
     signal dbg_nes_x                        : std_logic_vector (8 downto 0);
     signal dbg_vga_x                        : std_logic_vector (9 downto 0);
+    signal dbg_nes_y                        : std_logic_vector (8 downto 0);
+    signal dbg_vga_y                        : std_logic_vector (9 downto 0);
     signal dbg_plt_ce_rn_wn                 : std_logic_vector (2 downto 0);
     signal dbg_plt_addr                     : std_logic_vector (4 downto 0);
     signal dbg_plt_data                     : std_logic_vector (7 downto 0);
@@ -308,6 +312,7 @@ architecture rtl of de1_nes is
     signal dbg_int_d_bus_dummy    : std_logic_vector(7 downto 0);
     signal dbg_exec_cycle_dummy   : std_logic_vector (5 downto 0);
     signal dbg_ea_carry_dummy     : std_logic;
+    signal dbg_status_dummy       : std_logic_vector(7 downto 0);
 
 begin
 
@@ -326,7 +331,7 @@ begin
     dbg_ea_carry_dummy,
  --   dbg_index_bus,
  --   dbg_acc_bus,
-    dbg_status,
+    dbg_status_dummy,
     dbg_pcl, dbg_pch, dbg_sp, dbg_x, dbg_y, dbg_acc,
     dbg_dec_oe_n,
     dbg_dec_val,
@@ -359,6 +364,10 @@ begin
     dbg_instruction <= dbg_nes_x(7 downto 0);
     dbg_exec_cycle(3) <= dbg_emu_ppu_clk;
 
+    dbg_exec_cycle(4) <= dbg_nes_y(8);
+    dbg_status <= dbg_nes_y(7 downto 0);
+
+
     dbg_ppu_scrl_x(0) <= ale;
     dbg_ppu_scrl_x(1) <= rd_n;
     dbg_ppu_scrl_x(2) <= wr_n;
@@ -395,6 +404,8 @@ begin
         dbg_vga_clk                      ,
         dbg_nes_x                        ,
         dbg_vga_x                        ,
+        dbg_nes_y                        ,
+        dbg_vga_y                        ,
         dbg_disp_nt, dbg_disp_attr                          ,
         dbg_disp_ptn_h_dummy, dbg_disp_ptn_l_dummy                      ,
         dbg_plt_ce_rn_wn                 ,

diff --git a/de1_nes/dummy-mos6502.vhd b/de1_nes/dummy-mos6502.vhd
index 6659c4d..960c96e 100644 (file)
--- a/de1_nes/dummy-mos6502.vhd
+++ b/de1_nes/dummy-mos6502.vhd
@@ -1,48 +1,48 @@
-library ieee;
-use ieee.std_logic_1164.all;
-
-entity mos6502 is 
-    generic (   dsize : integer := 8;
-                asize : integer :=16
-            );
-    port (  
-    signal dbg_instruction  : out std_logic_vector(7 downto 0);
-    signal dbg_int_d_bus    : out std_logic_vector(7 downto 0);
-    signal dbg_exec_cycle   : out std_logic_vector (5 downto 0);
-    signal dbg_ea_carry     : out std_logic;
-
---    signal dbg_index_bus    : out std_logic_vector(7 downto 0);
---    signal dbg_acc_bus      : out std_logic_vector(7 downto 0);
-    signal dbg_status       : out std_logic_vector(7 downto 0);
-    signal dbg_pcl, dbg_pch, dbg_sp, dbg_x, dbg_y, dbg_acc       : out std_logic_vector(7 downto 0);
-    signal dbg_dec_oe_n    : out std_logic;
-    signal dbg_dec_val     : out std_logic_vector (7 downto 0);
-    signal dbg_int_dbus    : out std_logic_vector (7 downto 0);
---    signal dbg_status_val    : out std_logic_vector (7 downto 0);
-    signal dbg_stat_we_n    : out std_logic;
-    signal dbg_idl_h, dbg_idl_l, dbg_dbb_r, dbg_dbb_w    : out std_logic_vector (7 downto 0);
-
-            input_clk   : in std_logic; --phi0 input pin.
-            rdy         : in std_logic;
-            rst_n       : in std_logic;
-            irq_n       : in std_logic;
-            nmi_n       : in std_logic;
-            dbe         : in std_logic;
-            r_nw        : out std_logic;
-            phi1        : out std_logic;
-            phi2        : out std_logic;
-            addr        : out std_logic_vector ( asize - 1 downto 0);
-            d_io        : inout std_logic_vector ( dsize - 1 downto 0)
-    );
-end mos6502;
-
-architecture rtl of mos6502 is
-
-
-begin
+library ieee;\r
+use ieee.std_logic_1164.all;\r
+\r
+entity mos6502 is \r
+    generic (   dsize : integer := 8;\r
+                asize : integer :=16\r
+            );\r
+    port (  \r
+    signal dbg_instruction  : out std_logic_vector(7 downto 0);\r
+    signal dbg_int_d_bus    : out std_logic_vector(7 downto 0);\r
+    signal dbg_exec_cycle   : out std_logic_vector (5 downto 0);\r
+    signal dbg_ea_carry     : out std_logic;\r
+\r
+--    signal dbg_index_bus    : out std_logic_vector(7 downto 0);\r
+--    signal dbg_acc_bus      : out std_logic_vector(7 downto 0);\r
+    signal dbg_status       : out std_logic_vector(7 downto 0);\r
+    signal dbg_pcl, dbg_pch, dbg_sp, dbg_x, dbg_y, dbg_acc       : out std_logic_vector(7 downto 0);\r
+    signal dbg_dec_oe_n    : out std_logic;\r
+    signal dbg_dec_val     : out std_logic_vector (7 downto 0);\r
+    signal dbg_int_dbus    : out std_logic_vector (7 downto 0);\r
+--    signal dbg_status_val    : out std_logic_vector (7 downto 0);\r
+    signal dbg_stat_we_n    : out std_logic;\r
+    signal dbg_idl_h, dbg_idl_l, dbg_dbb_r, dbg_dbb_w    : out std_logic_vector (7 downto 0);\r
+\r
+            input_clk   : in std_logic; --phi0 input pin.\r
+            rdy         : in std_logic;\r
+            rst_n       : in std_logic;\r
+            irq_n       : in std_logic;\r
+            nmi_n       : in std_logic;\r
+            dbe         : in std_logic;\r
+            r_nw        : out std_logic;\r
+            phi1        : out std_logic;\r
+            phi2        : out std_logic;\r
+            addr        : out std_logic_vector ( asize - 1 downto 0);\r
+            d_io        : inout std_logic_vector ( dsize - 1 downto 0)\r
+    );\r
+end mos6502;\r
+\r
+architecture rtl of mos6502 is\r
+\r
+\r
+begin\r
     phi1 <= input_clk;\r
     phi2 <= not input_clk;\r
-
+\r
     --set ppu value...\r
     set_ppu_p : process (input_clk, rst_n)\r
     use ieee.std_logic_arith.conv_std_logic_vector;\r
@@ -347,7 +347,6 @@ end;
                     elsif (nt_step_cnt = 53 * cpu_io_multi) then\r
                         io_out(16#2007#, 16#1f#);\r
 \r
-\r
                     else\r
                         io_brk;\r
                         if (nt_step_cnt > 56 * cpu_io_multi) then\r
@@ -424,18 +423,24 @@ end;
 \r
                 elsif (global_step_cnt = 4) then\r
                     --final step = enable ppu.\r
-                    if (enable_ppu_step_cnt = 0) then\r
+                    if (enable_ppu_step_cnt = 0 * cpu_io_multi) then\r
+                        --scroll reg set x.\r
+                        io_out(16#2005#, 0);\r
+                    elsif (enable_ppu_step_cnt = 1 * cpu_io_multi) then\r
+                        --scroll reg set y.\r
+                        io_out(16#2005#, 247);\r
+                    elsif (enable_ppu_step_cnt = 2 * cpu_io_multi) then\r
                         --show bg\r
                         --PPUMASK=1e (show bg and sprite)\r
                         --PPUMASK=0e (show bg only)\r
                         io_out(16#2001#, 16#1e#);\r
-                    elsif (enable_ppu_step_cnt = 1 * cpu_io_multi) then\r
+                    elsif (enable_ppu_step_cnt = 3 * cpu_io_multi) then\r
                         --enable nmi\r
                         --PPUCTRL=80\r
                         io_out(16#2000#, 16#80#);\r
                     else\r
                         io_brk;\r
-                        if (enable_ppu_step_cnt > 2 * cpu_io_multi) then\r
+                        if (enable_ppu_step_cnt > 4 * cpu_io_multi) then\r
                             global_step_cnt := global_step_cnt + 1;\r
                         end if;\r
                     end if;\r
@@ -447,10 +452,10 @@ end;
                 end if;\r
             end if;--if (init_done = '0') then\r
         end if; --if (rst_n = '0') then\r
-    end process;
-
-end rtl;
-
+    end process;\r
+\r
+end rtl;\r
+\r
 \r
 \r
 \r

diff --git a/de1_nes/ppu/dmy_cpu.vhd b/de1_nes/ppu/dmy_cpu.vhd
deleted file mode 100644 (file)
index b677fb2..0000000
--- a/de1_nes/ppu/dmy_cpu.vhd
+++ /dev/null
@@ -1,157 +0,0 @@
-library ieee;
-use ieee.std_logic_1164.all;
-use ieee.std_logic_arith.conv_std_logic_vector;\r
-use ieee.std_logic_unsigned.conv_integer;\r
-
-entity mos6502 is 
-    generic (   dsize : integer := 8;
-                asize : integer :=16
-            );
-    port (  
-    signal dbg_instruction  : out std_logic_vector(7 downto 0);
-    signal dbg_int_d_bus    : out std_logic_vector(7 downto 0);
-    signal dbg_exec_cycle   : out std_logic_vector (5 downto 0);
-    signal dbg_ea_carry     : out std_logic;
-    signal dbg_wait_a58_branch_next     : out std_logic;
-
---    signal dbg_index_bus    : out std_logic_vector(7 downto 0);
---    signal dbg_acc_bus      : out std_logic_vector(7 downto 0);
-    signal dbg_status       : out std_logic_vector(7 downto 0);
-    signal dbg_pcl, dbg_pch, dbg_sp, dbg_x, dbg_y, dbg_acc       : out std_logic_vector(7 downto 0);
-    signal dbg_dec_oe_n    : out std_logic;
-    signal dbg_dec_val     : out std_logic_vector (7 downto 0);
-    signal dbg_int_dbus    : out std_logic_vector (7 downto 0);
---    signal dbg_status_val    : out std_logic_vector (7 downto 0);
-    signal dbg_stat_we_n    : out std_logic;
-    signal dbg_idl_h, dbg_idl_l, dbg_dbb_r, dbg_dbb_w    : out std_logic_vector (7 downto 0);
-
-            input_clk   : in std_logic; --phi0 input pin.
-            rdy         : in std_logic;
-            rst_n       : in std_logic;
-            irq_n       : in std_logic;
-            nmi_n       : in std_logic;
-            dbe         : in std_logic;
-            r_nw        : out std_logic;
-            phi1        : out std_logic;
-            phi2        : out std_logic;
-            addr        : out std_logic_vector ( asize - 1 downto 0);
-            d_io        : inout std_logic_vector ( dsize - 1 downto 0)
-    );
-end mos6502;
-
-architecture rtl of mos6502 is
-\r
-signal init_done : std_logic;\r
-signal global_step_cnt : integer;\r
-
-begin
-\r
-    phi1 <= input_clk;\r
-    phi2 <= not input_clk;\r
-\r
-    main_p : process (input_clk, rst_n)\r
-    variable plt_step_cnt, nt_step_cnt : integer;\r
-\r
-procedure vram_set (ad: in integer; dt : in integer) is\r
-begin\r
-    r_nw <= '0';\r
-    addr <= conv_std_logic_vector(ad, 16);\r
-    d_io <= conv_std_logic_vector(dt, 8);\r
-end;\r
-procedure vram_clr is\r
-begin\r
-    addr <= (others => 'Z');\r
-    d_io <= (others => 'Z');\r
-    r_nw <= '1';\r
-end;\r
-\r
-    begin\r
-        if (rst_n = '0') then\r
-            init_done <= '0';\r
-            global_step_cnt <= 0;\r
-            \r
-            r_nw <= 'Z';\r
-            addr <= (others => 'Z');\r
-            d_io <= (others => 'Z');\r
-            \r
-            plt_step_cnt := 0;\r
-            nt_step_cnt := 0;\r
-
-        elsif (rising_edge(input_clk)) then\r
-            if (init_done = '0') then\r
-                if (global_step_cnt = 0) then\r
-                    --step0 = palette set.\r
---palettes:\r
---;;;bg palette\r
---     .byte   $0f, $00, $10, $20\r
---     .byte   $0f, $04, $14, $24\r
---     .byte   $0f, $08, $18, $28\r
---     .byte   $0f, $0c, $1c, $2c\r
---;;;spr palette\r
---     .byte   $0f, $00, $10, $20\r
---     .byte   $0f, $06, $16, $26\r
---     .byte   $0f, $08, $18, $28\r
---     .byte   $0f, $0a, $1a, $2a\r
-                    \r
-                    \r
-                    if (plt_step_cnt = 0) then\r
-                        --set vram addr 3f00\r
-                        vram_set(16#2006#, 16#3f#);\r
-                    elsif (plt_step_cnt = 2) then\r
-                        vram_set(16#2006#, 16#00#);\r
-\r
-                    elsif (plt_step_cnt = 4) then\r
-                        --set palette data\r
-                        vram_set(16#2007#, 16#0f#);\r
-                    elsif (plt_step_cnt = 6) then\r
-                        vram_set(16#2007#, 16#00#);\r
-                    elsif (plt_step_cnt = 8) then\r
-                        vram_set(16#2007#, 16#10#);\r
-                    elsif (plt_step_cnt = 10) then\r
-                        vram_set(16#2007#, 16#20#);\r
-                    \r
-                    else\r
-                        vram_clr;\r
-                        if (plt_step_cnt > 10) then\r
-                            global_step_cnt <= global_step_cnt + 1;\r
-                        end if;\r
-                    end if;\r
-                    plt_step_cnt := plt_step_cnt + 1;\r
-                    \r
-                elsif (global_step_cnt = 1) then\r
-                    --step1 = name table set.\r
-                    \r
-                    if (nt_step_cnt = 0) then\r
-                        --set vram addr 2000\r
-                        vram_set(16#2006#, 16#20#);\r
-                    elsif (nt_step_cnt = 2) then\r
-                        vram_set(16#2006#, 16#00#);\r
-\r
-                    elsif (nt_step_cnt = 4) then\r
-                        --set name tbl data\r
-                        vram_set(16#2007#, 16#41#);\r
-                    elsif (nt_step_cnt = 6) then\r
-                        vram_set(16#2007#, 16#42#);\r
-                    elsif (nt_step_cnt = 8) then\r
-                        vram_set(16#2007#, 16#43#);\r
-\r
-                    else\r
-                        vram_clr;\r
-                        if (nt_step_cnt > 8) then\r
-                            global_step_cnt <= global_step_cnt + 1;\r
-                        end if;\r
-                    end if;\r
-                    nt_step_cnt := nt_step_cnt + 1;\r
-                    \r
-                else\r
-                    init_done <= '1';\r
-                end if;\r
-            end if;\r
-        \r
-        end if;\r
-    end process;\r
-
-
-
-end rtl;
-

diff --git a/de1_nes/ppu/ppu.vhd b/de1_nes/ppu/ppu.vhd
index a4f1957..bf02b9d 100644 (file)
--- a/de1_nes/ppu/ppu.vhd
+++ b/de1_nes/ppu/ppu.vhd
@@ -13,6 +13,8 @@ entity ppu is
     signal dbg_vga_clk                      : out std_logic;
     signal dbg_nes_x                        : out std_logic_vector (8 downto 0);
     signal dbg_vga_x                        : out std_logic_vector (9 downto 0);
+    signal dbg_nes_y                        : out std_logic_vector (8 downto 0);
+    signal dbg_vga_y                        : out std_logic_vector (9 downto 0);
     signal dbg_disp_nt, dbg_disp_attr       : out std_logic_vector (7 downto 0);
     signal dbg_disp_ptn_h, dbg_disp_ptn_l   : out std_logic_vector (15 downto 0);
     signal dbg_plt_ce_rn_wn                 : out std_logic_vector (2 downto 0);
@@ -62,6 +64,8 @@ component vga_ppu_render
     signal dbg_vga_clk                      : out std_logic;
     signal dbg_nes_x                        : out std_logic_vector (8 downto 0);
     signal dbg_vga_x                        : out std_logic_vector (9 downto 0);
+    signal dbg_nes_y                        : out std_logic_vector (8 downto 0);
+    signal dbg_vga_y                        : out std_logic_vector (9 downto 0);
     signal dbg_disp_nt, dbg_disp_attr       : out std_logic_vector (7 downto 0);
     signal dbg_disp_ptn_h, dbg_disp_ptn_l   : out std_logic_vector (15 downto 0);
     signal dbg_plt_ce_rn_wn                 : out std_logic_vector (2 downto 0);
@@ -225,6 +229,8 @@ begin
     dbg_vga_clk                      ,
     dbg_nes_x                        ,
     dbg_vga_x                        ,
+    dbg_nes_y                        ,
+    dbg_vga_y                        ,
     dbg_disp_nt, dbg_disp_attr, dbg_disp_ptn_h, dbg_disp_ptn_l,
     dbg_plt_ce_rn_wn                 ,
     dbg_plt_addr                     ,

diff --git a/de1_nes/ppu/vga_ppu.vhd b/de1_nes/ppu/vga_ppu.vhd
index a205894..f239449 100644 (file)
--- a/de1_nes/ppu/vga_ppu.vhd
+++ b/de1_nes/ppu/vga_ppu.vhd
@@ -16,6 +16,8 @@ entity vga_ppu_render is
     signal dbg_vga_clk                      : out std_logic;\r
     signal dbg_nes_x                        : out std_logic_vector (8 downto 0);\r
     signal dbg_vga_x                        : out std_logic_vector (9 downto 0);\r
+    signal dbg_nes_y                        : out std_logic_vector (8 downto 0);\r
+    signal dbg_vga_y                        : out std_logic_vector (9 downto 0);\r
     signal dbg_disp_nt, dbg_disp_attr       : out std_logic_vector (7 downto 0);\r
     signal dbg_disp_ptn_h, dbg_disp_ptn_l   : out std_logic_vector (15 downto 0);\r
     signal dbg_plt_ce_rn_wn                 : out std_logic_vector (2 downto 0);\r
@@ -85,6 +87,7 @@ component ppu_render
     port (  \r
     signal dbg_ppu_clk                      : out std_logic;\r
     signal dbg_nes_x                        : out std_logic_vector (8 downto 0);\r
+    signal dbg_nes_y                        : out std_logic_vector (8 downto 0);\r
     signal dbg_disp_nt, dbg_disp_attr       : out std_logic_vector (7 downto 0);\r
     signal dbg_disp_ptn_h, dbg_disp_ptn_l   : out std_logic_vector (15 downto 0);\r
     signal dbg_plt_ce_rn_wn                 : out std_logic_vector (2 downto 0);\r
@@ -162,6 +165,7 @@ signal nes_y        : std_logic_vector (8 downto 0);
 \r
 begin\r
     dbg_vga_x <= vga_x;\r
+    dbg_vga_y <= vga_y;\r
     dbg_vga_clk <= vga_clk;\r
     \r
     cnt_clk <= not vga_clk;\r
@@ -258,6 +262,7 @@ begin
         port map (\r
         dbg_emu_ppu_clk                      ,\r
         dbg_nes_x                        ,\r
+        dbg_nes_y                        ,\r
         dbg_disp_nt, dbg_disp_attr       ,\r
         dbg_disp_ptn_h, dbg_disp_ptn_l   ,\r
         dbg_plt_ce_rn_wn                 ,\r
@@ -317,6 +322,7 @@ entity ppu_render is
     port (  \r
     signal dbg_ppu_clk                      : out std_logic;\r
     signal dbg_nes_x                        : out std_logic_vector (8 downto 0);\r
+    signal dbg_nes_y                        : out std_logic_vector (8 downto 0);\r
     signal dbg_disp_nt, dbg_disp_attr       : out std_logic_vector (7 downto 0);\r
     signal dbg_disp_ptn_h, dbg_disp_ptn_l   : out std_logic_vector (15 downto 0);\r
     signal dbg_plt_ce_rn_wn                 : out std_logic_vector (2 downto 0);\r
@@ -661,6 +667,7 @@ signal spr_ptn_in       : std_logic_vector (dsize - 1 downto 0);
 begin\r
     dbg_ppu_clk <= ppu_clk;\r
     dbg_nes_x <= cur_x;\r
+    dbg_nes_y <= cur_y;\r
     dbg_disp_nt <= disp_nt;\r
     dbg_disp_attr <= disp_attr;\r
     dbg_disp_ptn_h <= disp_ptn_h;\r

diff --git a/de1_nes/simulation/modelsim/de1_nes_run_msim_gate_vhdl.do b/de1_nes/simulation/modelsim/de1_nes_run_msim_gate_vhdl.do
index 2171773..93c4453 100644 (file)
--- a/de1_nes/simulation/modelsim/de1_nes_run_msim_gate_vhdl.do
+++ b/de1_nes/simulation/modelsim/de1_nes_run_msim_gate_vhdl.do
@@ -63,11 +63,13 @@ add wave -label ppu_data -radix hex sim:/testbench_motones_sim/sim_board/dbg_ppu
 \r
 \r
 add wave -divider vga_pos\r
-add wave -label dbg_emu_ppu_clk           sim:/testbench_motones_sim/sim_board/dbg_exec_cycle(3)\r
-add wave -label nes_x           -radix decimal -unsigned  {sim:/testbench_motones_sim/sim_board/dbg_exec_cycle(0) & sim:/testbench_motones_sim/sim_board/dbg_instruction (7 downto 0)}\r
+add wave -label emu_ppu_clk           sim:/testbench_motones_sim/sim_board/dbg_exec_cycle(3)\r
 add wave -label vga_x           -radix decimal -unsigned  {sim:/testbench_motones_sim/sim_board/dbg_exec_cycle(2 downto 1) & sim:/testbench_motones_sim/sim_board/dbg_int_d_bus (7 downto 0)}\r
-#add wave -label dbg_disp_nt     -radix hex sim:/testbench_motones_sim/sim_board/dbg_disp_nt\r
-#add wave -label dbg_disp_attr   -radix hex sim:/testbench_motones_sim/sim_board/dbg_disp_attr\r
+add wave -label nes_x           -radix decimal -unsigned  {sim:/testbench_motones_sim/sim_board/dbg_exec_cycle(0) & sim:/testbench_motones_sim/sim_board/dbg_instruction (7 downto 0)}\r
+add wave -label nes_y           -radix decimal -unsigned  {sim:/testbench_motones_sim/sim_board/dbg_exec_cycle(4) & sim:/testbench_motones_sim/sim_board/dbg_status (7 downto 0)}\r
+\r
+add wave -label dbg_disp_nt     -radix hex sim:/testbench_motones_sim/sim_board/dbg_disp_nt\r
+add wave -label dbg_disp_attr   -radix hex sim:/testbench_motones_sim/sim_board/dbg_disp_attr\r
 #add wave -label dbg_disp_ptn_h  -radix hex sim:/testbench_motones_sim/sim_board/dbg_disp_ptn_h\r
 #add wave -label dbg_disp_ptn_l  -radix hex sim:/testbench_motones_sim/sim_board/dbg_disp_ptn_l\r
 \r