cmp bug fix.

diff --git a/simulation/cpu/alu.vhd b/simulation/cpu/alu.vhd
index e0d4f22..69b3117 100644 (file)
--- a/simulation/cpu/alu.vhd
+++ b/simulation/cpu/alu.vhd
@@ -4,6 +4,7 @@
 library ieee;
 use ieee.std_logic_1164.all;
 use ieee.std_logic_unsigned.all;
+--use ieee.std_logic_arith.all;
 
 entity alu is 
     generic (   dsize : integer := 8
@@ -12,8 +13,8 @@ entity alu is
             alu_en_n        : in std_logic;
             instruction     : in std_logic_vector (dsize - 1 downto 0);
             int_d_bus       : inout std_logic_vector (dsize - 1 downto 0);
-            acc_in          : in std_logic_vector (dsize - 1 downto 0);
-            acc_out         : out std_logic_vector (dsize - 1 downto 0);
+            alu_in          : in std_logic_vector (dsize - 1 downto 0);
+            alu_out         : out std_logic_vector (dsize - 1 downto 0);
             carry_in        : in std_logic;
             negative        : out std_logic;
             zero            : out std_logic;
@@ -35,7 +36,7 @@ end  procedure;
 
 begin
 
-    alu_p : process (alu_en_n)
+    alu_p : process (alu_en_n, instruction, alu_in, int_d_bus, carry_in)
     variable res : std_logic_vector (dsize - 1 downto 0);
 
 procedure set_n (data : in std_logic_vector (dsize - 1 downto 0)) is
@@ -71,8 +72,9 @@ end procedure;
                     d_print("adc");
                 elsif instruction (7 downto 5) = "110" then
                     d_print("cmp");
+                    --cmpare A - M.
                     --set n/v/z flag
-                    res := acc_in - int_d_bus;
+                    res := alu_in - int_d_bus;
                     set_n(res);
                     set_z(res);
                     --ovf flag set when acc < mem .
@@ -84,7 +86,7 @@ end procedure;
 
                     --no register update.
                     int_d_bus <= (others => 'Z');
-                    acc_out <= (others => 'Z');
+                    alu_out <= (others => 'Z');
                     carry_out <= 'Z';
 
                 elsif instruction (7 downto 5) = "111" then
@@ -127,7 +129,7 @@ end procedure;
             end if; --if instruction (1 downto 0) = "01"
     else
         int_d_bus <= (others => 'Z');
-        acc_out <= (others => 'Z');
+        alu_out <= (others => 'Z');
         negative <= 'Z';
         zero <= 'Z';
         carry_out <= 'Z';

diff --git a/simulation/cpu/cpu_registers.vhd b/simulation/cpu/cpu_registers.vhd
index 31fde66..ac7683f 100644 (file)
--- a/simulation/cpu/cpu_registers.vhd
+++ b/simulation/cpu/cpu_registers.vhd
@@ -600,8 +600,8 @@ entity accumulator is
             alu_we_n    : in std_logic;
             d_oe_n      : in std_logic;
             int_dbus    : inout std_logic_vector (dsize - 1 downto 0);
-            alu_in      : in std_logic_vector (dsize - 1 downto 0);
-            alu_out     : out std_logic_vector (dsize - 1 downto 0)
+            alu_out     : in std_logic_vector (dsize - 1 downto 0);
+            alu_in      : out std_logic_vector (dsize - 1 downto 0)
         );
 end accumulator;
 
@@ -626,11 +626,11 @@ signal q : std_logic_vector (dsize - 1 downto 0);
 begin
     we_n <= (d_we_n and alu_we_n);
     d <= int_dbus when d_we_n = '0' else
-        alu_in when alu_we_n = '0' else
+        alu_out when alu_we_n = '0' else
         (others => 'Z');
     int_dbus <= q when d_oe_n = '0' else
         (others => 'Z');
-    alu_out <= q;
+    alu_in <= q;
 
     --read from i/o to cpu
     dff_inst : dff generic map (dsize) 

diff --git a/simulation/cpu/mos6502.vhd b/simulation/cpu/mos6502.vhd
index a1e5855..6a21dd5 100644 (file)
--- a/simulation/cpu/mos6502.vhd
+++ b/simulation/cpu/mos6502.vhd
@@ -120,8 +120,8 @@ architecture rtl of mos6502 is
                 alu_en_n        : in std_logic;
                 instruction     : in std_logic_vector (dsize - 1 downto 0);
                 int_d_bus       : inout std_logic_vector (dsize - 1 downto 0);
-                acc_in          : in std_logic_vector (dsize - 1 downto 0);
-                acc_out         : out std_logic_vector (dsize - 1 downto 0);
+                alu_in          : in std_logic_vector (dsize - 1 downto 0);
+                alu_out         : out std_logic_vector (dsize - 1 downto 0);
                 carry_in        : in std_logic;
                 negative        : out std_logic;
                 zero            : out std_logic;
@@ -236,8 +236,8 @@ architecture rtl of mos6502 is
             alu_we_n    : in std_logic;
             d_oe_n      : in std_logic;
             int_dbus    : inout std_logic_vector (dsize - 1 downto 0);
-            alu_in      : in std_logic_vector (dsize - 1 downto 0);
-            alu_out     : out std_logic_vector (dsize - 1 downto 0)
+            alu_out     : in std_logic_vector (dsize - 1 downto 0);
+            alu_in      : out std_logic_vector (dsize - 1 downto 0)
         );
     end component;
 
@@ -504,7 +504,7 @@ begin
     acc_reg : accumulator generic map (dsize) 
             port map(trigger_clk, 
                     acc_d_we_n, acc_alu_we_n, acc_d_oe_n, 
-                    internal_dbus, alu_in, alu_out);
+                    internal_dbus, alu_out, alu_in);
 
     -- clock generate.
     phi1 <= input_clk;