+2000-02-08 Nick Clifton <nickc@cygnus.com>
+
+ * wrapper.c: Fix compile time warning messages.
+ * armcopro.c: Fix compile time warning messages.
+ * armdefs.h: Fix compile time warning messages.
+ * armemu.c: Fix compile time warning messages.
+ * armemu.h: Fix compile time warning messages.
+ * armos.c: Fix compile time warning messages.
+ * armsupp.c: Fix compile time warning messages.
+ * armvirt.c: Fix compile time warning messages.
+
+2000-02-02 Bernd Schmidt <bernds@cygnus.co.uk>
+
+ * *.[ch]: Use indent to make readable.
+
+1999-11-22 Nick Clifton <nickc@cygnus.com>
+
+ * armos.c (SWIread): Generate an error message if a huge read is
+ performed.
+ (SWIwrite): Generate an error message if a huge write is
+ performed.
+
+1999-10-27 Nick Clifton <nickc@cygnus.com>
+
+ * thumbemu.c (ARMul_ThumbDecode): Accept 0xbebe as a thumb
+ breakpoint.
+
+1999-10-08 Ulrich Drepper <drepper@cygnus.com>
+
+ * armos.c (SWIopen): Always pass third parameter with 0666 since
+ otherwise uninitialized memory gets access if the O_CREAT bit is
+ set and so we possibly cannot access the file afterwards.
+
+1999-09-29 Doug Evans <devans@casey.cygnus.com>
+
+ * armos.c (SWIWrite0): Send output to stdout instead of stderr.
+ (ARMul_OSHandleSWI, case SWI_WriteC,AngelSWI_Reason_WriteC): Ditto.
+
+Thu Sep 2 18:15:53 1999 Andrew Cagney <cagney@b1.cygnus.com>
+
+ * configure: Regenerated to track ../common/aclocal.m4 changes.
+
+
+1999-05-08 Felix Lee <flee@cygnus.com>
+
+ * configure: Regenerated to track ../common/aclocal.m4 changes.
+
+1999-04-06 Keith Seitz <keiths@cygnus.com>
+
+ * wrapper.c (stop_simulator): New global.
+ (sim_stop): Set sim state to STOP and set
+ stop_simulator.
+ (sim_resume): Reset stop_simulator.
+ (sim_stop_reason): If stop_simulator is set, tell gdb
+ that the we took SIGINT.
+ * armemu.c (ARMul_Emulate26): Don't loop forever. Stop if
+ stop_simulator is set.
+
+1999-04-02 Keith Seitz <keiths@cygnus.com>
+
+ * armemu.c (ARMul_Emulate26): If NEED_UI_LOOP_HOOK, call ui_loop_hook
+ whenever the counter expires.
+ * Makefile.in (SIM_EXTRA_CFLAGS): Include define NEED_UI_LOOP_HOOK.
+
+1999-03-24 Nick Clifton <nickc@cygnus.com>
+
+ * armemu.c (ARMul_Emulate26): Handle new breakpoint value.
+ * thumbemu.c (ARMul_ThumbDecode): Handle new breakpoint value.
+
Mon Sep 14 09:00:05 1998 Nick Clifton <nickc@cygnus.com>
* wrapper.c (sim_open): Set endianness according to BFD or command
/* armcopro.c -- co-processor interface: ARM6 Instruction Emulator.
- Copyright (C) 1994 Advanced RISC Machines Ltd.
+ Copyright (C) 1994, 2000 Advanced RISC Machines Ltd.
This program is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */
#include "armdefs.h"
+#include "ansidecl.h"
-extern unsigned ARMul_CoProInit(ARMul_State *state) ;
-extern void ARMul_CoProExit(ARMul_State *state) ;
-extern void ARMul_CoProAttach(ARMul_State *state, unsigned number,
- ARMul_CPInits *init, ARMul_CPExits *exit,
- ARMul_LDCs *ldc, ARMul_STCs *stc,
- ARMul_MRCs *mrc, ARMul_MCRs *mcr,
- ARMul_CDPs *cdp,
- ARMul_CPReads *read, ARMul_CPWrites *write) ;
-extern void ARMul_CoProDetach(ARMul_State *state, unsigned number) ;
+extern unsigned ARMul_CoProInit (ARMul_State * state);
+extern void ARMul_CoProExit (ARMul_State * state);
+extern void ARMul_CoProAttach (ARMul_State * state, unsigned number,
+ ARMul_CPInits * init, ARMul_CPExits * exit,
+ ARMul_LDCs * ldc, ARMul_STCs * stc,
+ ARMul_MRCs * mrc, ARMul_MCRs * mcr,
+ ARMul_CDPs * cdp,
+ ARMul_CPReads * read, ARMul_CPWrites * write);
+extern void ARMul_CoProDetach (ARMul_State * state, unsigned number);
/***************************************************************************\
* Dummy Co-processors *
\***************************************************************************/
-static unsigned NoCoPro3R(ARMul_State *state,unsigned,ARMword) ;
-static unsigned NoCoPro4R(ARMul_State *state,unsigned,ARMword,ARMword) ;
-static unsigned NoCoPro4W(ARMul_State *state,unsigned,ARMword,ARMword *) ;
+static unsigned NoCoPro3R (ARMul_State * state, unsigned, ARMword);
+static unsigned NoCoPro4R (ARMul_State * state, unsigned, ARMword, ARMword);
+static unsigned NoCoPro4W (ARMul_State * state, unsigned, ARMword, ARMword *);
/***************************************************************************\
* Define Co-Processor instruction handlers here *
bit 6 controls late abort timimg and bit 7 controls big/little endian.
*/
-static ARMword MMUReg[8] ;
+static ARMword MMUReg[8];
-static unsigned MMUInit(ARMul_State *state)
-{MMUReg[1] = state->prog32Sig << 4 |
- state->data32Sig << 5 |
- state->lateabtSig << 6 |
- state->bigendSig << 7 ;
- ARMul_ConsolePrint (state, ", MMU present") ;
- return(TRUE) ;
+static unsigned
+MMUInit (ARMul_State * state)
+{
+ MMUReg[1] = state->prog32Sig << 4 |
+ state->data32Sig << 5 | state->lateabtSig << 6 | state->bigendSig << 7;
+ ARMul_ConsolePrint (state, ", MMU present");
+ return (TRUE);
+}
+
+static unsigned
+MMUMRC (ARMul_State * state ATTRIBUTE_UNUSED, unsigned type ATTRIBUTE_UNUSED, ARMword instr, ARMword * value)
+{
+ int reg = BITS (16, 19) & 7;
+
+ if (reg == 0)
+ *value = 0x41440110;
+ else
+ *value = MMUReg[reg];
+ return (ARMul_DONE);
}
-static unsigned MMUMRC(ARMul_State *state, unsigned type, ARMword instr,ARMword *value)
-{int reg = BITS(16,19) & 7 ;
-
- if (reg == 0)
- *value = 0x41440110 ;
- else
- *value = MMUReg[reg] ;
- return(ARMul_DONE) ;
- }
-
-static unsigned MMUMCR(ARMul_State *state, unsigned type, ARMword instr, ARMword value)
-{int reg = BITS(16,19) & 7 ;
-
- MMUReg[reg] = value ;
- if (reg == 1) {
- state->prog32Sig = value >> 4 & 1 ;
- state->data32Sig = value >> 5 & 1 ;
- state->lateabtSig = value >> 6 & 1 ;
- state->bigendSig = value >> 7 & 1 ;
- state->Emulate = TRUE ; /* force ARMulator to notice these now !*/
+static unsigned
+MMUMCR (ARMul_State * state, unsigned type ATTRIBUTE_UNUSED, ARMword instr, ARMword value)
+{
+ int reg = BITS (16, 19) & 7;
+
+ MMUReg[reg] = value;
+ if (reg == 1)
+ {
+ state->prog32Sig = value >> 4 & 1;
+ state->data32Sig = value >> 5 & 1;
+ state->lateabtSig = value >> 6 & 1;
+ state->bigendSig = value >> 7 & 1;
+ state->Emulate = TRUE; /* force ARMulator to notice these now ! */
}
- return(ARMul_DONE) ;
- }
-
-
-static unsigned MMURead(ARMul_State *state, unsigned reg, ARMword *value)
-{if (reg == 0)
- *value = 0x41440110 ;
- else if (reg < 8)
- *value = MMUReg[reg] ;
- return(TRUE) ;
- }
-
-static unsigned MMUWrite(ARMul_State *state, unsigned reg, ARMword value)
-{if (reg < 8)
- MMUReg[reg] = value ;
- if (reg == 1) {
- state->prog32Sig = value >> 4 & 1 ;
- state->data32Sig = value >> 5 & 1 ;
- state->lateabtSig = value >> 6 & 1 ;
- state->bigendSig = value >> 7 & 1 ;
- state->Emulate = TRUE ; /* force ARMulator to notice these now !*/
+ return (ARMul_DONE);
+}
+
+
+static unsigned
+MMURead (ARMul_State * state ATTRIBUTE_UNUSED, unsigned reg, ARMword * value)
+{
+ if (reg == 0)
+ *value = 0x41440110;
+ else if (reg < 8)
+ *value = MMUReg[reg];
+ return (TRUE);
+}
+
+static unsigned
+MMUWrite (ARMul_State * state, unsigned reg, ARMword value)
+{
+ if (reg < 8)
+ MMUReg[reg] = value;
+ if (reg == 1)
+ {
+ state->prog32Sig = value >> 4 & 1;
+ state->data32Sig = value >> 5 & 1;
+ state->lateabtSig = value >> 6 & 1;
+ state->bigendSig = value >> 7 & 1;
+ state->Emulate = TRUE; /* force ARMulator to notice these now ! */
}
- return(TRUE) ;
- }
+ return (TRUE);
+}
/* What follows is the Validation Suite Coprocessor. It uses two
bit time value in a CP register (actually it's the total number of N, S,
I, C and F cyles) */
-static ARMword ValReg[16] ;
+static ARMword ValReg[16];
-static unsigned ValLDC(ARMul_State *state, unsigned type,
- ARMword instr, ARMword data)
-{static unsigned words ;
+static unsigned
+ValLDC (ARMul_State * state ATTRIBUTE_UNUSED, unsigned type, ARMword instr, ARMword data)
+{
+ static unsigned words;
- if (type != ARMul_DATA) {
- words = 0 ;
- return(ARMul_DONE) ;
+ if (type != ARMul_DATA)
+ {
+ words = 0;
+ return (ARMul_DONE);
}
- if (BIT(22)) { /* it's a long access, get two words */
- ValReg[BITS(12,15)] = data ;
- if (words++ == 4)
- return(ARMul_DONE) ;
- else
- return(ARMul_INC) ;
+ if (BIT (22))
+ { /* it's a long access, get two words */
+ ValReg[BITS (12, 15)] = data;
+ if (words++ == 4)
+ return (ARMul_DONE);
+ else
+ return (ARMul_INC);
}
- else { /* get just one word */
- ValReg[BITS(12,15)] = data ;
- return(ARMul_DONE) ;
+ else
+ { /* get just one word */
+ ValReg[BITS (12, 15)] = data;
+ return (ARMul_DONE);
}
- }
+}
-static unsigned ValSTC(ARMul_State *state, unsigned type,
- ARMword instr, ARMword *data)
-{static unsigned words ;
+static unsigned
+ValSTC (ARMul_State * state ATTRIBUTE_UNUSED, unsigned type, ARMword instr, ARMword * data)
+{
+ static unsigned words;
- if (type != ARMul_DATA) {
- words = 0 ;
- return(ARMul_DONE) ;
+ if (type != ARMul_DATA)
+ {
+ words = 0;
+ return (ARMul_DONE);
}
- if (BIT(22)) { /* it's a long access, get two words */
- *data = ValReg[BITS(12,15)] ;
- if (words++ == 4)
- return(ARMul_DONE) ;
- else
- return(ARMul_INC) ;
- }
- else { /* get just one word */
- *data = ValReg[BITS(12,15)] ;
- return(ARMul_DONE) ;
+ if (BIT (22))
+ { /* it's a long access, get two words */
+ *data = ValReg[BITS (12, 15)];
+ if (words++ == 4)
+ return (ARMul_DONE);
+ else
+ return (ARMul_INC);
}
- }
+ else
+ { /* get just one word */
+ *data = ValReg[BITS (12, 15)];
+ return (ARMul_DONE);
+ }
+}
-static unsigned ValMRC(ARMul_State *state, unsigned type, ARMword instr,ARMword *value)
+static unsigned
+ValMRC (ARMul_State * state ATTRIBUTE_UNUSED, unsigned type ATTRIBUTE_UNUSED, ARMword instr, ARMword * value)
{
- *value = ValReg[BITS(16,19)] ;
- return(ARMul_DONE) ;
- }
+ *value = ValReg[BITS (16, 19)];
+ return (ARMul_DONE);
+}
-static unsigned ValMCR(ARMul_State *state, unsigned type, ARMword instr, ARMword value)
+static unsigned
+ValMCR (ARMul_State * state ATTRIBUTE_UNUSED, unsigned type ATTRIBUTE_UNUSED, ARMword instr, ARMword value)
{
- ValReg[BITS(16,19)] = value ;
- return(ARMul_DONE) ;
- }
+ ValReg[BITS (16, 19)] = value;
+ return (ARMul_DONE);
+}
-static unsigned ValCDP(ARMul_State *state, unsigned type, ARMword instr)
+static unsigned
+ValCDP (ARMul_State * state, unsigned type, ARMword instr)
{
- static unsigned long finish = 0 ;
- ARMword howlong ;
-
- howlong = ValReg[BITS(0,3)] ;
- if (BITS(20,23)==0) {
- if (type == ARMul_FIRST) { /* First cycle of a busy wait */
- finish = ARMul_Time(state) + howlong ;
- if (howlong == 0)
- return(ARMul_DONE) ;
- else
- return(ARMul_BUSY) ;
- }
- else if (type == ARMul_BUSY) {
- if (ARMul_Time(state) >= finish)
- return(ARMul_DONE) ;
- else
- return(ARMul_BUSY) ;
- }
+ static unsigned long finish = 0;
+ ARMword howlong;
+
+ howlong = ValReg[BITS (0, 3)];
+ if (BITS (20, 23) == 0)
+ {
+ if (type == ARMul_FIRST)
+ { /* First cycle of a busy wait */
+ finish = ARMul_Time (state) + howlong;
+ if (howlong == 0)
+ return (ARMul_DONE);
+ else
+ return (ARMul_BUSY);
+ }
+ else if (type == ARMul_BUSY)
+ {
+ if (ARMul_Time (state) >= finish)
+ return (ARMul_DONE);
+ else
+ return (ARMul_BUSY);
+ }
}
- return(ARMul_CANT) ;
- }
+ return (ARMul_CANT);
+}
-static unsigned DoAFIQ(ARMul_State *state)
-{state->NfiqSig = LOW ;
- state->Exception++ ;
- return(0) ;
+static unsigned
+DoAFIQ (ARMul_State * state)
+{
+ state->NfiqSig = LOW;
+ state->Exception++;
+ return (0);
}
-static unsigned DoAIRQ(ARMul_State *state)
-{state->NirqSig = LOW ;
- state->Exception++ ;
- return(0) ;
+static unsigned
+DoAIRQ (ARMul_State * state)
+{
+ state->NirqSig = LOW;
+ state->Exception++;
+ return (0);
}
-static unsigned IntCDP(ARMul_State *state, unsigned type, ARMword instr)
-{static unsigned long finish ;
- ARMword howlong ;
-
- howlong = ValReg[BITS(0,3)] ;
- switch((int)BITS(20,23)) {
- case 0 : if (type == ARMul_FIRST) { /* First cycle of a busy wait */
- finish = ARMul_Time(state) + howlong ;
- if (howlong == 0)
- return(ARMul_DONE) ;
- else
- return(ARMul_BUSY) ;
- }
- else if (type == ARMul_BUSY) {
- if (ARMul_Time(state) >= finish)
- return(ARMul_DONE) ;
- else
- return(ARMul_BUSY) ;
- }
- return(ARMul_DONE) ;
- case 1 : if (howlong == 0)
- ARMul_Abort(state,ARMul_FIQV) ;
- else
- ARMul_ScheduleEvent(state,howlong,DoAFIQ) ;
- return(ARMul_DONE) ;
- case 2 : if (howlong == 0)
- ARMul_Abort(state,ARMul_IRQV) ;
- else
- ARMul_ScheduleEvent(state,howlong,DoAIRQ) ;
- return(ARMul_DONE) ;
- case 3 : state->NfiqSig = HIGH ;
- state->Exception-- ;
- return(ARMul_DONE) ;
- case 4 : state->NirqSig = HIGH ;
- state->Exception-- ;
- return(ARMul_DONE) ;
- case 5 : ValReg[BITS(0,3)] = ARMul_Time(state) ;
- return(ARMul_DONE) ;
+static unsigned
+IntCDP (ARMul_State * state, unsigned type, ARMword instr)
+{
+ static unsigned long finish;
+ ARMword howlong;
+
+ howlong = ValReg[BITS (0, 3)];
+ switch ((int) BITS (20, 23))
+ {
+ case 0:
+ if (type == ARMul_FIRST)
+ { /* First cycle of a busy wait */
+ finish = ARMul_Time (state) + howlong;
+ if (howlong == 0)
+ return (ARMul_DONE);
+ else
+ return (ARMul_BUSY);
+ }
+ else if (type == ARMul_BUSY)
+ {
+ if (ARMul_Time (state) >= finish)
+ return (ARMul_DONE);
+ else
+ return (ARMul_BUSY);
+ }
+ return (ARMul_DONE);
+ case 1:
+ if (howlong == 0)
+ ARMul_Abort (state, ARMul_FIQV);
+ else
+ ARMul_ScheduleEvent (state, howlong, DoAFIQ);
+ return (ARMul_DONE);
+ case 2:
+ if (howlong == 0)
+ ARMul_Abort (state, ARMul_IRQV);
+ else
+ ARMul_ScheduleEvent (state, howlong, DoAIRQ);
+ return (ARMul_DONE);
+ case 3:
+ state->NfiqSig = HIGH;
+ state->Exception--;
+ return (ARMul_DONE);
+ case 4:
+ state->NirqSig = HIGH;
+ state->Exception--;
+ return (ARMul_DONE);
+ case 5:
+ ValReg[BITS (0, 3)] = ARMul_Time (state);
+ return (ARMul_DONE);
}
- return(ARMul_CANT) ;
- }
+ return (ARMul_CANT);
+}
/***************************************************************************\
* Install co-processor instruction handlers in this routine *
\***************************************************************************/
-unsigned ARMul_CoProInit(ARMul_State *state)
-{register unsigned i ;
+unsigned
+ARMul_CoProInit (ARMul_State * state)
+{
+ register unsigned i;
- for (i = 0 ; i < 16 ; i++) /* initialise tham all first */
- ARMul_CoProDetach(state, i) ;
+ for (i = 0; i < 16; i++) /* initialise tham all first */
+ ARMul_CoProDetach (state, i);
- /* Install CoPro Instruction handlers here
- The format is
- ARMul_CoProAttach(state, CP Number, Init routine, Exit routine
- LDC routine, STC routine, MRC routine, MCR routine,
- CDP routine, Read Reg routine, Write Reg routine) ;
+ /* Install CoPro Instruction handlers here
+ The format is
+ ARMul_CoProAttach(state, CP Number, Init routine, Exit routine
+ LDC routine, STC routine, MRC routine, MCR routine,
+ CDP routine, Read Reg routine, Write Reg routine) ;
*/
- ARMul_CoProAttach(state, 4, NULL, NULL,
- ValLDC, ValSTC, ValMRC, ValMCR,
- ValCDP, NULL, NULL) ;
+ ARMul_CoProAttach (state, 4, NULL, NULL,
+ ValLDC, ValSTC, ValMRC, ValMCR, ValCDP, NULL, NULL);
- ARMul_CoProAttach(state, 5, NULL, NULL,
- NULL, NULL, ValMRC, ValMCR,
- IntCDP, NULL, NULL) ;
+ ARMul_CoProAttach (state, 5, NULL, NULL,
+ NULL, NULL, ValMRC, ValMCR, IntCDP, NULL, NULL);
- ARMul_CoProAttach(state, 15, MMUInit, NULL,
- NULL, NULL, MMUMRC, MMUMCR,
- NULL, MMURead, MMUWrite) ;
+ ARMul_CoProAttach (state, 15, MMUInit, NULL,
+ NULL, NULL, MMUMRC, MMUMCR, NULL, MMURead, MMUWrite);
- /* No handlers below here */
+ /* No handlers below here */
- for (i = 0 ; i < 16 ; i++) /* Call all the initialisation routines */
- if (state->CPInit[i])
- (state->CPInit[i])(state) ;
- return(TRUE) ;
- }
+ for (i = 0; i < 16; i++) /* Call all the initialisation routines */
+ if (state->CPInit[i])
+ (state->CPInit[i]) (state);
+ return (TRUE);
+}
/***************************************************************************\
* Install co-processor finalisation routines in this routine *
\***************************************************************************/
-void ARMul_CoProExit(ARMul_State *state)
-{register unsigned i ;
+void
+ARMul_CoProExit (ARMul_State * state)
+{
+ register unsigned i;
- for (i = 0 ; i < 16 ; i++)
+ for (i = 0; i < 16; i++)
if (state->CPExit[i])
- (state->CPExit[i])(state) ;
- for (i = 0 ; i < 16 ; i++) /* Detach all handlers */
- ARMul_CoProDetach(state, i) ;
- }
+ (state->CPExit[i]) (state);
+ for (i = 0; i < 16; i++) /* Detach all handlers */
+ ARMul_CoProDetach (state, i);
+}
/***************************************************************************\
* Routines to hook Co-processors into ARMulator *
\***************************************************************************/
-void ARMul_CoProAttach(ARMul_State *state, unsigned number,
- ARMul_CPInits *init, ARMul_CPExits *exit,
- ARMul_LDCs *ldc, ARMul_STCs *stc,
- ARMul_MRCs *mrc, ARMul_MCRs *mcr, ARMul_CDPs *cdp,
- ARMul_CPReads *read, ARMul_CPWrites *write)
-{if (init != NULL)
- state->CPInit[number] = init ;
- if (exit != NULL)
- state->CPExit[number] = exit ;
- if (ldc != NULL)
- state->LDC[number] = ldc ;
- if (stc != NULL)
- state->STC[number] = stc ;
- if (mrc != NULL)
- state->MRC[number] = mrc ;
- if (mcr != NULL)
- state->MCR[number] = mcr ;
- if (cdp != NULL)
- state->CDP[number] = cdp ;
- if (read != NULL)
- state->CPRead[number] = read ;
- if (write != NULL)
- state->CPWrite[number] = write ;
+void
+ARMul_CoProAttach (ARMul_State * state, unsigned number,
+ ARMul_CPInits * init, ARMul_CPExits * exit,
+ ARMul_LDCs * ldc, ARMul_STCs * stc,
+ ARMul_MRCs * mrc, ARMul_MCRs * mcr, ARMul_CDPs * cdp,
+ ARMul_CPReads * read, ARMul_CPWrites * write)
+{
+ if (init != NULL)
+ state->CPInit[number] = init;
+ if (exit != NULL)
+ state->CPExit[number] = exit;
+ if (ldc != NULL)
+ state->LDC[number] = ldc;
+ if (stc != NULL)
+ state->STC[number] = stc;
+ if (mrc != NULL)
+ state->MRC[number] = mrc;
+ if (mcr != NULL)
+ state->MCR[number] = mcr;
+ if (cdp != NULL)
+ state->CDP[number] = cdp;
+ if (read != NULL)
+ state->CPRead[number] = read;
+ if (write != NULL)
+ state->CPWrite[number] = write;
}
-void ARMul_CoProDetach(ARMul_State *state, unsigned number)
-{ARMul_CoProAttach(state, number, NULL, NULL,
- NoCoPro4R, NoCoPro4W, NoCoPro4W, NoCoPro4R,
- NoCoPro3R, NULL, NULL) ;
- state->CPInit[number] = NULL ;
- state->CPExit[number] = NULL ;
- state->CPRead[number] = NULL ;
- state->CPWrite[number] = NULL ;
+void
+ARMul_CoProDetach (ARMul_State * state, unsigned number)
+{
+ ARMul_CoProAttach (state, number, NULL, NULL,
+ NoCoPro4R, NoCoPro4W, NoCoPro4W, NoCoPro4R,
+ NoCoPro3R, NULL, NULL);
+ state->CPInit[number] = NULL;
+ state->CPExit[number] = NULL;
+ state->CPRead[number] = NULL;
+ state->CPWrite[number] = NULL;
}
/***************************************************************************\
* There is no CoPro around, so Undefined Instruction trap *
\***************************************************************************/
-static unsigned NoCoPro3R(ARMul_State *state,unsigned a,ARMword b)
-{return(ARMul_CANT) ;}
+static unsigned
+NoCoPro3R (ARMul_State * state ATTRIBUTE_UNUSED,
+ unsigned a ATTRIBUTE_UNUSED,
+ ARMword b ATTRIBUTE_UNUSED)
+{
+ return (ARMul_CANT);
+}
-static unsigned NoCoPro4R(ARMul_State *state, unsigned a,ARMword b,ARMword c)
-{return(ARMul_CANT) ;}
+static unsigned
+NoCoPro4R (
+ ARMul_State * state ATTRIBUTE_UNUSED,
+ unsigned a ATTRIBUTE_UNUSED,
+ ARMword b ATTRIBUTE_UNUSED,
+ ARMword c ATTRIBUTE_UNUSED)
+{
+ return (ARMul_CANT);
+}
-static unsigned NoCoPro4W(ARMul_State *state, unsigned a,ARMword b,ARMword *c)
-{return(ARMul_CANT) ;}
+static unsigned
+NoCoPro4W (
+ ARMul_State * state ATTRIBUTE_UNUSED,
+ unsigned a ATTRIBUTE_UNUSED,
+ ARMword b ATTRIBUTE_UNUSED,
+ ARMword * c ATTRIBUTE_UNUSED)
+{
+ return (ARMul_CANT);
+}
#define HIGHLOW 2
#ifndef __STDC__
-typedef char * VoidStar ;
+typedef char *VoidStar;
#endif
-typedef unsigned long ARMword ; /* must be 32 bits wide */
-
-typedef struct ARMul_State ARMul_State ;
-
-typedef unsigned ARMul_CPInits(ARMul_State *state) ;
-typedef unsigned ARMul_CPExits(ARMul_State *state) ;
-typedef unsigned ARMul_LDCs(ARMul_State *state,unsigned type,ARMword instr,ARMword value) ;
-typedef unsigned ARMul_STCs(ARMul_State *state,unsigned type,ARMword instr,ARMword *value) ;
-typedef unsigned ARMul_MRCs(ARMul_State *state,unsigned type,ARMword instr,ARMword *value) ;
-typedef unsigned ARMul_MCRs(ARMul_State *state,unsigned type,ARMword instr,ARMword value) ;
-typedef unsigned ARMul_CDPs(ARMul_State *state,unsigned type,ARMword instr) ;
-typedef unsigned ARMul_CPReads(ARMul_State *state,unsigned reg,ARMword *value) ;
-typedef unsigned ARMul_CPWrites(ARMul_State *state,unsigned reg,ARMword value) ;
-
-struct ARMul_State {
- ARMword Emulate ; /* to start and stop emulation */
- unsigned EndCondition ; /* reason for stopping */
- unsigned ErrorCode ; /* type of illegal instruction */
- ARMword Reg[16] ; /* the current register file */
- ARMword RegBank[7][16] ; /* all the registers */
- ARMword Cpsr ; /* the current psr */
- ARMword Spsr[7] ; /* the exception psr's */
- ARMword NFlag, ZFlag, CFlag, VFlag, IFFlags ; /* dummy flags for speed */
+typedef unsigned long ARMword; /* must be 32 bits wide */
+typedef struct ARMul_State ARMul_State;
+
+typedef unsigned ARMul_CPInits (ARMul_State * state);
+typedef unsigned ARMul_CPExits (ARMul_State * state);
+typedef unsigned ARMul_LDCs (ARMul_State * state, unsigned type,
+ ARMword instr, ARMword value);
+typedef unsigned ARMul_STCs (ARMul_State * state, unsigned type,
+ ARMword instr, ARMword * value);
+typedef unsigned ARMul_MRCs (ARMul_State * state, unsigned type,
+ ARMword instr, ARMword * value);
+typedef unsigned ARMul_MCRs (ARMul_State * state, unsigned type,
+ ARMword instr, ARMword value);
+typedef unsigned ARMul_CDPs (ARMul_State * state, unsigned type,
+ ARMword instr);
+typedef unsigned ARMul_CPReads (ARMul_State * state, unsigned reg,
+ ARMword * value);
+typedef unsigned ARMul_CPWrites (ARMul_State * state, unsigned reg,
+ ARMword value);
+
+struct ARMul_State
+{
+ ARMword Emulate; /* to start and stop emulation */
+ unsigned EndCondition; /* reason for stopping */
+ unsigned ErrorCode; /* type of illegal instruction */
+ ARMword Reg[16]; /* the current register file */
+ ARMword RegBank[7][16]; /* all the registers */
+ ARMword Cpsr; /* the current psr */
+ ARMword Spsr[7]; /* the exception psr's */
+ ARMword NFlag, ZFlag, CFlag, VFlag, IFFlags; /* dummy flags for speed */
#ifdef MODET
- ARMword TFlag ; /* Thumb state */
+ ARMword TFlag; /* Thumb state */
#endif
- ARMword Bank ; /* the current register bank */
- ARMword Mode ; /* the current mode */
- ARMword instr, pc, temp ; /* saved register state */
- ARMword loaded, decoded ; /* saved pipeline state */
- unsigned long NumScycles,
- NumNcycles,
- NumIcycles,
- NumCcycles,
- NumFcycles ; /* emulated cycles used */
- unsigned long NumInstrs ; /* the number of instructions executed */
- unsigned NextInstr ;
- unsigned VectorCatch ; /* caught exception mask */
- unsigned CallDebug ; /* set to call the debugger */
- unsigned CanWatch ; /* set by memory interface if its willing to suffer the
- overhead of checking for watchpoints on each memory
- access */
- unsigned MemReadDebug, MemWriteDebug ;
- unsigned long StopHandle ;
-
- unsigned char *MemDataPtr ; /* admin data */
- unsigned char *MemInPtr ; /* the Data In bus */
- unsigned char *MemOutPtr ; /* the Data Out bus (which you may not need */
- unsigned char *MemSparePtr ; /* extra space */
- ARMword MemSize ;
-
- unsigned char *OSptr ; /* OS Handle */
- char *CommandLine ; /* Command Line from ARMsd */
-
- ARMul_CPInits *CPInit[16] ; /* coprocessor initialisers */
- ARMul_CPExits *CPExit[16] ; /* coprocessor finalisers */
- ARMul_LDCs *LDC[16] ; /* LDC instruction */
- ARMul_STCs *STC[16] ; /* STC instruction */
- ARMul_MRCs *MRC[16] ; /* MRC instruction */
- ARMul_MCRs *MCR[16] ; /* MCR instruction */
- ARMul_CDPs *CDP[16] ; /* CDP instruction */
- ARMul_CPReads *CPRead[16] ; /* Read CP register */
- ARMul_CPWrites *CPWrite[16] ; /* Write CP register */
- unsigned char *CPData[16] ; /* Coprocessor data */
- unsigned char const *CPRegWords[16] ; /* map of coprocessor register sizes */
-
- unsigned EventSet ; /* the number of events in the queue */
- unsigned long Now ; /* time to the nearest cycle */
- struct EventNode **EventPtr ; /* the event list */
-
- unsigned Exception ; /* enable the next four values */
- unsigned Debug ; /* show instructions as they are executed */
- unsigned NresetSig ; /* reset the processor */
- unsigned NfiqSig ;
- unsigned NirqSig ;
-
- unsigned abortSig ;
- unsigned NtransSig ;
- unsigned bigendSig ;
- unsigned prog32Sig ;
- unsigned data32Sig ;
- unsigned lateabtSig ;
- ARMword Vector ; /* synthesize aborts in cycle modes */
- ARMword Aborted ; /* sticky flag for aborts */
- ARMword Reseted ; /* sticky flag for Reset */
- ARMword Inted, LastInted ; /* sticky flags for interrupts */
- ARMword Base ; /* extra hand for base writeback */
- ARMword AbortAddr ; /* to keep track of Prefetch aborts */
-
- const struct Dbg_HostosInterface *hostif;
-
- int verbose; /* non-zero means print various messages like the banner */
- } ;
+ ARMword Bank; /* the current register bank */
+ ARMword Mode; /* the current mode */
+ ARMword instr, pc, temp; /* saved register state */
+ ARMword loaded, decoded; /* saved pipeline state */
+ unsigned long NumScycles, NumNcycles, NumIcycles, NumCcycles, NumFcycles; /* emulated cycles used */
+ unsigned long NumInstrs; /* the number of instructions executed */
+ unsigned NextInstr;
+ unsigned VectorCatch; /* caught exception mask */
+ unsigned CallDebug; /* set to call the debugger */
+ unsigned CanWatch; /* set by memory interface if its willing to suffer the
+ overhead of checking for watchpoints on each memory
+ access */
+ unsigned MemReadDebug, MemWriteDebug;
+ unsigned long StopHandle;
+
+ unsigned char *MemDataPtr; /* admin data */
+ unsigned char *MemInPtr; /* the Data In bus */
+ unsigned char *MemOutPtr; /* the Data Out bus (which you may not need */
+ unsigned char *MemSparePtr; /* extra space */
+ ARMword MemSize;
+
+ unsigned char *OSptr; /* OS Handle */
+ char *CommandLine; /* Command Line from ARMsd */
+
+ ARMul_CPInits *CPInit[16]; /* coprocessor initialisers */
+ ARMul_CPExits *CPExit[16]; /* coprocessor finalisers */
+ ARMul_LDCs *LDC[16]; /* LDC instruction */
+ ARMul_STCs *STC[16]; /* STC instruction */
+ ARMul_MRCs *MRC[16]; /* MRC instruction */
+ ARMul_MCRs *MCR[16]; /* MCR instruction */
+ ARMul_CDPs *CDP[16]; /* CDP instruction */
+ ARMul_CPReads *CPRead[16]; /* Read CP register */
+ ARMul_CPWrites *CPWrite[16]; /* Write CP register */
+ unsigned char *CPData[16]; /* Coprocessor data */
+ unsigned char const *CPRegWords[16]; /* map of coprocessor register sizes */
+
+ unsigned EventSet; /* the number of events in the queue */
+ unsigned long Now; /* time to the nearest cycle */
+ struct EventNode **EventPtr; /* the event list */
+
+ unsigned Exception; /* enable the next four values */
+ unsigned Debug; /* show instructions as they are executed */
+ unsigned NresetSig; /* reset the processor */
+ unsigned NfiqSig;
+ unsigned NirqSig;
+
+ unsigned abortSig;
+ unsigned NtransSig;
+ unsigned bigendSig;
+ unsigned prog32Sig;
+ unsigned data32Sig;
+ unsigned lateabtSig;
+ ARMword Vector; /* synthesize aborts in cycle modes */
+ ARMword Aborted; /* sticky flag for aborts */
+ ARMword Reseted; /* sticky flag for Reset */
+ ARMword Inted, LastInted; /* sticky flags for interrupts */
+ ARMword Base; /* extra hand for base writeback */
+ ARMword AbortAddr; /* to keep track of Prefetch aborts */
+
+ const struct Dbg_HostosInterface *hostif;
+
+ int verbose; /* non-zero means print various messages like the banner */
+};
#define ResetPin NresetSig
#define FIQPin NfiqSig
/***************************************************************************\
* Types of ARM we know about *
\***************************************************************************/
-
+
/* The bitflags */
#define ARM_Fix26_Prop 0x01
#define ARM_Nexec_Prop 0x02
#define ARM_Debug_Prop 0x10
#define ARM_Isync_Prop ARM_Debug_Prop
#define ARM_Lock_Prop 0x20
-
+
/* ARM2 family */
#define ARM2 (ARM_Fix26_Prop)
#define ARM2as ARM2
#define ARM61 ARM2
#define ARM3 ARM2
-#ifdef ARM60 /* previous definition in armopts.h */
+#ifdef ARM60 /* previous definition in armopts.h */
#undef ARM60
#endif
#define ARM600 ARM6
#define ARM610 ARM6
#define ARM620 ARM6
-
+
/***************************************************************************\
* Macros to extract instruction fields *
\***************************************************************************/
-#define BIT(n) ( (ARMword)(instr>>(n))&1) /* bit n of instruction */
-#define BITS(m,n) ( (ARMword)(instr<<(31-(n))) >> ((31-(n))+(m)) ) /* bits m to n of instr */
-#define TOPBITS(n) (instr >> (n)) /* bits 31 to n of instr */
+#define BIT(n) ( (ARMword)(instr>>(n))&1) /* bit n of instruction */
+#define BITS(m,n) ( (ARMword)(instr<<(31-(n))) >> ((31-(n))+(m)) ) /* bits m to n of instr */
+#define TOPBITS(n) (instr >> (n)) /* bits 31 to n of instr */
/***************************************************************************\
* The hardware vector addresses *
#define ARMAddrExceptnV 20L
#define ARMIRQV 24L
#define ARMFIQV 28L
-#define ARMErrorV 32L /* This is an offset, not an address ! */
+#define ARMErrorV 32L /* This is an offset, not an address ! */
#define ARMul_ResetV ARMResetV
#define ARMul_UndefinedInstrV ARMUndefinedInstrV
* Definitons of things in the emulator *
\***************************************************************************/
-extern void ARMul_EmulateInit(void) ;
-extern ARMul_State *ARMul_NewState(void) ;
-extern void ARMul_Reset(ARMul_State *state) ;
-extern ARMword ARMul_DoProg(ARMul_State *state) ;
-extern ARMword ARMul_DoInstr(ARMul_State *state) ;
+extern void ARMul_EmulateInit (void);
+extern ARMul_State *ARMul_NewState (void);
+extern void ARMul_Reset (ARMul_State * state);
+extern ARMword ARMul_DoProg (ARMul_State * state);
+extern ARMword ARMul_DoInstr (ARMul_State * state);
/***************************************************************************\
* Definitons of things for event handling *
\***************************************************************************/
-extern void ARMul_ScheduleEvent(ARMul_State *state, unsigned long delay, unsigned (*func)() ) ;
-extern void ARMul_EnvokeEvent(ARMul_State *state) ;
-extern unsigned long ARMul_Time(ARMul_State *state) ;
+extern void ARMul_ScheduleEvent (ARMul_State * state, unsigned long delay,
+ unsigned (*func) ());
+extern void ARMul_EnvokeEvent (ARMul_State * state);
+extern unsigned long ARMul_Time (ARMul_State * state);
/***************************************************************************\
* Useful support routines *
\***************************************************************************/
-extern ARMword ARMul_GetReg(ARMul_State *state, unsigned mode, unsigned reg) ;
-extern void ARMul_SetReg(ARMul_State *state, unsigned mode, unsigned reg, ARMword value) ;
-extern ARMword ARMul_GetPC(ARMul_State *state) ;
-extern ARMword ARMul_GetNextPC(ARMul_State *state) ;
-extern void ARMul_SetPC(ARMul_State *state, ARMword value) ;
-extern ARMword ARMul_GetR15(ARMul_State *state) ;
-extern void ARMul_SetR15(ARMul_State *state, ARMword value) ;
-
-extern ARMword ARMul_GetCPSR(ARMul_State *state) ;
-extern void ARMul_SetCPSR(ARMul_State *state, ARMword value) ;
-extern ARMword ARMul_GetSPSR(ARMul_State *state, ARMword mode) ;
-extern void ARMul_SetSPSR(ARMul_State *state, ARMword mode, ARMword value) ;
+extern ARMword ARMul_GetReg (ARMul_State * state, unsigned mode,
+ unsigned reg);
+extern void ARMul_SetReg (ARMul_State * state, unsigned mode, unsigned reg,
+ ARMword value);
+extern ARMword ARMul_GetPC (ARMul_State * state);
+extern ARMword ARMul_GetNextPC (ARMul_State * state);
+extern void ARMul_SetPC (ARMul_State * state, ARMword value);
+extern ARMword ARMul_GetR15 (ARMul_State * state);
+extern void ARMul_SetR15 (ARMul_State * state, ARMword value);
+
+extern ARMword ARMul_GetCPSR (ARMul_State * state);
+extern void ARMul_SetCPSR (ARMul_State * state, ARMword value);
+extern ARMword ARMul_GetSPSR (ARMul_State * state, ARMword mode);
+extern void ARMul_SetSPSR (ARMul_State * state, ARMword mode, ARMword value);
/***************************************************************************\
* Definitons of things to handle aborts *
\***************************************************************************/
-extern void ARMul_Abort(ARMul_State *state, ARMword address) ;
-#define ARMul_ABORTWORD 0xefffffff /* SWI -1 */
+extern void ARMul_Abort (ARMul_State * state, ARMword address);
+#define ARMul_ABORTWORD 0xefffffff /* SWI -1 */
#define ARMul_PREFETCHABORT(address) if (state->AbortAddr == 1) \
state->AbortAddr = (address & ~3L)
#define ARMul_DATAABORT(address) state->abortSig = HIGH ; \
* Definitons of things in the memory interface *
\***************************************************************************/
-extern unsigned ARMul_MemoryInit(ARMul_State *state,unsigned long initmemsize) ;
-extern void ARMul_MemoryExit(ARMul_State *state) ;
-
-extern ARMword ARMul_LoadInstrS(ARMul_State *state,ARMword address,ARMword isize) ;
-extern ARMword ARMul_LoadInstrN(ARMul_State *state,ARMword address,ARMword isize) ;
-extern ARMword ARMul_ReLoadInstr(ARMul_State *state,ARMword address,ARMword isize) ;
-
-extern ARMword ARMul_LoadWordS(ARMul_State *state,ARMword address) ;
-extern ARMword ARMul_LoadWordN(ARMul_State *state,ARMword address) ;
-extern ARMword ARMul_LoadHalfWord(ARMul_State *state,ARMword address) ;
-extern ARMword ARMul_LoadByte(ARMul_State *state,ARMword address) ;
-
-extern void ARMul_StoreWordS(ARMul_State *state,ARMword address, ARMword data) ;
-extern void ARMul_StoreWordN(ARMul_State *state,ARMword address, ARMword data) ;
-extern void ARMul_StoreHalfWord(ARMul_State *state,ARMword address, ARMword data) ;
-extern void ARMul_StoreByte(ARMul_State *state,ARMword address, ARMword data) ;
-
-extern ARMword ARMul_SwapWord(ARMul_State *state,ARMword address, ARMword data) ;
-extern ARMword ARMul_SwapByte(ARMul_State *state,ARMword address, ARMword data) ;
-
-extern void ARMul_Icycles(ARMul_State *state,unsigned number, ARMword address) ;
-extern void ARMul_Ccycles(ARMul_State *state,unsigned number, ARMword address) ;
-
-extern ARMword ARMul_ReadWord(ARMul_State *state,ARMword address) ;
-extern ARMword ARMul_ReadByte(ARMul_State *state,ARMword address) ;
-extern void ARMul_WriteWord(ARMul_State *state,ARMword address, ARMword data) ;
-extern void ARMul_WriteByte(ARMul_State *state,ARMword address, ARMword data) ;
-
-extern ARMword ARMul_MemAccess(ARMul_State *state,ARMword,ARMword,ARMword,
- ARMword,ARMword,ARMword,ARMword,ARMword,ARMword,ARMword) ;
+extern unsigned ARMul_MemoryInit (ARMul_State * state,
+ unsigned long initmemsize);
+extern void ARMul_MemoryExit (ARMul_State * state);
+
+extern ARMword ARMul_LoadInstrS (ARMul_State * state, ARMword address,
+ ARMword isize);
+extern ARMword ARMul_LoadInstrN (ARMul_State * state, ARMword address,
+ ARMword isize);
+extern ARMword ARMul_ReLoadInstr (ARMul_State * state, ARMword address,
+ ARMword isize);
+
+extern ARMword ARMul_LoadWordS (ARMul_State * state, ARMword address);
+extern ARMword ARMul_LoadWordN (ARMul_State * state, ARMword address);
+extern ARMword ARMul_LoadHalfWord (ARMul_State * state, ARMword address);
+extern ARMword ARMul_LoadByte (ARMul_State * state, ARMword address);
+
+extern void ARMul_StoreWordS (ARMul_State * state, ARMword address,
+ ARMword data);
+extern void ARMul_StoreWordN (ARMul_State * state, ARMword address,
+ ARMword data);
+extern void ARMul_StoreHalfWord (ARMul_State * state, ARMword address,
+ ARMword data);
+extern void ARMul_StoreByte (ARMul_State * state, ARMword address,
+ ARMword data);
+
+extern ARMword ARMul_SwapWord (ARMul_State * state, ARMword address,
+ ARMword data);
+extern ARMword ARMul_SwapByte (ARMul_State * state, ARMword address,
+ ARMword data);
+
+extern void ARMul_Icycles (ARMul_State * state, unsigned number,
+ ARMword address);
+extern void ARMul_Ccycles (ARMul_State * state, unsigned number,
+ ARMword address);
+
+extern ARMword ARMul_ReadWord (ARMul_State * state, ARMword address);
+extern ARMword ARMul_ReadByte (ARMul_State * state, ARMword address);
+extern void ARMul_WriteWord (ARMul_State * state, ARMword address,
+ ARMword data);
+extern void ARMul_WriteByte (ARMul_State * state, ARMword address,
+ ARMword data);
+
+extern ARMword ARMul_MemAccess (ARMul_State * state, ARMword, ARMword,
+ ARMword, ARMword, ARMword, ARMword, ARMword,
+ ARMword, ARMword, ARMword);
/***************************************************************************\
* Definitons of things in the co-processor interface *
#define ARMul_CANT 1
#define ARMul_INC 3
-extern unsigned ARMul_CoProInit(ARMul_State *state) ;
-extern void ARMul_CoProExit(ARMul_State *state) ;
-extern void ARMul_CoProAttach(ARMul_State *state, unsigned number,
- ARMul_CPInits *init, ARMul_CPExits *exit,
- ARMul_LDCs *ldc, ARMul_STCs *stc,
- ARMul_MRCs *mrc, ARMul_MCRs *mcr,
- ARMul_CDPs *cdp,
- ARMul_CPReads *read, ARMul_CPWrites *write) ;
-extern void ARMul_CoProDetach(ARMul_State *state, unsigned number) ;
+extern unsigned ARMul_CoProInit (ARMul_State * state);
+extern void ARMul_CoProExit (ARMul_State * state);
+extern void ARMul_CoProAttach (ARMul_State * state, unsigned number,
+ ARMul_CPInits * init, ARMul_CPExits * exit,
+ ARMul_LDCs * ldc, ARMul_STCs * stc,
+ ARMul_MRCs * mrc, ARMul_MCRs * mcr,
+ ARMul_CDPs * cdp,
+ ARMul_CPReads * read, ARMul_CPWrites * write);
+extern void ARMul_CoProDetach (ARMul_State * state, unsigned number);
/***************************************************************************\
* Definitons of things in the host environment *
\***************************************************************************/
-extern unsigned ARMul_OSInit(ARMul_State *state) ;
-extern void ARMul_OSExit(ARMul_State *state) ;
-extern unsigned ARMul_OSHandleSWI(ARMul_State *state,ARMword number) ;
-extern ARMword ARMul_OSLastErrorP(ARMul_State *state) ;
+extern unsigned ARMul_OSInit (ARMul_State * state);
+extern void ARMul_OSExit (ARMul_State * state);
+extern unsigned ARMul_OSHandleSWI (ARMul_State * state, ARMword number);
+extern ARMword ARMul_OSLastErrorP (ARMul_State * state);
-extern ARMword ARMul_Debug(ARMul_State *state, ARMword pc, ARMword instr) ;
-extern unsigned ARMul_OSException(ARMul_State *state, ARMword vector, ARMword pc) ;
-extern int rdi_log ;
+extern ARMword ARMul_Debug (ARMul_State * state, ARMword pc, ARMword instr);
+extern unsigned ARMul_OSException (ARMul_State * state, ARMword vector,
+ ARMword pc);
+extern int rdi_log;
/***************************************************************************\
* Host-dependent stuff *
\***************************************************************************/
#ifdef macintosh
-pascal void SpinCursor(short increment); /* copied from CursorCtl.h */
+pascal void SpinCursor (short increment); /* copied from CursorCtl.h */
# define HOURGLASS SpinCursor( 1 )
-# define HOURGLASS_RATE 1023 /* 2^n - 1 */
+# define HOURGLASS_RATE 1023 /* 2^n - 1 */
#endif
+extern void ARMul_UndefInstr (ARMul_State *, ARMword);
+extern void ARMul_FixCPSR (ARMul_State *, ARMword, ARMword);
+extern void ARMul_FixSPSR (ARMul_State *, ARMword, ARMword);
+extern void ARMul_ConsolePrint (ARMul_State *, const char *, ...);
+extern void ARMul_SelectProcessor (ARMul_State *, unsigned);
#include "armdefs.h"
#include "armemu.h"
-
-static ARMword GetDPRegRHS(ARMul_State *state, ARMword instr) ;
-static ARMword GetDPSRegRHS(ARMul_State *state, ARMword instr) ;
-static void WriteR15(ARMul_State *state, ARMword src) ;
-static void WriteSR15(ARMul_State *state, ARMword src) ;
-static ARMword GetLSRegRHS(ARMul_State *state, ARMword instr) ;
-static ARMword GetLS7RHS(ARMul_State *state, ARMword instr) ;
-static unsigned LoadWord(ARMul_State *state, ARMword instr, ARMword address) ;
-static unsigned LoadHalfWord(ARMul_State *state, ARMword instr, ARMword address,int signextend) ;
-static unsigned LoadByte(ARMul_State *state, ARMword instr, ARMword address,int signextend) ;
-static unsigned StoreWord(ARMul_State *state, ARMword instr, ARMword address) ;
-static unsigned StoreHalfWord(ARMul_State *state, ARMword instr, ARMword address) ;
-static unsigned StoreByte(ARMul_State *state, ARMword instr, ARMword address) ;
-static void LoadMult(ARMul_State *state, ARMword address, ARMword instr, ARMword WBBase) ;
-static void StoreMult(ARMul_State *state, ARMword address, ARMword instr, ARMword WBBase) ;
-static void LoadSMult(ARMul_State *state, ARMword address, ARMword instr, ARMword WBBase) ;
-static void StoreSMult(ARMul_State *state, ARMword address, ARMword instr, ARMword WBBase) ;
-static unsigned Multiply64(ARMul_State *state, ARMword instr,int signextend,int scc) ;
-static unsigned MultiplyAdd64(ARMul_State *state, ARMword instr,int signextend,int scc) ;
-
-#define LUNSIGNED (0) /* unsigned operation */
-#define LSIGNED (1) /* signed operation */
-#define LDEFAULT (0) /* default : do nothing */
-#define LSCC (1) /* set condition codes on result */
+#include "armos.h"
+
+static ARMword GetDPRegRHS (ARMul_State * state, ARMword instr);
+static ARMword GetDPSRegRHS (ARMul_State * state, ARMword instr);
+static void WriteR15 (ARMul_State * state, ARMword src);
+static void WriteSR15 (ARMul_State * state, ARMword src);
+static ARMword GetLSRegRHS (ARMul_State * state, ARMword instr);
+static ARMword GetLS7RHS (ARMul_State * state, ARMword instr);
+static unsigned LoadWord (ARMul_State * state, ARMword instr,
+ ARMword address);
+static unsigned LoadHalfWord (ARMul_State * state, ARMword instr,
+ ARMword address, int signextend);
+static unsigned LoadByte (ARMul_State * state, ARMword instr, ARMword address,
+ int signextend);
+static unsigned StoreWord (ARMul_State * state, ARMword instr,
+ ARMword address);
+static unsigned StoreHalfWord (ARMul_State * state, ARMword instr,
+ ARMword address);
+static unsigned StoreByte (ARMul_State * state, ARMword instr,
+ ARMword address);
+static void LoadMult (ARMul_State * state, ARMword address, ARMword instr,
+ ARMword WBBase);
+static void StoreMult (ARMul_State * state, ARMword address, ARMword instr,
+ ARMword WBBase);
+static void LoadSMult (ARMul_State * state, ARMword address, ARMword instr,
+ ARMword WBBase);
+static void StoreSMult (ARMul_State * state, ARMword address, ARMword instr,
+ ARMword WBBase);
+static unsigned Multiply64 (ARMul_State * state, ARMword instr,
+ int signextend, int scc);
+static unsigned MultiplyAdd64 (ARMul_State * state, ARMword instr,
+ int signextend, int scc);
+
+#define LUNSIGNED (0) /* unsigned operation */
+#define LSIGNED (1) /* signed operation */
+#define LDEFAULT (0) /* default : do nothing */
+#define LSCC (1) /* set condition codes on result */
+
+#ifdef NEED_UI_LOOP_HOOK
+/* How often to run the ui_loop update, when in use */
+#define UI_LOOP_POLL_INTERVAL 0x32000
+
+/* Counter for the ui_loop_hook update */
+static long ui_loop_hook_counter = UI_LOOP_POLL_INTERVAL;
+
+/* Actual hook to call to run through gdb's gui event loop */
+extern int (*ui_loop_hook) (int);
+#endif /* NEED_UI_LOOP_HOOK */
+
+extern int stop_simulator;
/***************************************************************************\
* short-hand macros for LDR/STR *
/* store pre increment */
#define SHPREUP() \
- (void)StoreHalfWord(state, instr, LHS + GetLS7RHS(state, instr)) ;
+ (void)StoreHalfWord(state, instr, LHS + GetLS7RHS(state, instr)) ;
/* store pre increment writeback */
#define SHPREUPWB() \
ARMword isize;
#ifdef MODE32
-ARMword ARMul_Emulate32(register ARMul_State *state)
+ARMword
+ARMul_Emulate32 (register ARMul_State * state)
{
#else
-ARMword ARMul_Emulate26(register ARMul_State *state)
+ARMword
+ARMul_Emulate26 (register ARMul_State * state)
{
#endif
- register ARMword instr, /* the current instruction */
- dest, /* almost the DestBus */
- temp, /* ubiquitous third hand */
- pc ; /* the address of the current instruction */
- ARMword lhs, rhs ; /* almost the ABus and BBus */
- ARMword decoded, loaded ; /* instruction pipeline */
+ register ARMword instr, /* the current instruction */
+ dest = 0, /* almost the DestBus */
+ temp, /* ubiquitous third hand */
+ pc = 0; /* the address of the current instruction */
+ ARMword lhs, rhs; /* almost the ABus and BBus */
+ ARMword decoded = 0, loaded = 0; /* instruction pipeline */
/***************************************************************************\
* Execute the next instruction *
\***************************************************************************/
- if (state->NextInstr < PRIMEPIPE) {
- decoded = state->decoded ;
- loaded = state->loaded ;
- pc = state->pc ;
+ if (state->NextInstr < PRIMEPIPE)
+ {
+ decoded = state->decoded;
+ loaded = state->loaded;
+ pc = state->pc;
}
- do { /* just keep going */
+ do
+ { /* just keep going */
#ifdef MODET
- if (TFLAG) {
- isize = 2;
- } else
-#endif
- isize = 4;
- switch (state->NextInstr) {
- case SEQ :
- state->Reg[15] += isize ; /* Advance the pipeline, and an S cycle */
- pc += isize ;
- instr = decoded ;
- decoded = loaded ;
- loaded = ARMul_LoadInstrS(state,pc+(isize * 2),isize) ;
- break ;
-
- case NONSEQ :
- state->Reg[15] += isize ; /* Advance the pipeline, and an N cycle */
- pc += isize ;
- instr = decoded ;
- decoded = loaded ;
- loaded = ARMul_LoadInstrN(state,pc+(isize * 2),isize) ;
- NORMALCYCLE ;
- break ;
-
- case PCINCEDSEQ :
- pc += isize ; /* Program counter advanced, and an S cycle */
- instr = decoded ;
- decoded = loaded ;
- loaded = ARMul_LoadInstrS(state,pc+(isize * 2),isize) ;
- NORMALCYCLE ;
- break ;
-
- case PCINCEDNONSEQ :
- pc += isize ; /* Program counter advanced, and an N cycle */
- instr = decoded ;
- decoded = loaded ;
- loaded = ARMul_LoadInstrN(state,pc+(isize * 2),isize) ;
- NORMALCYCLE ;
- break ;
-
- case RESUME : /* The program counter has been changed */
- pc = state->Reg[15] ;
+ if (TFLAG)
+ {
+ isize = 2;
+ }
+ else
+#endif
+ isize = 4;
+ switch (state->NextInstr)
+ {
+ case SEQ:
+ state->Reg[15] += isize; /* Advance the pipeline, and an S cycle */
+ pc += isize;
+ instr = decoded;
+ decoded = loaded;
+ loaded = ARMul_LoadInstrS (state, pc + (isize * 2), isize);
+ break;
+
+ case NONSEQ:
+ state->Reg[15] += isize; /* Advance the pipeline, and an N cycle */
+ pc += isize;
+ instr = decoded;
+ decoded = loaded;
+ loaded = ARMul_LoadInstrN (state, pc + (isize * 2), isize);
+ NORMALCYCLE;
+ break;
+
+ case PCINCEDSEQ:
+ pc += isize; /* Program counter advanced, and an S cycle */
+ instr = decoded;
+ decoded = loaded;
+ loaded = ARMul_LoadInstrS (state, pc + (isize * 2), isize);
+ NORMALCYCLE;
+ break;
+
+ case PCINCEDNONSEQ:
+ pc += isize; /* Program counter advanced, and an N cycle */
+ instr = decoded;
+ decoded = loaded;
+ loaded = ARMul_LoadInstrN (state, pc + (isize * 2), isize);
+ NORMALCYCLE;
+ break;
+
+ case RESUME: /* The program counter has been changed */
+ pc = state->Reg[15];
#ifndef MODE32
- pc = pc & R15PCBITS ;
-#endif
- state->Reg[15] = pc + (isize * 2) ;
- state->Aborted = 0 ;
- instr = ARMul_ReLoadInstr(state,pc,isize) ;
- decoded = ARMul_ReLoadInstr(state,pc + isize,isize) ;
- loaded = ARMul_ReLoadInstr(state,pc + isize * 2,isize) ;
- NORMALCYCLE ;
- break ;
-
- default : /* The program counter has been changed */
- pc = state->Reg[15] ;
+ pc = pc & R15PCBITS;
+#endif
+ state->Reg[15] = pc + (isize * 2);
+ state->Aborted = 0;
+ instr = ARMul_ReLoadInstr (state, pc, isize);
+ decoded = ARMul_ReLoadInstr (state, pc + isize, isize);
+ loaded = ARMul_ReLoadInstr (state, pc + isize * 2, isize);
+ NORMALCYCLE;
+ break;
+
+ default: /* The program counter has been changed */
+ pc = state->Reg[15];
#ifndef MODE32
- pc = pc & R15PCBITS ;
-#endif
- state->Reg[15] = pc + (isize * 2) ;
- state->Aborted = 0 ;
- instr = ARMul_LoadInstrN(state,pc,isize) ;
- decoded = ARMul_LoadInstrS(state,pc + (isize),isize) ;
- loaded = ARMul_LoadInstrS(state,pc + (isize * 2),isize) ;
- NORMALCYCLE ;
- break ;
- }
- if (state->EventSet)
- ARMul_EnvokeEvent(state) ;
-
+ pc = pc & R15PCBITS;
+#endif
+ state->Reg[15] = pc + (isize * 2);
+ state->Aborted = 0;
+ instr = ARMul_LoadInstrN (state, pc, isize);
+ decoded = ARMul_LoadInstrS (state, pc + (isize), isize);
+ loaded = ARMul_LoadInstrS (state, pc + (isize * 2), isize);
+ NORMALCYCLE;
+ break;
+ }
+ if (state->EventSet)
+ ARMul_EnvokeEvent (state);
+
#if 0
- /* Enable this for a helpful bit of debugging when tracing is needed. */
- fprintf (stderr, "pc: %x, instr: %x\n", pc & ~1, instr);
- if (instr == 0) abort ();
-#endif
-
- if (state->Exception) { /* Any exceptions */
- if (state->NresetSig == LOW) {
- ARMul_Abort(state,ARMul_ResetV) ;
- break ;
- }
- else if (!state->NfiqSig && !FFLAG) {
- ARMul_Abort(state,ARMul_FIQV) ;
- break ;
- }
- else if (!state->NirqSig && !IFLAG) {
- ARMul_Abort(state,ARMul_IRQV) ;
- break ;
- }
- }
-
- if (state->CallDebug > 0) {
- instr = ARMul_Debug(state,pc,instr) ;
- if (state->Emulate < ONCE) {
- state->NextInstr = RESUME ;
- break ;
- }
- if (state->Debug) {
- fprintf(stderr,"At %08lx Instr %08lx Mode %02lx\n",pc,instr,state->Mode) ;
- (void)fgetc(stdin) ;
- }
- }
- else
- if (state->Emulate < ONCE) {
- state->NextInstr = RESUME ;
- break ;
- }
-
- state->NumInstrs++ ;
+ /* Enable this for a helpful bit of debugging when tracing is needed. */
+ fprintf (stderr, "pc: %x, instr: %x\n", pc & ~1, instr);
+ if (instr == 0)
+ abort ();
+#endif
+
+ if (state->Exception)
+ { /* Any exceptions */
+ if (state->NresetSig == LOW)
+ {
+ ARMul_Abort (state, ARMul_ResetV);
+ break;
+ }
+ else if (!state->NfiqSig && !FFLAG)
+ {
+ ARMul_Abort (state, ARMul_FIQV);
+ break;
+ }
+ else if (!state->NirqSig && !IFLAG)
+ {
+ ARMul_Abort (state, ARMul_IRQV);
+ break;
+ }
+ }
+
+ if (state->CallDebug > 0)
+ {
+ instr = ARMul_Debug (state, pc, instr);
+ if (state->Emulate < ONCE)
+ {
+ state->NextInstr = RESUME;
+ break;
+ }
+ if (state->Debug)
+ {
+ fprintf (stderr, "At %08lx Instr %08lx Mode %02lx\n", pc, instr,
+ state->Mode);
+ (void) fgetc (stdin);
+ }
+ }
+ else if (state->Emulate < ONCE)
+ {
+ state->NextInstr = RESUME;
+ break;
+ }
+
+ state->NumInstrs++;
#ifdef MODET
- /* Provide Thumb instruction decoding. If the processor is in Thumb
- mode, then we can simply decode the Thumb instruction, and map it
- to the corresponding ARM instruction (by directly loading the
- instr variable, and letting the normal ARM simulator
- execute). There are some caveats to ensure that the correct
- pipelined PC value is used when executing Thumb code, and also for
- dealing with the BL instruction. */
- if (TFLAG) { /* check if in Thumb mode */
- ARMword new;
- switch (ARMul_ThumbDecode(state,pc,instr,&new)) {
- case t_undefined:
- ARMul_UndefInstr(state,instr); /* This is a Thumb instruction */
- break;
-
- case t_branch: /* already processed */
- goto donext;
-
- case t_decoded: /* ARM instruction available */
- instr = new; /* so continue instruction decoding */
- break;
- }
- }
+ /* Provide Thumb instruction decoding. If the processor is in Thumb
+ mode, then we can simply decode the Thumb instruction, and map it
+ to the corresponding ARM instruction (by directly loading the
+ instr variable, and letting the normal ARM simulator
+ execute). There are some caveats to ensure that the correct
+ pipelined PC value is used when executing Thumb code, and also for
+ dealing with the BL instruction. */
+ if (TFLAG)
+ { /* check if in Thumb mode */
+ ARMword new;
+ switch (ARMul_ThumbDecode (state, pc, instr, &new))
+ {
+ case t_undefined:
+ ARMul_UndefInstr (state, instr); /* This is a Thumb instruction */
+ break;
+
+ case t_branch: /* already processed */
+ goto donext;
+
+ case t_decoded: /* ARM instruction available */
+ instr = new; /* so continue instruction decoding */
+ break;
+ }
+ }
#endif
/***************************************************************************\
* Check the condition codes *
\***************************************************************************/
- if ((temp = TOPBITS(28)) == AL)
- goto mainswitch ; /* vile deed in the need for speed */
-
- switch ((int)TOPBITS(28)) { /* check the condition code */
- case AL : temp=TRUE ;
- break ;
- case NV : temp=FALSE ;
- break ;
- case EQ : temp=ZFLAG ;
- break ;
- case NE : temp=!ZFLAG ;
- break ;
- case VS : temp=VFLAG ;
- break ;
- case VC : temp=!VFLAG ;
- break ;
- case MI : temp=NFLAG ;
- break ;
- case PL : temp=!NFLAG ;
- break ;
- case CS : temp=CFLAG ;
- break ;
- case CC : temp=!CFLAG ;
- break ;
- case HI : temp=(CFLAG && !ZFLAG) ;
- break ;
- case LS : temp=(!CFLAG || ZFLAG) ;
- break ;
- case GE : temp=((!NFLAG && !VFLAG) || (NFLAG && VFLAG)) ;
- break ;
- case LT : temp=((NFLAG && !VFLAG) || (!NFLAG && VFLAG)) ;
- break ;
- case GT : temp=((!NFLAG && !VFLAG && !ZFLAG) || (NFLAG && VFLAG && !ZFLAG)) ;
- break ;
- case LE : temp=((NFLAG && !VFLAG) || (!NFLAG && VFLAG)) || ZFLAG ;
- break ;
- } /* cc check */
+ if ((temp = TOPBITS (28)) == AL)
+ goto mainswitch; /* vile deed in the need for speed */
+
+ switch ((int) TOPBITS (28))
+ { /* check the condition code */
+ case AL:
+ temp = TRUE;
+ break;
+ case NV:
+ temp = FALSE;
+ break;
+ case EQ:
+ temp = ZFLAG;
+ break;
+ case NE:
+ temp = !ZFLAG;
+ break;
+ case VS:
+ temp = VFLAG;
+ break;
+ case VC:
+ temp = !VFLAG;
+ break;
+ case MI:
+ temp = NFLAG;
+ break;
+ case PL:
+ temp = !NFLAG;
+ break;
+ case CS:
+ temp = CFLAG;
+ break;
+ case CC:
+ temp = !CFLAG;
+ break;
+ case HI:
+ temp = (CFLAG && !ZFLAG);
+ break;
+ case LS:
+ temp = (!CFLAG || ZFLAG);
+ break;
+ case GE:
+ temp = ((!NFLAG && !VFLAG) || (NFLAG && VFLAG));
+ break;
+ case LT:
+ temp = ((NFLAG && !VFLAG) || (!NFLAG && VFLAG));
+ break;
+ case GT:
+ temp = ((!NFLAG && !VFLAG && !ZFLAG) || (NFLAG && VFLAG && !ZFLAG));
+ break;
+ case LE:
+ temp = ((NFLAG && !VFLAG) || (!NFLAG && VFLAG)) || ZFLAG;
+ break;
+ } /* cc check */
/***************************************************************************\
* Actual execution of instructions begins here *
\***************************************************************************/
- if (temp) { /* if the condition codes don't match, stop here */
-mainswitch:
+ if (temp)
+ { /* if the condition codes don't match, stop here */
+ mainswitch:
+
- switch ((int)BITS(20,27)) {
+ switch ((int) BITS (20, 27))
+ {
/***************************************************************************\
* Data Processing Register RHS Instructions *
\***************************************************************************/
- case 0x00 : /* AND reg and MUL */
+ case 0x00: /* AND reg and MUL */
#ifdef MODET
- if (BITS(4,11) == 0xB) {
- /* STRH register offset, no write-back, down, post indexed */
- SHDOWNWB() ;
- break ;
- }
- /* TODO: CHECK: should 0xD and 0xF generate undefined intruction aborts? */
-#endif
- if (BITS(4,7) == 9) { /* MUL */
- rhs = state->Reg[MULRHSReg] ;
- if (MULLHSReg == MULDESTReg) {
- UNDEF_MULDestEQOp1 ;
- state->Reg[MULDESTReg] = 0 ;
- }
- else if (MULDESTReg != 15)
- state->Reg[MULDESTReg] = state->Reg[MULLHSReg] * rhs ;
- else {
- UNDEF_MULPCDest ;
- }
- for (dest = 0, temp = 0 ; dest < 32 ; dest++)
- if (rhs & (1L << dest))
- temp = dest ; /* mult takes this many/2 I cycles */
- ARMul_Icycles(state,ARMul_MultTable[temp],0L) ;
- }
- else { /* AND reg */
- rhs = DPRegRHS ;
- dest = LHS & rhs ;
- WRITEDEST(dest) ;
- }
- break ;
-
- case 0x01 : /* ANDS reg and MULS */
+ if (BITS (4, 11) == 0xB)
+ {
+ /* STRH register offset, no write-back, down, post indexed */
+ SHDOWNWB ();
+ break;
+ }
+ /* TODO: CHECK: should 0xD and 0xF generate undefined intruction aborts? */
+#endif
+ if (BITS (4, 7) == 9)
+ { /* MUL */
+ rhs = state->Reg[MULRHSReg];
+ if (MULLHSReg == MULDESTReg)
+ {
+ UNDEF_MULDestEQOp1;
+ state->Reg[MULDESTReg] = 0;
+ }
+ else if (MULDESTReg != 15)
+ state->Reg[MULDESTReg] = state->Reg[MULLHSReg] * rhs;
+ else
+ {
+ UNDEF_MULPCDest;
+ }
+ for (dest = 0, temp = 0; dest < 32; dest++)
+ if (rhs & (1L << dest))
+ temp = dest; /* mult takes this many/2 I cycles */
+ ARMul_Icycles (state, ARMul_MultTable[temp], 0L);
+ }
+ else
+ { /* AND reg */
+ rhs = DPRegRHS;
+ dest = LHS & rhs;
+ WRITEDEST (dest);
+ }
+ break;
+
+ case 0x01: /* ANDS reg and MULS */
#ifdef MODET
- if ((BITS(4,11) & 0xF9) == 0x9) {
- /* LDR register offset, no write-back, down, post indexed */
- LHPOSTDOWN() ;
- /* fall through to rest of decoding */
- }
-#endif
- if (BITS(4,7) == 9) { /* MULS */
- rhs = state->Reg[MULRHSReg] ;
- if (MULLHSReg == MULDESTReg) {
- UNDEF_MULDestEQOp1 ;
- state->Reg[MULDESTReg] = 0 ;
- CLEARN ;
- SETZ ;
- }
- else if (MULDESTReg != 15) {
- dest = state->Reg[MULLHSReg] * rhs ;
- ARMul_NegZero(state,dest) ;
- state->Reg[MULDESTReg] = dest ;
- }
- else {
- UNDEF_MULPCDest ;
- }
- for (dest = 0, temp = 0 ; dest < 32 ; dest++)
- if (rhs & (1L << dest))
- temp = dest ; /* mult takes this many/2 I cycles */
- ARMul_Icycles(state,ARMul_MultTable[temp],0L) ;
- }
- else { /* ANDS reg */
- rhs = DPSRegRHS ;
- dest = LHS & rhs ;
- WRITESDEST(dest) ;
- }
- break ;
-
- case 0x02 : /* EOR reg and MLA */
+ if ((BITS (4, 11) & 0xF9) == 0x9)
+ {
+ /* LDR register offset, no write-back, down, post indexed */
+ LHPOSTDOWN ();
+ /* fall through to rest of decoding */
+ }
+#endif
+ if (BITS (4, 7) == 9)
+ { /* MULS */
+ rhs = state->Reg[MULRHSReg];
+ if (MULLHSReg == MULDESTReg)
+ {
+ UNDEF_MULDestEQOp1;
+ state->Reg[MULDESTReg] = 0;
+ CLEARN;
+ SETZ;
+ }
+ else if (MULDESTReg != 15)
+ {
+ dest = state->Reg[MULLHSReg] * rhs;
+ ARMul_NegZero (state, dest);
+ state->Reg[MULDESTReg] = dest;
+ }
+ else
+ {
+ UNDEF_MULPCDest;
+ }
+ for (dest = 0, temp = 0; dest < 32; dest++)
+ if (rhs & (1L << dest))
+ temp = dest; /* mult takes this many/2 I cycles */
+ ARMul_Icycles (state, ARMul_MultTable[temp], 0L);
+ }
+ else
+ { /* ANDS reg */
+ rhs = DPSRegRHS;
+ dest = LHS & rhs;
+ WRITESDEST (dest);
+ }
+ break;
+
+ case 0x02: /* EOR reg and MLA */
#ifdef MODET
- if (BITS(4,11) == 0xB) {
- /* STRH register offset, write-back, down, post indexed */
- SHDOWNWB() ;
- break ;
- }
-#endif
- if (BITS(4,7) == 9) { /* MLA */
- rhs = state->Reg[MULRHSReg] ;
- if (MULLHSReg == MULDESTReg) {
- UNDEF_MULDestEQOp1 ;
- state->Reg[MULDESTReg] = state->Reg[MULACCReg] ;
- }
- else if (MULDESTReg != 15)
- state->Reg[MULDESTReg] = state->Reg[MULLHSReg] * rhs + state->Reg[MULACCReg] ;
- else {
- UNDEF_MULPCDest ;
- }
- for (dest = 0, temp = 0 ; dest < 32 ; dest++)
- if (rhs & (1L << dest))
- temp = dest ; /* mult takes this many/2 I cycles */
- ARMul_Icycles(state,ARMul_MultTable[temp],0L) ;
- }
- else {
- rhs = DPRegRHS ;
- dest = LHS ^ rhs ;
- WRITEDEST(dest) ;
- }
- break ;
-
- case 0x03 : /* EORS reg and MLAS */
+ if (BITS (4, 11) == 0xB)
+ {
+ /* STRH register offset, write-back, down, post indexed */
+ SHDOWNWB ();
+ break;
+ }
+#endif
+ if (BITS (4, 7) == 9)
+ { /* MLA */
+ rhs = state->Reg[MULRHSReg];
+ if (MULLHSReg == MULDESTReg)
+ {
+ UNDEF_MULDestEQOp1;
+ state->Reg[MULDESTReg] = state->Reg[MULACCReg];
+ }
+ else if (MULDESTReg != 15)
+ state->Reg[MULDESTReg] =
+ state->Reg[MULLHSReg] * rhs + state->Reg[MULACCReg];
+ else
+ {
+ UNDEF_MULPCDest;
+ }
+ for (dest = 0, temp = 0; dest < 32; dest++)
+ if (rhs & (1L << dest))
+ temp = dest; /* mult takes this many/2 I cycles */
+ ARMul_Icycles (state, ARMul_MultTable[temp], 0L);
+ }
+ else
+ {
+ rhs = DPRegRHS;
+ dest = LHS ^ rhs;
+ WRITEDEST (dest);
+ }
+ break;
+
+ case 0x03: /* EORS reg and MLAS */
#ifdef MODET
- if ((BITS(4,11) & 0xF9) == 0x9) {
- /* LDR register offset, write-back, down, post-indexed */
- LHPOSTDOWN() ;
- /* fall through to rest of the decoding */
- }
-#endif
- if (BITS(4,7) == 9) { /* MLAS */
- rhs = state->Reg[MULRHSReg] ;
- if (MULLHSReg == MULDESTReg) {
- UNDEF_MULDestEQOp1 ;
- dest = state->Reg[MULACCReg] ;
- ARMul_NegZero(state,dest) ;
- state->Reg[MULDESTReg] = dest ;
- }
- else if (MULDESTReg != 15) {
- dest = state->Reg[MULLHSReg] * rhs + state->Reg[MULACCReg] ;
- ARMul_NegZero(state,dest) ;
- state->Reg[MULDESTReg] = dest ;
- }
- else {
- UNDEF_MULPCDest ;
- }
- for (dest = 0, temp = 0 ; dest < 32 ; dest++)
- if (rhs & (1L << dest))
- temp = dest ; /* mult takes this many/2 I cycles */
- ARMul_Icycles(state,ARMul_MultTable[temp],0L) ;
- }
- else { /* EORS Reg */
- rhs = DPSRegRHS ;
- dest = LHS ^ rhs ;
- WRITESDEST(dest) ;
- }
- break ;
-
- case 0x04 : /* SUB reg */
+ if ((BITS (4, 11) & 0xF9) == 0x9)
+ {
+ /* LDR register offset, write-back, down, post-indexed */
+ LHPOSTDOWN ();
+ /* fall through to rest of the decoding */
+ }
+#endif
+ if (BITS (4, 7) == 9)
+ { /* MLAS */
+ rhs = state->Reg[MULRHSReg];
+ if (MULLHSReg == MULDESTReg)
+ {
+ UNDEF_MULDestEQOp1;
+ dest = state->Reg[MULACCReg];
+ ARMul_NegZero (state, dest);
+ state->Reg[MULDESTReg] = dest;
+ }
+ else if (MULDESTReg != 15)
+ {
+ dest =
+ state->Reg[MULLHSReg] * rhs + state->Reg[MULACCReg];
+ ARMul_NegZero (state, dest);
+ state->Reg[MULDESTReg] = dest;
+ }
+ else
+ {
+ UNDEF_MULPCDest;
+ }
+ for (dest = 0, temp = 0; dest < 32; dest++)
+ if (rhs & (1L << dest))
+ temp = dest; /* mult takes this many/2 I cycles */
+ ARMul_Icycles (state, ARMul_MultTable[temp], 0L);
+ }
+ else
+ { /* EORS Reg */
+ rhs = DPSRegRHS;
+ dest = LHS ^ rhs;
+ WRITESDEST (dest);
+ }
+ break;
+
+ case 0x04: /* SUB reg */
#ifdef MODET
- if (BITS(4,7) == 0xB) {
- /* STRH immediate offset, no write-back, down, post indexed */
- SHDOWNWB() ;
- break ;
- }
-#endif
- rhs = DPRegRHS;
- dest = LHS - rhs ;
- WRITEDEST(dest) ;
- break ;
-
- case 0x05 : /* SUBS reg */
+ if (BITS (4, 7) == 0xB)
+ {
+ /* STRH immediate offset, no write-back, down, post indexed */
+ SHDOWNWB ();
+ break;
+ }
+#endif
+ rhs = DPRegRHS;
+ dest = LHS - rhs;
+ WRITEDEST (dest);
+ break;
+
+ case 0x05: /* SUBS reg */
#ifdef MODET
- if ((BITS(4,7) & 0x9) == 0x9) {
- /* LDR immediate offset, no write-back, down, post indexed */
- LHPOSTDOWN() ;
- /* fall through to the rest of the instruction decoding */
- }
-#endif
- lhs = LHS ;
- rhs = DPRegRHS ;
- dest = lhs - rhs ;
- if ((lhs >= rhs) || ((rhs | lhs) >> 31)) {
- ARMul_SubCarry(state,lhs,rhs,dest) ;
- ARMul_SubOverflow(state,lhs,rhs,dest) ;
- }
- else {
- CLEARC ;
- CLEARV ;
- }
- WRITESDEST(dest) ;
- break ;
-
- case 0x06 : /* RSB reg */
+ if ((BITS (4, 7) & 0x9) == 0x9)
+ {
+ /* LDR immediate offset, no write-back, down, post indexed */
+ LHPOSTDOWN ();
+ /* fall through to the rest of the instruction decoding */
+ }
+#endif
+ lhs = LHS;
+ rhs = DPRegRHS;
+ dest = lhs - rhs;
+ if ((lhs >= rhs) || ((rhs | lhs) >> 31))
+ {
+ ARMul_SubCarry (state, lhs, rhs, dest);
+ ARMul_SubOverflow (state, lhs, rhs, dest);
+ }
+ else
+ {
+ CLEARC;
+ CLEARV;
+ }
+ WRITESDEST (dest);
+ break;
+
+ case 0x06: /* RSB reg */
#ifdef MODET
- if (BITS(4,7) == 0xB) {
- /* STRH immediate offset, write-back, down, post indexed */
- SHDOWNWB() ;
- break ;
- }
-#endif
- rhs = DPRegRHS ;
- dest = rhs - LHS ;
- WRITEDEST(dest) ;
- break ;
-
- case 0x07 : /* RSBS reg */
+ if (BITS (4, 7) == 0xB)
+ {
+ /* STRH immediate offset, write-back, down, post indexed */
+ SHDOWNWB ();
+ break;
+ }
+#endif
+ rhs = DPRegRHS;
+ dest = rhs - LHS;
+ WRITEDEST (dest);
+ break;
+
+ case 0x07: /* RSBS reg */
#ifdef MODET
- if ((BITS(4,7) & 0x9) == 0x9) {
- /* LDR immediate offset, write-back, down, post indexed */
- LHPOSTDOWN() ;
- /* fall through to remainder of instruction decoding */
- }
-#endif
- lhs = LHS ;
- rhs = DPRegRHS ;
- dest = rhs - lhs ;
- if ((rhs >= lhs) || ((rhs | lhs) >> 31)) {
- ARMul_SubCarry(state,rhs,lhs,dest) ;
- ARMul_SubOverflow(state,rhs,lhs,dest) ;
- }
- else {
- CLEARC ;
- CLEARV ;
- }
- WRITESDEST(dest) ;
- break ;
-
- case 0x08 : /* ADD reg */
+ if ((BITS (4, 7) & 0x9) == 0x9)
+ {
+ /* LDR immediate offset, write-back, down, post indexed */
+ LHPOSTDOWN ();
+ /* fall through to remainder of instruction decoding */
+ }
+#endif
+ lhs = LHS;
+ rhs = DPRegRHS;
+ dest = rhs - lhs;
+ if ((rhs >= lhs) || ((rhs | lhs) >> 31))
+ {
+ ARMul_SubCarry (state, rhs, lhs, dest);
+ ARMul_SubOverflow (state, rhs, lhs, dest);
+ }
+ else
+ {
+ CLEARC;
+ CLEARV;
+ }
+ WRITESDEST (dest);
+ break;
+
+ case 0x08: /* ADD reg */
#ifdef MODET
- if (BITS(4,11) == 0xB) {
- /* STRH register offset, no write-back, up, post indexed */
- SHUPWB() ;
- break ;
- }
+ if (BITS (4, 11) == 0xB)
+ {
+ /* STRH register offset, no write-back, up, post indexed */
+ SHUPWB ();
+ break;
+ }
#endif
#ifdef MODET
- if (BITS(4,7) == 0x9) { /* MULL */
- /* 32x32 = 64 */
- ARMul_Icycles(state,Multiply64(state,instr,LUNSIGNED,LDEFAULT),0L) ;
- break ;
- }
-#endif
- rhs = DPRegRHS ;
- dest = LHS + rhs ;
- WRITEDEST(dest) ;
- break ;
-
- case 0x09 : /* ADDS reg */
+ if (BITS (4, 7) == 0x9)
+ { /* MULL */
+ /* 32x32 = 64 */
+ ARMul_Icycles (state,
+ Multiply64 (state, instr, LUNSIGNED,
+ LDEFAULT), 0L);
+ break;
+ }
+#endif
+ rhs = DPRegRHS;
+ dest = LHS + rhs;
+ WRITEDEST (dest);
+ break;
+
+ case 0x09: /* ADDS reg */
#ifdef MODET
- if ((BITS(4,11) & 0xF9) == 0x9) {
- /* LDR register offset, no write-back, up, post indexed */
- LHPOSTUP() ;
- /* fall through to remaining instruction decoding */
- }
+ if ((BITS (4, 11) & 0xF9) == 0x9)
+ {
+ /* LDR register offset, no write-back, up, post indexed */
+ LHPOSTUP ();
+ /* fall through to remaining instruction decoding */
+ }
#endif
#ifdef MODET
- if (BITS(4,7) == 0x9) { /* MULL */
- /* 32x32=64 */
- ARMul_Icycles(state,Multiply64(state,instr,LUNSIGNED,LSCC),0L) ;
- break ;
- }
-#endif
- lhs = LHS ;
- rhs = DPRegRHS ;
- dest = lhs + rhs ;
- ASSIGNZ(dest==0) ;
- if ((lhs | rhs) >> 30) { /* possible C,V,N to set */
- ASSIGNN(NEG(dest)) ;
- ARMul_AddCarry(state,lhs,rhs,dest) ;
- ARMul_AddOverflow(state,lhs,rhs,dest) ;
- }
- else {
- CLEARN ;
- CLEARC ;
- CLEARV ;
- }
- WRITESDEST(dest) ;
- break ;
-
- case 0x0a : /* ADC reg */
+ if (BITS (4, 7) == 0x9)
+ { /* MULL */
+ /* 32x32=64 */
+ ARMul_Icycles (state,
+ Multiply64 (state, instr, LUNSIGNED, LSCC),
+ 0L);
+ break;
+ }
+#endif
+ lhs = LHS;
+ rhs = DPRegRHS;
+ dest = lhs + rhs;
+ ASSIGNZ (dest == 0);
+ if ((lhs | rhs) >> 30)
+ { /* possible C,V,N to set */
+ ASSIGNN (NEG (dest));
+ ARMul_AddCarry (state, lhs, rhs, dest);
+ ARMul_AddOverflow (state, lhs, rhs, dest);
+ }
+ else
+ {
+ CLEARN;
+ CLEARC;
+ CLEARV;
+ }
+ WRITESDEST (dest);
+ break;
+
+ case 0x0a: /* ADC reg */
#ifdef MODET
- if (BITS(4,11) == 0xB) {
- /* STRH register offset, write-back, up, post-indexed */
- SHUPWB() ;
- break ;
- }
+ if (BITS (4, 11) == 0xB)
+ {
+ /* STRH register offset, write-back, up, post-indexed */
+ SHUPWB ();
+ break;
+ }
#endif
#ifdef MODET
- if (BITS(4,7) == 0x9) { /* MULL */
- /* 32x32=64 */
- ARMul_Icycles(state,MultiplyAdd64(state,instr,LUNSIGNED,LDEFAULT),0L) ;
- break ;
- }
-#endif
- rhs = DPRegRHS ;
- dest = LHS + rhs + CFLAG ;
- WRITEDEST(dest) ;
- break ;
-
- case 0x0b : /* ADCS reg */
+ if (BITS (4, 7) == 0x9)
+ { /* MULL */
+ /* 32x32=64 */
+ ARMul_Icycles (state,
+ MultiplyAdd64 (state, instr, LUNSIGNED,
+ LDEFAULT), 0L);
+ break;
+ }
+#endif
+ rhs = DPRegRHS;
+ dest = LHS + rhs + CFLAG;
+ WRITEDEST (dest);
+ break;
+
+ case 0x0b: /* ADCS reg */
#ifdef MODET
- if ((BITS(4,11) & 0xF9) == 0x9) {
- /* LDR register offset, write-back, up, post indexed */
- LHPOSTUP() ;
- /* fall through to remaining instruction decoding */
- }
+ if ((BITS (4, 11) & 0xF9) == 0x9)
+ {
+ /* LDR register offset, write-back, up, post indexed */
+ LHPOSTUP ();
+ /* fall through to remaining instruction decoding */
+ }
#endif
#ifdef MODET
- if (BITS(4,7) == 0x9) { /* MULL */
- /* 32x32=64 */
- ARMul_Icycles(state,MultiplyAdd64(state,instr,LUNSIGNED,LSCC),0L) ;
- break ;
- }
-#endif
- lhs = LHS ;
- rhs = DPRegRHS ;
- dest = lhs + rhs + CFLAG ;
- ASSIGNZ(dest==0) ;
- if ((lhs | rhs) >> 30) { /* possible C,V,N to set */
- ASSIGNN(NEG(dest)) ;
- ARMul_AddCarry(state,lhs,rhs,dest) ;
- ARMul_AddOverflow(state,lhs,rhs,dest) ;
- }
- else {
- CLEARN ;
- CLEARC ;
- CLEARV ;
- }
- WRITESDEST(dest) ;
- break ;
-
- case 0x0c : /* SBC reg */
+ if (BITS (4, 7) == 0x9)
+ { /* MULL */
+ /* 32x32=64 */
+ ARMul_Icycles (state,
+ MultiplyAdd64 (state, instr, LUNSIGNED,
+ LSCC), 0L);
+ break;
+ }
+#endif
+ lhs = LHS;
+ rhs = DPRegRHS;
+ dest = lhs + rhs + CFLAG;
+ ASSIGNZ (dest == 0);
+ if ((lhs | rhs) >> 30)
+ { /* possible C,V,N to set */
+ ASSIGNN (NEG (dest));
+ ARMul_AddCarry (state, lhs, rhs, dest);
+ ARMul_AddOverflow (state, lhs, rhs, dest);
+ }
+ else
+ {
+ CLEARN;
+ CLEARC;
+ CLEARV;
+ }
+ WRITESDEST (dest);
+ break;
+
+ case 0x0c: /* SBC reg */
#ifdef MODET
- if (BITS(4,7) == 0xB) {
- /* STRH immediate offset, no write-back, up post indexed */
- SHUPWB() ;
- break ;
- }
+ if (BITS (4, 7) == 0xB)
+ {
+ /* STRH immediate offset, no write-back, up post indexed */
+ SHUPWB ();
+ break;
+ }
#endif
#ifdef MODET
- if (BITS(4,7) == 0x9) { /* MULL */
- /* 32x32=64 */
- ARMul_Icycles(state,Multiply64(state,instr,LSIGNED,LDEFAULT),0L) ;
- break ;
- }
-#endif
- rhs = DPRegRHS ;
- dest = LHS - rhs - !CFLAG ;
- WRITEDEST(dest) ;
- break ;
-
- case 0x0d : /* SBCS reg */
+ if (BITS (4, 7) == 0x9)
+ { /* MULL */
+ /* 32x32=64 */
+ ARMul_Icycles (state,
+ Multiply64 (state, instr, LSIGNED, LDEFAULT),
+ 0L);
+ break;
+ }
+#endif
+ rhs = DPRegRHS;
+ dest = LHS - rhs - !CFLAG;
+ WRITEDEST (dest);
+ break;
+
+ case 0x0d: /* SBCS reg */
#ifdef MODET
- if ((BITS(4,7) & 0x9) == 0x9) {
- /* LDR immediate offset, no write-back, up, post indexed */
- LHPOSTUP() ;
- }
+ if ((BITS (4, 7) & 0x9) == 0x9)
+ {
+ /* LDR immediate offset, no write-back, up, post indexed */
+ LHPOSTUP ();
+ }
#endif
#ifdef MODET
- if (BITS(4,7) == 0x9) { /* MULL */
- /* 32x32=64 */
- ARMul_Icycles(state,Multiply64(state,instr,LSIGNED,LSCC),0L) ;
- break ;
- }
-#endif
- lhs = LHS ;
- rhs = DPRegRHS ;
- dest = lhs - rhs - !CFLAG ;
- if ((lhs >= rhs) || ((rhs | lhs) >> 31)) {
- ARMul_SubCarry(state,lhs,rhs,dest) ;
- ARMul_SubOverflow(state,lhs,rhs,dest) ;
- }
- else {
- CLEARC ;
- CLEARV ;
- }
- WRITESDEST(dest) ;
- break ;
-
- case 0x0e : /* RSC reg */
+ if (BITS (4, 7) == 0x9)
+ { /* MULL */
+ /* 32x32=64 */
+ ARMul_Icycles (state,
+ Multiply64 (state, instr, LSIGNED, LSCC),
+ 0L);
+ break;
+ }
+#endif
+ lhs = LHS;
+ rhs = DPRegRHS;
+ dest = lhs - rhs - !CFLAG;
+ if ((lhs >= rhs) || ((rhs | lhs) >> 31))
+ {
+ ARMul_SubCarry (state, lhs, rhs, dest);
+ ARMul_SubOverflow (state, lhs, rhs, dest);
+ }
+ else
+ {
+ CLEARC;
+ CLEARV;
+ }
+ WRITESDEST (dest);
+ break;
+
+ case 0x0e: /* RSC reg */
#ifdef MODET
- if (BITS(4,7) == 0xB) {
- /* STRH immediate offset, write-back, up, post indexed */
- SHUPWB() ;
- break ;
- }
+ if (BITS (4, 7) == 0xB)
+ {
+ /* STRH immediate offset, write-back, up, post indexed */
+ SHUPWB ();
+ break;
+ }
#endif
#ifdef MODET
- if (BITS(4,7) == 0x9) { /* MULL */
- /* 32x32=64 */
- ARMul_Icycles(state,MultiplyAdd64(state,instr,LSIGNED,LDEFAULT),0L) ;
- break ;
- }
-#endif
- rhs = DPRegRHS ;
- dest = rhs - LHS - !CFLAG ;
- WRITEDEST(dest) ;
- break ;
-
- case 0x0f : /* RSCS reg */
+ if (BITS (4, 7) == 0x9)
+ { /* MULL */
+ /* 32x32=64 */
+ ARMul_Icycles (state,
+ MultiplyAdd64 (state, instr, LSIGNED,
+ LDEFAULT), 0L);
+ break;
+ }
+#endif
+ rhs = DPRegRHS;
+ dest = rhs - LHS - !CFLAG;
+ WRITEDEST (dest);
+ break;
+
+ case 0x0f: /* RSCS reg */
#ifdef MODET
- if ((BITS(4,7) & 0x9) == 0x9) {
- /* LDR immediate offset, write-back, up, post indexed */
- LHPOSTUP() ;
- /* fall through to remaining instruction decoding */
- }
+ if ((BITS (4, 7) & 0x9) == 0x9)
+ {
+ /* LDR immediate offset, write-back, up, post indexed */
+ LHPOSTUP ();
+ /* fall through to remaining instruction decoding */
+ }
#endif
#ifdef MODET
- if (BITS(4,7) == 0x9) { /* MULL */
- /* 32x32=64 */
- ARMul_Icycles(state,MultiplyAdd64(state,instr,LSIGNED,LSCC),0L) ;
- break ;
- }
-#endif
- lhs = LHS ;
- rhs = DPRegRHS ;
- dest = rhs - lhs - !CFLAG ;
- if ((rhs >= lhs) || ((rhs | lhs) >> 31)) {
- ARMul_SubCarry(state,rhs,lhs,dest) ;
- ARMul_SubOverflow(state,rhs,lhs,dest) ;
- }
- else {
- CLEARC ;
- CLEARV ;
- }
- WRITESDEST(dest) ;
- break ;
-
- case 0x10 : /* TST reg and MRS CPSR and SWP word */
+ if (BITS (4, 7) == 0x9)
+ { /* MULL */
+ /* 32x32=64 */
+ ARMul_Icycles (state,
+ MultiplyAdd64 (state, instr, LSIGNED, LSCC),
+ 0L);
+ break;
+ }
+#endif
+ lhs = LHS;
+ rhs = DPRegRHS;
+ dest = rhs - lhs - !CFLAG;
+ if ((rhs >= lhs) || ((rhs | lhs) >> 31))
+ {
+ ARMul_SubCarry (state, rhs, lhs, dest);
+ ARMul_SubOverflow (state, rhs, lhs, dest);
+ }
+ else
+ {
+ CLEARC;
+ CLEARV;
+ }
+ WRITESDEST (dest);
+ break;
+
+ case 0x10: /* TST reg and MRS CPSR and SWP word */
#ifdef MODET
- if (BITS(4,11) == 0xB) {
- /* STRH register offset, no write-back, down, pre indexed */
- SHPREDOWN() ;
- break ;
- }
-#endif
- if (BITS(4,11) == 9) { /* SWP */
- UNDEF_SWPPC ;
- temp = LHS ;
- BUSUSEDINCPCS ;
+ if (BITS (4, 11) == 0xB)
+ {
+ /* STRH register offset, no write-back, down, pre indexed */
+ SHPREDOWN ();
+ break;
+ }
+#endif
+ if (BITS (4, 11) == 9)
+ { /* SWP */
+ UNDEF_SWPPC;
+ temp = LHS;
+ BUSUSEDINCPCS;
#ifndef MODE32
- if (VECTORACCESS(temp) || ADDREXCEPT(temp)) {
- INTERNALABORT(temp) ;
- (void)ARMul_LoadWordN(state,temp) ;
- (void)ARMul_LoadWordN(state,temp) ;
- }
- else
-#endif
- dest = ARMul_SwapWord(state,temp,state->Reg[RHSReg]) ;
- if (temp & 3)
- DEST = ARMul_Align(state,temp,dest) ;
- else
- DEST = dest ;
- if (state->abortSig || state->Aborted) {
- TAKEABORT ;
- }
- }
- else if ((BITS(0,11)==0) && (LHSReg==15)) { /* MRS CPSR */
- UNDEF_MRSPC ;
- DEST = ECC | EINT | EMODE ;
- }
- else {
- UNDEF_Test ;
- }
- break ;
-
- case 0x11 : /* TSTP reg */
+ if (VECTORACCESS (temp) || ADDREXCEPT (temp))
+ {
+ INTERNALABORT (temp);
+ (void) ARMul_LoadWordN (state, temp);
+ (void) ARMul_LoadWordN (state, temp);
+ }
+ else
+#endif
+ dest = ARMul_SwapWord (state, temp, state->Reg[RHSReg]);
+ if (temp & 3)
+ DEST = ARMul_Align (state, temp, dest);
+ else
+ DEST = dest;
+ if (state->abortSig || state->Aborted)
+ {
+ TAKEABORT;
+ }
+ }
+ else if ((BITS (0, 11) == 0) && (LHSReg == 15))
+ { /* MRS CPSR */
+ UNDEF_MRSPC;
+ DEST = ECC | EINT | EMODE;
+ }
+ else
+ {
+ UNDEF_Test;
+ }
+ break;
+
+ case 0x11: /* TSTP reg */
#ifdef MODET
- if ((BITS(4,11) & 0xF9) == 0x9) {
- /* LDR register offset, no write-back, down, pre indexed */
- LHPREDOWN() ;
- /* continue with remaining instruction decode */
- }
-#endif
- if (DESTReg == 15) { /* TSTP reg */
+ if ((BITS (4, 11) & 0xF9) == 0x9)
+ {
+ /* LDR register offset, no write-back, down, pre indexed */
+ LHPREDOWN ();
+ /* continue with remaining instruction decode */
+ }
+#endif
+ if (DESTReg == 15)
+ { /* TSTP reg */
#ifdef MODE32
- state->Cpsr = GETSPSR(state->Bank) ;
- ARMul_CPSRAltered(state) ;
+ state->Cpsr = GETSPSR (state->Bank);
+ ARMul_CPSRAltered (state);
#else
- rhs = DPRegRHS ;
- temp = LHS & rhs ;
- SETR15PSR(temp) ;
-#endif
- }
- else { /* TST reg */
- rhs = DPSRegRHS ;
- dest = LHS & rhs ;
- ARMul_NegZero(state,dest) ;
- }
- break ;
-
- case 0x12 : /* TEQ reg and MSR reg to CPSR (ARM6) */
+ rhs = DPRegRHS;
+ temp = LHS & rhs;
+ SETR15PSR (temp);
+#endif
+ }
+ else
+ { /* TST reg */
+ rhs = DPSRegRHS;
+ dest = LHS & rhs;
+ ARMul_NegZero (state, dest);
+ }
+ break;
+
+ case 0x12: /* TEQ reg and MSR reg to CPSR (ARM6) */
#ifdef MODET
- if (BITS(4,11) == 0xB) {
- /* STRH register offset, write-back, down, pre indexed */
- SHPREDOWNWB() ;
- break ;
- }
+ if (BITS (4, 11) == 0xB)
+ {
+ /* STRH register offset, write-back, down, pre indexed */
+ SHPREDOWNWB ();
+ break;
+ }
#endif
#ifdef MODET
- if (BITS(4,27)==0x12FFF1) { /* BX */
- /* Branch to the address in RHSReg. If bit0 of
- destination address is 1 then switch to Thumb mode: */
- ARMword addr = state->Reg[RHSReg];
-
- /* If we read the PC then the bottom bit is clear */
- if (RHSReg == 15) addr &= ~1;
-
- /* Enable this for a helpful bit of debugging when
- GDB is not yet fully working...
- fprintf (stderr, "BX at %x to %x (go %s)\n",
- state->Reg[15], addr, (addr & 1) ? "thumb": "arm" ); */
-
- if (addr & (1 << 0)) { /* Thumb bit */
- SETT;
- state->Reg[15] = addr & 0xfffffffe;
- /* NOTE: The other CPSR flag setting blocks do not
- seem to update the state->Cpsr state, but just do
- the explicit flag. The copy from the seperate
- flags to the register must happen later. */
- FLUSHPIPE;
- } else {
- CLEART;
- state->Reg[15] = addr & 0xfffffffc;
- FLUSHPIPE;
- }
- }
-#endif
- if (DESTReg==15 && BITS(17,18)==0) { /* MSR reg to CPSR */
- UNDEF_MSRPC ;
- temp = DPRegRHS ;
- ARMul_FixCPSR(state,instr,temp) ;
- }
- else {
- UNDEF_Test ;
- }
- break ;
-
- case 0x13 : /* TEQP reg */
+ if (BITS (4, 27) == 0x12FFF1)
+ { /* BX */
+ /* Branch to the address in RHSReg. If bit0 of
+ destination address is 1 then switch to Thumb mode: */
+ ARMword addr = state->Reg[RHSReg];
+
+ /* If we read the PC then the bottom bit is clear */
+ if (RHSReg == 15)
+ addr &= ~1;
+
+ /* Enable this for a helpful bit of debugging when
+ GDB is not yet fully working...
+ fprintf (stderr, "BX at %x to %x (go %s)\n",
+ state->Reg[15], addr, (addr & 1) ? "thumb": "arm" ); */
+
+ if (addr & (1 << 0))
+ { /* Thumb bit */
+ SETT;
+ state->Reg[15] = addr & 0xfffffffe;
+ /* NOTE: The other CPSR flag setting blocks do not
+ seem to update the state->Cpsr state, but just do
+ the explicit flag. The copy from the seperate
+ flags to the register must happen later. */
+ FLUSHPIPE;
+ }
+ else
+ {
+ CLEART;
+ state->Reg[15] = addr & 0xfffffffc;
+ FLUSHPIPE;
+ }
+ }
+#endif
+ if (DESTReg == 15 && BITS (17, 18) == 0)
+ { /* MSR reg to CPSR */
+ UNDEF_MSRPC;
+ temp = DPRegRHS;
+ ARMul_FixCPSR (state, instr, temp);
+ }
+ else
+ {
+ UNDEF_Test;
+ }
+ break;
+
+ case 0x13: /* TEQP reg */
#ifdef MODET
- if ((BITS(4,11) & 0xF9) == 0x9) {
- /* LDR register offset, write-back, down, pre indexed */
- LHPREDOWNWB() ;
- /* continue with remaining instruction decode */
- }
-#endif
- if (DESTReg == 15) { /* TEQP reg */
+ if ((BITS (4, 11) & 0xF9) == 0x9)
+ {
+ /* LDR register offset, write-back, down, pre indexed */
+ LHPREDOWNWB ();
+ /* continue with remaining instruction decode */
+ }
+#endif
+ if (DESTReg == 15)
+ { /* TEQP reg */
#ifdef MODE32
- state->Cpsr = GETSPSR(state->Bank) ;
- ARMul_CPSRAltered(state) ;
+ state->Cpsr = GETSPSR (state->Bank);
+ ARMul_CPSRAltered (state);
#else
- rhs = DPRegRHS ;
- temp = LHS ^ rhs ;
- SETR15PSR(temp) ;
-#endif
- }
- else { /* TEQ Reg */
- rhs = DPSRegRHS ;
- dest = LHS ^ rhs ;
- ARMul_NegZero(state,dest) ;
- }
- break ;
-
- case 0x14 : /* CMP reg and MRS SPSR and SWP byte */
+ rhs = DPRegRHS;
+ temp = LHS ^ rhs;
+ SETR15PSR (temp);
+#endif
+ }
+ else
+ { /* TEQ Reg */
+ rhs = DPSRegRHS;
+ dest = LHS ^ rhs;
+ ARMul_NegZero (state, dest);
+ }
+ break;
+
+ case 0x14: /* CMP reg and MRS SPSR and SWP byte */
#ifdef MODET
- if (BITS(4,7) == 0xB) {
- /* STRH immediate offset, no write-back, down, pre indexed */
- SHPREDOWN() ;
- break ;
- }
-#endif
- if (BITS(4,11) == 9) { /* SWP */
- UNDEF_SWPPC ;
- temp = LHS ;
- BUSUSEDINCPCS ;
+ if (BITS (4, 7) == 0xB)
+ {
+ /* STRH immediate offset, no write-back, down, pre indexed */
+ SHPREDOWN ();
+ break;
+ }
+#endif
+ if (BITS (4, 11) == 9)
+ { /* SWP */
+ UNDEF_SWPPC;
+ temp = LHS;
+ BUSUSEDINCPCS;
#ifndef MODE32
- if (VECTORACCESS(temp) || ADDREXCEPT(temp)) {
- INTERNALABORT(temp) ;
- (void)ARMul_LoadByte(state,temp) ;
- (void)ARMul_LoadByte(state,temp) ;
- }
- else
-#endif
- DEST = ARMul_SwapByte(state,temp,state->Reg[RHSReg]) ;
- if (state->abortSig || state->Aborted) {
- TAKEABORT ;
- }
- }
- else if ((BITS(0,11)==0) && (LHSReg==15)) { /* MRS SPSR */
- UNDEF_MRSPC ;
- DEST = GETSPSR(state->Bank) ;
- }
- else {
- UNDEF_Test ;
- }
- break ;
-
- case 0x15 : /* CMPP reg */
+ if (VECTORACCESS (temp) || ADDREXCEPT (temp))
+ {
+ INTERNALABORT (temp);
+ (void) ARMul_LoadByte (state, temp);
+ (void) ARMul_LoadByte (state, temp);
+ }
+ else
+#endif
+ DEST = ARMul_SwapByte (state, temp, state->Reg[RHSReg]);
+ if (state->abortSig || state->Aborted)
+ {
+ TAKEABORT;
+ }
+ }
+ else if ((BITS (0, 11) == 0) && (LHSReg == 15))
+ { /* MRS SPSR */
+ UNDEF_MRSPC;
+ DEST = GETSPSR (state->Bank);
+ }
+ else
+ {
+ UNDEF_Test;
+ }
+ break;
+
+ case 0x15: /* CMPP reg */
#ifdef MODET
- if ((BITS(4,7) & 0x9) == 0x9) {
- /* LDR immediate offset, no write-back, down, pre indexed */
- LHPREDOWN() ;
- /* continue with remaining instruction decode */
- }
-#endif
- if (DESTReg == 15) { /* CMPP reg */
+ if ((BITS (4, 7) & 0x9) == 0x9)
+ {
+ /* LDR immediate offset, no write-back, down, pre indexed */
+ LHPREDOWN ();
+ /* continue with remaining instruction decode */
+ }
+#endif
+ if (DESTReg == 15)
+ { /* CMPP reg */
#ifdef MODE32
- state->Cpsr = GETSPSR(state->Bank) ;
- ARMul_CPSRAltered(state) ;
+ state->Cpsr = GETSPSR (state->Bank);
+ ARMul_CPSRAltered (state);
#else
- rhs = DPRegRHS ;
- temp = LHS - rhs ;
- SETR15PSR(temp) ;
-#endif
- }
- else { /* CMP reg */
- lhs = LHS ;
- rhs = DPRegRHS ;
- dest = lhs - rhs ;
- ARMul_NegZero(state,dest) ;
- if ((lhs >= rhs) || ((rhs | lhs) >> 31)) {
- ARMul_SubCarry(state,lhs,rhs,dest) ;
- ARMul_SubOverflow(state,lhs,rhs,dest) ;
- }
- else {
- CLEARC ;
- CLEARV ;
- }
- }
- break ;
-
- case 0x16 : /* CMN reg and MSR reg to SPSR */
+ rhs = DPRegRHS;
+ temp = LHS - rhs;
+ SETR15PSR (temp);
+#endif
+ }
+ else
+ { /* CMP reg */
+ lhs = LHS;
+ rhs = DPRegRHS;
+ dest = lhs - rhs;
+ ARMul_NegZero (state, dest);
+ if ((lhs >= rhs) || ((rhs | lhs) >> 31))
+ {
+ ARMul_SubCarry (state, lhs, rhs, dest);
+ ARMul_SubOverflow (state, lhs, rhs, dest);
+ }
+ else
+ {
+ CLEARC;
+ CLEARV;
+ }
+ }
+ break;
+
+ case 0x16: /* CMN reg and MSR reg to SPSR */
#ifdef MODET
- if (BITS(4,7) == 0xB) {
- /* STRH immediate offset, write-back, down, pre indexed */
- SHPREDOWNWB() ;
- break ;
- }
-#endif
- if (DESTReg==15 && BITS(17,18)==0) { /* MSR */
- UNDEF_MSRPC ;
- ARMul_FixSPSR(state,instr,DPRegRHS);
- }
- else {
- UNDEF_Test ;
- }
- break ;
-
- case 0x17 : /* CMNP reg */
+ if (BITS (4, 7) == 0xB)
+ {
+ /* STRH immediate offset, write-back, down, pre indexed */
+ SHPREDOWNWB ();
+ break;
+ }
+#endif
+ if (DESTReg == 15 && BITS (17, 18) == 0)
+ { /* MSR */
+ UNDEF_MSRPC;
+ ARMul_FixSPSR (state, instr, DPRegRHS);
+ }
+ else
+ {
+ UNDEF_Test;
+ }
+ break;
+
+ case 0x17: /* CMNP reg */
#ifdef MODET
- if ((BITS(4,7) & 0x9) == 0x9) {
- /* LDR immediate offset, write-back, down, pre indexed */
- LHPREDOWNWB() ;
- /* continue with remaining instruction decoding */
- }
-#endif
- if (DESTReg == 15) {
+ if ((BITS (4, 7) & 0x9) == 0x9)
+ {
+ /* LDR immediate offset, write-back, down, pre indexed */
+ LHPREDOWNWB ();
+ /* continue with remaining instruction decoding */
+ }
+#endif
+ if (DESTReg == 15)
+ {
#ifdef MODE32
- state->Cpsr = GETSPSR(state->Bank) ;
- ARMul_CPSRAltered(state) ;
+ state->Cpsr = GETSPSR (state->Bank);
+ ARMul_CPSRAltered (state);
#else
- rhs = DPRegRHS ;
- temp = LHS + rhs ;
- SETR15PSR(temp) ;
-#endif
- break ;
- }
- else { /* CMN reg */
- lhs = LHS ;
- rhs = DPRegRHS ;
- dest = lhs + rhs ;
- ASSIGNZ(dest==0) ;
- if ((lhs | rhs) >> 30) { /* possible C,V,N to set */
- ASSIGNN(NEG(dest)) ;
- ARMul_AddCarry(state,lhs,rhs,dest) ;
- ARMul_AddOverflow(state,lhs,rhs,dest) ;
- }
- else {
- CLEARN ;
- CLEARC ;
- CLEARV ;
- }
- }
- break ;
-
- case 0x18 : /* ORR reg */
+ rhs = DPRegRHS;
+ temp = LHS + rhs;
+ SETR15PSR (temp);
+#endif
+ break;
+ }
+ else
+ { /* CMN reg */
+ lhs = LHS;
+ rhs = DPRegRHS;
+ dest = lhs + rhs;
+ ASSIGNZ (dest == 0);
+ if ((lhs | rhs) >> 30)
+ { /* possible C,V,N to set */
+ ASSIGNN (NEG (dest));
+ ARMul_AddCarry (state, lhs, rhs, dest);
+ ARMul_AddOverflow (state, lhs, rhs, dest);
+ }
+ else
+ {
+ CLEARN;
+ CLEARC;
+ CLEARV;
+ }
+ }
+ break;
+
+ case 0x18: /* ORR reg */
#ifdef MODET
- if (BITS(4,11) == 0xB) {
- /* STRH register offset, no write-back, up, pre indexed */
- SHPREUP() ;
- break ;
- }
-#endif
- rhs = DPRegRHS ;
- dest = LHS | rhs ;
- WRITEDEST(dest) ;
- break ;
-
- case 0x19 : /* ORRS reg */
+ if (BITS (4, 11) == 0xB)
+ {
+ /* STRH register offset, no write-back, up, pre indexed */
+ SHPREUP ();
+ break;
+ }
+#endif
+ rhs = DPRegRHS;
+ dest = LHS | rhs;
+ WRITEDEST (dest);
+ break;
+
+ case 0x19: /* ORRS reg */
#ifdef MODET
- if ((BITS(4,11) & 0xF9) == 0x9) {
- /* LDR register offset, no write-back, up, pre indexed */
- LHPREUP() ;
- /* continue with remaining instruction decoding */
- }
-#endif
- rhs = DPSRegRHS ;
- dest = LHS | rhs ;
- WRITESDEST(dest) ;
- break ;
-
- case 0x1a : /* MOV reg */
+ if ((BITS (4, 11) & 0xF9) == 0x9)
+ {
+ /* LDR register offset, no write-back, up, pre indexed */
+ LHPREUP ();
+ /* continue with remaining instruction decoding */
+ }
+#endif
+ rhs = DPSRegRHS;
+ dest = LHS | rhs;
+ WRITESDEST (dest);
+ break;
+
+ case 0x1a: /* MOV reg */
#ifdef MODET
- if (BITS(4,11) == 0xB) {
- /* STRH register offset, write-back, up, pre indexed */
- SHPREUPWB() ;
- break ;
- }
-#endif
- dest = DPRegRHS ;
- WRITEDEST(dest) ;
- break ;
-
- case 0x1b : /* MOVS reg */
+ if (BITS (4, 11) == 0xB)
+ {
+ /* STRH register offset, write-back, up, pre indexed */
+ SHPREUPWB ();
+ break;
+ }
+#endif
+ dest = DPRegRHS;
+ WRITEDEST (dest);
+ break;
+
+ case 0x1b: /* MOVS reg */
#ifdef MODET
- if ((BITS(4,11) & 0xF9) == 0x9) {
- /* LDR register offset, write-back, up, pre indexed */
- LHPREUPWB() ;
- /* continue with remaining instruction decoding */
- }
-#endif
- dest = DPSRegRHS ;
- WRITESDEST(dest) ;
- break ;
-
- case 0x1c : /* BIC reg */
+ if ((BITS (4, 11) & 0xF9) == 0x9)
+ {
+ /* LDR register offset, write-back, up, pre indexed */
+ LHPREUPWB ();
+ /* continue with remaining instruction decoding */
+ }
+#endif
+ dest = DPSRegRHS;
+ WRITESDEST (dest);
+ break;
+
+ case 0x1c: /* BIC reg */
#ifdef MODET
- if (BITS(4,7) == 0xB) {
- /* STRH immediate offset, no write-back, up, pre indexed */
- SHPREUP() ;
- break ;
- }
-#endif
- rhs = DPRegRHS ;
- dest = LHS & ~rhs ;
- WRITEDEST(dest) ;
- break ;
-
- case 0x1d : /* BICS reg */
+ if (BITS (4, 7) == 0xB)
+ {
+ /* STRH immediate offset, no write-back, up, pre indexed */
+ SHPREUP ();
+ break;
+ }
+#endif
+ rhs = DPRegRHS;
+ dest = LHS & ~rhs;
+ WRITEDEST (dest);
+ break;
+
+ case 0x1d: /* BICS reg */
#ifdef MODET
- if ((BITS(4,7) & 0x9) == 0x9) {
- /* LDR immediate offset, no write-back, up, pre indexed */
- LHPREUP() ;
- /* continue with instruction decoding */
- }
-#endif
- rhs = DPSRegRHS ;
- dest = LHS & ~rhs ;
- WRITESDEST(dest) ;
- break ;
-
- case 0x1e : /* MVN reg */
+ if ((BITS (4, 7) & 0x9) == 0x9)
+ {
+ /* LDR immediate offset, no write-back, up, pre indexed */
+ LHPREUP ();
+ /* continue with instruction decoding */
+ }
+#endif
+ rhs = DPSRegRHS;
+ dest = LHS & ~rhs;
+ WRITESDEST (dest);
+ break;
+
+ case 0x1e: /* MVN reg */
#ifdef MODET
- if (BITS(4,7) == 0xB) {
- /* STRH immediate offset, write-back, up, pre indexed */
- SHPREUPWB() ;
- break ;
- }
-#endif
- dest = ~DPRegRHS ;
- WRITEDEST(dest) ;
- break ;
-
- case 0x1f : /* MVNS reg */
+ if (BITS (4, 7) == 0xB)
+ {
+ /* STRH immediate offset, write-back, up, pre indexed */
+ SHPREUPWB ();
+ break;
+ }
+#endif
+ dest = ~DPRegRHS;
+ WRITEDEST (dest);
+ break;
+
+ case 0x1f: /* MVNS reg */
#ifdef MODET
- if ((BITS(4,7) & 0x9) == 0x9) {
- /* LDR immediate offset, write-back, up, pre indexed */
- LHPREUPWB() ;
- /* continue instruction decoding */
- }
+ if ((BITS (4, 7) & 0x9) == 0x9)
+ {
+ /* LDR immediate offset, write-back, up, pre indexed */
+ LHPREUPWB ();
+ /* continue instruction decoding */
+ }
#endif
- dest = ~DPSRegRHS ;
- WRITESDEST(dest) ;
- break ;
+ dest = ~DPSRegRHS;
+ WRITESDEST (dest);
+ break;
/***************************************************************************\
* Data Processing Immediate RHS Instructions *
\***************************************************************************/
- case 0x20 : /* AND immed */
- dest = LHS & DPImmRHS ;
- WRITEDEST(dest) ;
- break ;
-
- case 0x21 : /* ANDS immed */
- DPSImmRHS ;
- dest = LHS & rhs ;
- WRITESDEST(dest) ;
- break ;
-
- case 0x22 : /* EOR immed */
- dest = LHS ^ DPImmRHS ;
- WRITEDEST(dest) ;
- break ;
-
- case 0x23 : /* EORS immed */
- DPSImmRHS ;
- dest = LHS ^ rhs ;
- WRITESDEST(dest) ;
- break ;
-
- case 0x24 : /* SUB immed */
- dest = LHS - DPImmRHS ;
- WRITEDEST(dest) ;
- break ;
-
- case 0x25 : /* SUBS immed */
- lhs = LHS ;
- rhs = DPImmRHS ;
- dest = lhs - rhs ;
- if ((lhs >= rhs) || ((rhs | lhs) >> 31)) {
- ARMul_SubCarry(state,lhs,rhs,dest) ;
- ARMul_SubOverflow(state,lhs,rhs,dest) ;
- }
- else {
- CLEARC ;
- CLEARV ;
- }
- WRITESDEST(dest) ;
- break ;
-
- case 0x26 : /* RSB immed */
- dest = DPImmRHS - LHS ;
- WRITEDEST(dest) ;
- break ;
-
- case 0x27 : /* RSBS immed */
- lhs = LHS ;
- rhs = DPImmRHS ;
- dest = rhs - lhs ;
- if ((rhs >= lhs) || ((rhs | lhs) >> 31)) {
- ARMul_SubCarry(state,rhs,lhs,dest) ;
- ARMul_SubOverflow(state,rhs,lhs,dest) ;
- }
- else {
- CLEARC ;
- CLEARV ;
- }
- WRITESDEST(dest) ;
- break ;
-
- case 0x28 : /* ADD immed */
- dest = LHS + DPImmRHS ;
- WRITEDEST(dest) ;
- break ;
-
- case 0x29 : /* ADDS immed */
- lhs = LHS ;
- rhs = DPImmRHS ;
- dest = lhs + rhs ;
- ASSIGNZ(dest==0) ;
- if ((lhs | rhs) >> 30) { /* possible C,V,N to set */
- ASSIGNN(NEG(dest)) ;
- ARMul_AddCarry(state,lhs,rhs,dest) ;
- ARMul_AddOverflow(state,lhs,rhs,dest) ;
- }
- else {
- CLEARN ;
- CLEARC ;
- CLEARV ;
- }
- WRITESDEST(dest) ;
- break ;
-
- case 0x2a : /* ADC immed */
- dest = LHS + DPImmRHS + CFLAG ;
- WRITEDEST(dest) ;
- break ;
-
- case 0x2b : /* ADCS immed */
- lhs = LHS ;
- rhs = DPImmRHS ;
- dest = lhs + rhs + CFLAG ;
- ASSIGNZ(dest==0) ;
- if ((lhs | rhs) >> 30) { /* possible C,V,N to set */
- ASSIGNN(NEG(dest)) ;
- ARMul_AddCarry(state,lhs,rhs,dest) ;
- ARMul_AddOverflow(state,lhs,rhs,dest) ;
- }
- else {
- CLEARN ;
- CLEARC ;
- CLEARV ;
- }
- WRITESDEST(dest) ;
- break ;
-
- case 0x2c : /* SBC immed */
- dest = LHS - DPImmRHS - !CFLAG ;
- WRITEDEST(dest) ;
- break ;
-
- case 0x2d : /* SBCS immed */
- lhs = LHS ;
- rhs = DPImmRHS ;
- dest = lhs - rhs - !CFLAG ;
- if ((lhs >= rhs) || ((rhs | lhs) >> 31)) {
- ARMul_SubCarry(state,lhs,rhs,dest) ;
- ARMul_SubOverflow(state,lhs,rhs,dest) ;
- }
- else {
- CLEARC ;
- CLEARV ;
- }
- WRITESDEST(dest) ;
- break ;
-
- case 0x2e : /* RSC immed */
- dest = DPImmRHS - LHS - !CFLAG ;
- WRITEDEST(dest) ;
- break ;
-
- case 0x2f : /* RSCS immed */
- lhs = LHS ;
- rhs = DPImmRHS ;
- dest = rhs - lhs - !CFLAG ;
- if ((rhs >= lhs) || ((rhs | lhs) >> 31)) {
- ARMul_SubCarry(state,rhs,lhs,dest) ;
- ARMul_SubOverflow(state,rhs,lhs,dest) ;
- }
- else {
- CLEARC ;
- CLEARV ;
- }
- WRITESDEST(dest) ;
- break ;
-
- case 0x30 : /* TST immed */
- UNDEF_Test ;
- break ;
-
- case 0x31 : /* TSTP immed */
- if (DESTReg == 15) { /* TSTP immed */
+ case 0x20: /* AND immed */
+ dest = LHS & DPImmRHS;
+ WRITEDEST (dest);
+ break;
+
+ case 0x21: /* ANDS immed */
+ DPSImmRHS;
+ dest = LHS & rhs;
+ WRITESDEST (dest);
+ break;
+
+ case 0x22: /* EOR immed */
+ dest = LHS ^ DPImmRHS;
+ WRITEDEST (dest);
+ break;
+
+ case 0x23: /* EORS immed */
+ DPSImmRHS;
+ dest = LHS ^ rhs;
+ WRITESDEST (dest);
+ break;
+
+ case 0x24: /* SUB immed */
+ dest = LHS - DPImmRHS;
+ WRITEDEST (dest);
+ break;
+
+ case 0x25: /* SUBS immed */
+ lhs = LHS;
+ rhs = DPImmRHS;
+ dest = lhs - rhs;
+ if ((lhs >= rhs) || ((rhs | lhs) >> 31))
+ {
+ ARMul_SubCarry (state, lhs, rhs, dest);
+ ARMul_SubOverflow (state, lhs, rhs, dest);
+ }
+ else
+ {
+ CLEARC;
+ CLEARV;
+ }
+ WRITESDEST (dest);
+ break;
+
+ case 0x26: /* RSB immed */
+ dest = DPImmRHS - LHS;
+ WRITEDEST (dest);
+ break;
+
+ case 0x27: /* RSBS immed */
+ lhs = LHS;
+ rhs = DPImmRHS;
+ dest = rhs - lhs;
+ if ((rhs >= lhs) || ((rhs | lhs) >> 31))
+ {
+ ARMul_SubCarry (state, rhs, lhs, dest);
+ ARMul_SubOverflow (state, rhs, lhs, dest);
+ }
+ else
+ {
+ CLEARC;
+ CLEARV;
+ }
+ WRITESDEST (dest);
+ break;
+
+ case 0x28: /* ADD immed */
+ dest = LHS + DPImmRHS;
+ WRITEDEST (dest);
+ break;
+
+ case 0x29: /* ADDS immed */
+ lhs = LHS;
+ rhs = DPImmRHS;
+ dest = lhs + rhs;
+ ASSIGNZ (dest == 0);
+ if ((lhs | rhs) >> 30)
+ { /* possible C,V,N to set */
+ ASSIGNN (NEG (dest));
+ ARMul_AddCarry (state, lhs, rhs, dest);
+ ARMul_AddOverflow (state, lhs, rhs, dest);
+ }
+ else
+ {
+ CLEARN;
+ CLEARC;
+ CLEARV;
+ }
+ WRITESDEST (dest);
+ break;
+
+ case 0x2a: /* ADC immed */
+ dest = LHS + DPImmRHS + CFLAG;
+ WRITEDEST (dest);
+ break;
+
+ case 0x2b: /* ADCS immed */
+ lhs = LHS;
+ rhs = DPImmRHS;
+ dest = lhs + rhs + CFLAG;
+ ASSIGNZ (dest == 0);
+ if ((lhs | rhs) >> 30)
+ { /* possible C,V,N to set */
+ ASSIGNN (NEG (dest));
+ ARMul_AddCarry (state, lhs, rhs, dest);
+ ARMul_AddOverflow (state, lhs, rhs, dest);
+ }
+ else
+ {
+ CLEARN;
+ CLEARC;
+ CLEARV;
+ }
+ WRITESDEST (dest);
+ break;
+
+ case 0x2c: /* SBC immed */
+ dest = LHS - DPImmRHS - !CFLAG;
+ WRITEDEST (dest);
+ break;
+
+ case 0x2d: /* SBCS immed */
+ lhs = LHS;
+ rhs = DPImmRHS;
+ dest = lhs - rhs - !CFLAG;
+ if ((lhs >= rhs) || ((rhs | lhs) >> 31))
+ {
+ ARMul_SubCarry (state, lhs, rhs, dest);
+ ARMul_SubOverflow (state, lhs, rhs, dest);
+ }
+ else
+ {
+ CLEARC;
+ CLEARV;
+ }
+ WRITESDEST (dest);
+ break;
+
+ case 0x2e: /* RSC immed */
+ dest = DPImmRHS - LHS - !CFLAG;
+ WRITEDEST (dest);
+ break;
+
+ case 0x2f: /* RSCS immed */
+ lhs = LHS;
+ rhs = DPImmRHS;
+ dest = rhs - lhs - !CFLAG;
+ if ((rhs >= lhs) || ((rhs | lhs) >> 31))
+ {
+ ARMul_SubCarry (state, rhs, lhs, dest);
+ ARMul_SubOverflow (state, rhs, lhs, dest);
+ }
+ else
+ {
+ CLEARC;
+ CLEARV;
+ }
+ WRITESDEST (dest);
+ break;
+
+ case 0x30: /* TST immed */
+ UNDEF_Test;
+ break;
+
+ case 0x31: /* TSTP immed */
+ if (DESTReg == 15)
+ { /* TSTP immed */
#ifdef MODE32
- state->Cpsr = GETSPSR(state->Bank) ;
- ARMul_CPSRAltered(state) ;
+ state->Cpsr = GETSPSR (state->Bank);
+ ARMul_CPSRAltered (state);
#else
- temp = LHS & DPImmRHS ;
- SETR15PSR(temp) ;
-#endif
- }
- else {
- DPSImmRHS ; /* TST immed */
- dest = LHS & rhs ;
- ARMul_NegZero(state,dest) ;
- }
- break ;
-
- case 0x32 : /* TEQ immed and MSR immed to CPSR */
- if (DESTReg==15 && BITS(17,18)==0) { /* MSR immed to CPSR */
- ARMul_FixCPSR(state,instr,DPImmRHS) ;
- }
- else {
- UNDEF_Test ;
- }
- break ;
-
- case 0x33 : /* TEQP immed */
- if (DESTReg == 15) { /* TEQP immed */
+ temp = LHS & DPImmRHS;
+ SETR15PSR (temp);
+#endif
+ }
+ else
+ {
+ DPSImmRHS; /* TST immed */
+ dest = LHS & rhs;
+ ARMul_NegZero (state, dest);
+ }
+ break;
+
+ case 0x32: /* TEQ immed and MSR immed to CPSR */
+ if (DESTReg == 15 && BITS (17, 18) == 0)
+ { /* MSR immed to CPSR */
+ ARMul_FixCPSR (state, instr, DPImmRHS);
+ }
+ else
+ {
+ UNDEF_Test;
+ }
+ break;
+
+ case 0x33: /* TEQP immed */
+ if (DESTReg == 15)
+ { /* TEQP immed */
#ifdef MODE32
- state->Cpsr = GETSPSR(state->Bank) ;
- ARMul_CPSRAltered(state) ;
+ state->Cpsr = GETSPSR (state->Bank);
+ ARMul_CPSRAltered (state);
#else
- temp = LHS ^ DPImmRHS ;
- SETR15PSR(temp) ;
-#endif
- }
- else {
- DPSImmRHS ; /* TEQ immed */
- dest = LHS ^ rhs ;
- ARMul_NegZero(state,dest) ;
- }
- break ;
-
- case 0x34 : /* CMP immed */
- UNDEF_Test ;
- break ;
-
- case 0x35 : /* CMPP immed */
- if (DESTReg == 15) { /* CMPP immed */
+ temp = LHS ^ DPImmRHS;
+ SETR15PSR (temp);
+#endif
+ }
+ else
+ {
+ DPSImmRHS; /* TEQ immed */
+ dest = LHS ^ rhs;
+ ARMul_NegZero (state, dest);
+ }
+ break;
+
+ case 0x34: /* CMP immed */
+ UNDEF_Test;
+ break;
+
+ case 0x35: /* CMPP immed */
+ if (DESTReg == 15)
+ { /* CMPP immed */
#ifdef MODE32
- state->Cpsr = GETSPSR(state->Bank) ;
- ARMul_CPSRAltered(state) ;
+ state->Cpsr = GETSPSR (state->Bank);
+ ARMul_CPSRAltered (state);
#else
- temp = LHS - DPImmRHS ;
- SETR15PSR(temp) ;
-#endif
- break ;
- }
- else {
- lhs = LHS ; /* CMP immed */
- rhs = DPImmRHS ;
- dest = lhs - rhs ;
- ARMul_NegZero(state,dest) ;
- if ((lhs >= rhs) || ((rhs | lhs) >> 31)) {
- ARMul_SubCarry(state,lhs,rhs,dest) ;
- ARMul_SubOverflow(state,lhs,rhs,dest) ;
- }
- else {
- CLEARC ;
- CLEARV ;
- }
- }
- break ;
-
- case 0x36 : /* CMN immed and MSR immed to SPSR */
- if (DESTReg==15 && BITS(17,18)==0) /* MSR */
- ARMul_FixSPSR(state, instr, DPImmRHS) ;
- else {
- UNDEF_Test ;
- }
- break ;
-
- case 0x37 : /* CMNP immed */
- if (DESTReg == 15) { /* CMNP immed */
+ temp = LHS - DPImmRHS;
+ SETR15PSR (temp);
+#endif
+ break;
+ }
+ else
+ {
+ lhs = LHS; /* CMP immed */
+ rhs = DPImmRHS;
+ dest = lhs - rhs;
+ ARMul_NegZero (state, dest);
+ if ((lhs >= rhs) || ((rhs | lhs) >> 31))
+ {
+ ARMul_SubCarry (state, lhs, rhs, dest);
+ ARMul_SubOverflow (state, lhs, rhs, dest);
+ }
+ else
+ {
+ CLEARC;
+ CLEARV;
+ }
+ }
+ break;
+
+ case 0x36: /* CMN immed and MSR immed to SPSR */
+ if (DESTReg == 15 && BITS (17, 18) == 0) /* MSR */
+ ARMul_FixSPSR (state, instr, DPImmRHS);
+ else
+ {
+ UNDEF_Test;
+ }
+ break;
+
+ case 0x37: /* CMNP immed */
+ if (DESTReg == 15)
+ { /* CMNP immed */
#ifdef MODE32
- state->Cpsr = GETSPSR(state->Bank) ;
- ARMul_CPSRAltered(state) ;
+ state->Cpsr = GETSPSR (state->Bank);
+ ARMul_CPSRAltered (state);
#else
- temp = LHS + DPImmRHS ;
- SETR15PSR(temp) ;
-#endif
- break ;
- }
- else {
- lhs = LHS ; /* CMN immed */
- rhs = DPImmRHS ;
- dest = lhs + rhs ;
- ASSIGNZ(dest==0) ;
- if ((lhs | rhs) >> 30) { /* possible C,V,N to set */
- ASSIGNN(NEG(dest)) ;
- ARMul_AddCarry(state,lhs,rhs,dest) ;
- ARMul_AddOverflow(state,lhs,rhs,dest) ;
- }
- else {
- CLEARN ;
- CLEARC ;
- CLEARV ;
- }
- }
- break ;
-
- case 0x38 : /* ORR immed */
- dest = LHS | DPImmRHS ;
- WRITEDEST(dest) ;
- break ;
-
- case 0x39 : /* ORRS immed */
- DPSImmRHS ;
- dest = LHS | rhs ;
- WRITESDEST(dest) ;
- break ;
-
- case 0x3a : /* MOV immed */
- dest = DPImmRHS ;
- WRITEDEST(dest) ;
- break ;
-
- case 0x3b : /* MOVS immed */
- DPSImmRHS ;
- WRITESDEST(rhs) ;
- break ;
-
- case 0x3c : /* BIC immed */
- dest = LHS & ~DPImmRHS ;
- WRITEDEST(dest) ;
- break ;
-
- case 0x3d : /* BICS immed */
- DPSImmRHS ;
- dest = LHS & ~rhs ;
- WRITESDEST(dest) ;
- break ;
-
- case 0x3e : /* MVN immed */
- dest = ~DPImmRHS ;
- WRITEDEST(dest) ;
- break ;
-
- case 0x3f : /* MVNS immed */
- DPSImmRHS ;
- WRITESDEST(~rhs) ;
- break ;
+ temp = LHS + DPImmRHS;
+ SETR15PSR (temp);
+#endif
+ break;
+ }
+ else
+ {
+ lhs = LHS; /* CMN immed */
+ rhs = DPImmRHS;
+ dest = lhs + rhs;
+ ASSIGNZ (dest == 0);
+ if ((lhs | rhs) >> 30)
+ { /* possible C,V,N to set */
+ ASSIGNN (NEG (dest));
+ ARMul_AddCarry (state, lhs, rhs, dest);
+ ARMul_AddOverflow (state, lhs, rhs, dest);
+ }
+ else
+ {
+ CLEARN;
+ CLEARC;
+ CLEARV;
+ }
+ }
+ break;
+
+ case 0x38: /* ORR immed */
+ dest = LHS | DPImmRHS;
+ WRITEDEST (dest);
+ break;
+
+ case 0x39: /* ORRS immed */
+ DPSImmRHS;
+ dest = LHS | rhs;
+ WRITESDEST (dest);
+ break;
+
+ case 0x3a: /* MOV immed */
+ dest = DPImmRHS;
+ WRITEDEST (dest);
+ break;
+
+ case 0x3b: /* MOVS immed */
+ DPSImmRHS;
+ WRITESDEST (rhs);
+ break;
+
+ case 0x3c: /* BIC immed */
+ dest = LHS & ~DPImmRHS;
+ WRITEDEST (dest);
+ break;
+
+ case 0x3d: /* BICS immed */
+ DPSImmRHS;
+ dest = LHS & ~rhs;
+ WRITESDEST (dest);
+ break;
+
+ case 0x3e: /* MVN immed */
+ dest = ~DPImmRHS;
+ WRITEDEST (dest);
+ break;
+
+ case 0x3f: /* MVNS immed */
+ DPSImmRHS;
+ WRITESDEST (~rhs);
+ break;
/***************************************************************************\
* Single Data Transfer Immediate RHS Instructions *
\***************************************************************************/
- case 0x40 : /* Store Word, No WriteBack, Post Dec, Immed */
- lhs = LHS ;
- if (StoreWord(state,instr,lhs))
- LSBase = lhs - LSImmRHS ;
- break ;
-
- case 0x41 : /* Load Word, No WriteBack, Post Dec, Immed */
- lhs = LHS ;
- if (LoadWord(state,instr,lhs))
- LSBase = lhs - LSImmRHS ;
- break ;
-
- case 0x42 : /* Store Word, WriteBack, Post Dec, Immed */
- UNDEF_LSRBaseEQDestWb ;
- UNDEF_LSRPCBaseWb ;
- lhs = LHS ;
- temp = lhs - LSImmRHS ;
- state->NtransSig = LOW ;
- if (StoreWord(state,instr,lhs))
- LSBase = temp ;
- state->NtransSig = (state->Mode & 3)?HIGH:LOW ;
- break ;
-
- case 0x43 : /* Load Word, WriteBack, Post Dec, Immed */
- UNDEF_LSRBaseEQDestWb ;
- UNDEF_LSRPCBaseWb ;
- lhs = LHS ;
- state->NtransSig = LOW ;
- if (LoadWord(state,instr,lhs))
- LSBase = lhs - LSImmRHS ;
- state->NtransSig = (state->Mode & 3)?HIGH:LOW ;
- break ;
-
- case 0x44 : /* Store Byte, No WriteBack, Post Dec, Immed */
- lhs = LHS ;
- if (StoreByte(state,instr,lhs))
- LSBase = lhs - LSImmRHS ;
- break ;
-
- case 0x45 : /* Load Byte, No WriteBack, Post Dec, Immed */
- lhs = LHS ;
- if (LoadByte(state,instr,lhs,LUNSIGNED))
- LSBase = lhs - LSImmRHS ;
- break ;
-
- case 0x46 : /* Store Byte, WriteBack, Post Dec, Immed */
- UNDEF_LSRBaseEQDestWb ;
- UNDEF_LSRPCBaseWb ;
- lhs = LHS ;
- state->NtransSig = LOW ;
- if (StoreByte(state,instr,lhs))
- LSBase = lhs - LSImmRHS ;
- state->NtransSig = (state->Mode & 3)?HIGH:LOW ;
- break ;
-
- case 0x47 : /* Load Byte, WriteBack, Post Dec, Immed */
- UNDEF_LSRBaseEQDestWb ;
- UNDEF_LSRPCBaseWb ;
- lhs = LHS ;
- state->NtransSig = LOW ;
- if (LoadByte(state,instr,lhs,LUNSIGNED))
- LSBase = lhs - LSImmRHS ;
- state->NtransSig = (state->Mode & 3)?HIGH:LOW ;
- break ;
-
- case 0x48 : /* Store Word, No WriteBack, Post Inc, Immed */
- lhs = LHS ;
- if (StoreWord(state,instr,lhs))
- LSBase = lhs + LSImmRHS ;
- break ;
-
- case 0x49 : /* Load Word, No WriteBack, Post Inc, Immed */
- lhs = LHS ;
- if (LoadWord(state,instr,lhs))
- LSBase = lhs + LSImmRHS ;
- break ;
-
- case 0x4a : /* Store Word, WriteBack, Post Inc, Immed */
- UNDEF_LSRBaseEQDestWb ;
- UNDEF_LSRPCBaseWb ;
- lhs = LHS ;
- state->NtransSig = LOW ;
- if (StoreWord(state,instr,lhs))
- LSBase = lhs + LSImmRHS ;
- state->NtransSig = (state->Mode & 3)?HIGH:LOW ;
- break ;
-
- case 0x4b : /* Load Word, WriteBack, Post Inc, Immed */
- UNDEF_LSRBaseEQDestWb ;
- UNDEF_LSRPCBaseWb ;
- lhs = LHS ;
- state->NtransSig = LOW ;
- if (LoadWord(state,instr,lhs))
- LSBase = lhs + LSImmRHS ;
- state->NtransSig = (state->Mode & 3)?HIGH:LOW ;
- break ;
-
- case 0x4c : /* Store Byte, No WriteBack, Post Inc, Immed */
- lhs = LHS ;
- if (StoreByte(state,instr,lhs))
- LSBase = lhs + LSImmRHS ;
- break ;
-
- case 0x4d : /* Load Byte, No WriteBack, Post Inc, Immed */
- lhs = LHS ;
- if (LoadByte(state,instr,lhs,LUNSIGNED))
- LSBase = lhs + LSImmRHS ;
- break ;
-
- case 0x4e : /* Store Byte, WriteBack, Post Inc, Immed */
- UNDEF_LSRBaseEQDestWb ;
- UNDEF_LSRPCBaseWb ;
- lhs = LHS ;
- state->NtransSig = LOW ;
- if (StoreByte(state,instr,lhs))
- LSBase = lhs + LSImmRHS ;
- state->NtransSig = (state->Mode & 3)?HIGH:LOW ;
- break ;
-
- case 0x4f : /* Load Byte, WriteBack, Post Inc, Immed */
- UNDEF_LSRBaseEQDestWb ;
- UNDEF_LSRPCBaseWb ;
- lhs = LHS ;
- state->NtransSig = LOW ;
- if (LoadByte(state,instr,lhs,LUNSIGNED))
- LSBase = lhs + LSImmRHS ;
- state->NtransSig = (state->Mode & 3)?HIGH:LOW ;
- break ;
-
-
- case 0x50 : /* Store Word, No WriteBack, Pre Dec, Immed */
- (void)StoreWord(state,instr,LHS - LSImmRHS) ;
- break ;
-
- case 0x51 : /* Load Word, No WriteBack, Pre Dec, Immed */
- (void)LoadWord(state,instr,LHS - LSImmRHS) ;
- break ;
-
- case 0x52 : /* Store Word, WriteBack, Pre Dec, Immed */
- UNDEF_LSRBaseEQDestWb ;
- UNDEF_LSRPCBaseWb ;
- temp = LHS - LSImmRHS ;
- if (StoreWord(state,instr,temp))
- LSBase = temp ;
- break ;
-
- case 0x53 : /* Load Word, WriteBack, Pre Dec, Immed */
- UNDEF_LSRBaseEQDestWb ;
- UNDEF_LSRPCBaseWb ;
- temp = LHS - LSImmRHS ;
- if (LoadWord(state,instr,temp))
- LSBase = temp ;
- break ;
-
- case 0x54 : /* Store Byte, No WriteBack, Pre Dec, Immed */
- (void)StoreByte(state,instr,LHS - LSImmRHS) ;
- break ;
-
- case 0x55 : /* Load Byte, No WriteBack, Pre Dec, Immed */
- (void)LoadByte(state,instr,LHS - LSImmRHS,LUNSIGNED) ;
- break ;
-
- case 0x56 : /* Store Byte, WriteBack, Pre Dec, Immed */
- UNDEF_LSRBaseEQDestWb ;
- UNDEF_LSRPCBaseWb ;
- temp = LHS - LSImmRHS ;
- if (StoreByte(state,instr,temp))
- LSBase = temp ;
- break ;
-
- case 0x57 : /* Load Byte, WriteBack, Pre Dec, Immed */
- UNDEF_LSRBaseEQDestWb ;
- UNDEF_LSRPCBaseWb ;
- temp = LHS - LSImmRHS ;
- if (LoadByte(state,instr,temp,LUNSIGNED))
- LSBase = temp ;
- break ;
-
- case 0x58 : /* Store Word, No WriteBack, Pre Inc, Immed */
- (void)StoreWord(state,instr,LHS + LSImmRHS) ;
- break ;
-
- case 0x59 : /* Load Word, No WriteBack, Pre Inc, Immed */
- (void)LoadWord(state,instr,LHS + LSImmRHS) ;
- break ;
-
- case 0x5a : /* Store Word, WriteBack, Pre Inc, Immed */
- UNDEF_LSRBaseEQDestWb ;
- UNDEF_LSRPCBaseWb ;
- temp = LHS + LSImmRHS ;
- if (StoreWord(state,instr,temp))
- LSBase = temp ;
- break ;
-
- case 0x5b : /* Load Word, WriteBack, Pre Inc, Immed */
- UNDEF_LSRBaseEQDestWb ;
- UNDEF_LSRPCBaseWb ;
- temp = LHS + LSImmRHS ;
- if (LoadWord(state,instr,temp))
- LSBase = temp ;
- break ;
-
- case 0x5c : /* Store Byte, No WriteBack, Pre Inc, Immed */
- (void)StoreByte(state,instr,LHS + LSImmRHS) ;
- break ;
-
- case 0x5d : /* Load Byte, No WriteBack, Pre Inc, Immed */
- (void)LoadByte(state,instr,LHS + LSImmRHS,LUNSIGNED) ;
- break ;
-
- case 0x5e : /* Store Byte, WriteBack, Pre Inc, Immed */
- UNDEF_LSRBaseEQDestWb ;
- UNDEF_LSRPCBaseWb ;
- temp = LHS + LSImmRHS ;
- if (StoreByte(state,instr,temp))
- LSBase = temp ;
- break ;
-
- case 0x5f : /* Load Byte, WriteBack, Pre Inc, Immed */
- UNDEF_LSRBaseEQDestWb ;
- UNDEF_LSRPCBaseWb ;
- temp = LHS + LSImmRHS ;
- if (LoadByte(state,instr,temp,LUNSIGNED))
- LSBase = temp ;
- break ;
+ case 0x40: /* Store Word, No WriteBack, Post Dec, Immed */
+ lhs = LHS;
+ if (StoreWord (state, instr, lhs))
+ LSBase = lhs - LSImmRHS;
+ break;
+
+ case 0x41: /* Load Word, No WriteBack, Post Dec, Immed */
+ lhs = LHS;
+ if (LoadWord (state, instr, lhs))
+ LSBase = lhs - LSImmRHS;
+ break;
+
+ case 0x42: /* Store Word, WriteBack, Post Dec, Immed */
+ UNDEF_LSRBaseEQDestWb;
+ UNDEF_LSRPCBaseWb;
+ lhs = LHS;
+ temp = lhs - LSImmRHS;
+ state->NtransSig = LOW;
+ if (StoreWord (state, instr, lhs))
+ LSBase = temp;
+ state->NtransSig = (state->Mode & 3) ? HIGH : LOW;
+ break;
+
+ case 0x43: /* Load Word, WriteBack, Post Dec, Immed */
+ UNDEF_LSRBaseEQDestWb;
+ UNDEF_LSRPCBaseWb;
+ lhs = LHS;
+ state->NtransSig = LOW;
+ if (LoadWord (state, instr, lhs))
+ LSBase = lhs - LSImmRHS;
+ state->NtransSig = (state->Mode & 3) ? HIGH : LOW;
+ break;
+
+ case 0x44: /* Store Byte, No WriteBack, Post Dec, Immed */
+ lhs = LHS;
+ if (StoreByte (state, instr, lhs))
+ LSBase = lhs - LSImmRHS;
+ break;
+
+ case 0x45: /* Load Byte, No WriteBack, Post Dec, Immed */
+ lhs = LHS;
+ if (LoadByte (state, instr, lhs, LUNSIGNED))
+ LSBase = lhs - LSImmRHS;
+ break;
+
+ case 0x46: /* Store Byte, WriteBack, Post Dec, Immed */
+ UNDEF_LSRBaseEQDestWb;
+ UNDEF_LSRPCBaseWb;
+ lhs = LHS;
+ state->NtransSig = LOW;
+ if (StoreByte (state, instr, lhs))
+ LSBase = lhs - LSImmRHS;
+ state->NtransSig = (state->Mode & 3) ? HIGH : LOW;
+ break;
+
+ case 0x47: /* Load Byte, WriteBack, Post Dec, Immed */
+ UNDEF_LSRBaseEQDestWb;
+ UNDEF_LSRPCBaseWb;
+ lhs = LHS;
+ state->NtransSig = LOW;
+ if (LoadByte (state, instr, lhs, LUNSIGNED))
+ LSBase = lhs - LSImmRHS;
+ state->NtransSig = (state->Mode & 3) ? HIGH : LOW;
+ break;
+
+ case 0x48: /* Store Word, No WriteBack, Post Inc, Immed */
+ lhs = LHS;
+ if (StoreWord (state, instr, lhs))
+ LSBase = lhs + LSImmRHS;
+ break;
+
+ case 0x49: /* Load Word, No WriteBack, Post Inc, Immed */
+ lhs = LHS;
+ if (LoadWord (state, instr, lhs))
+ LSBase = lhs + LSImmRHS;
+ break;
+
+ case 0x4a: /* Store Word, WriteBack, Post Inc, Immed */
+ UNDEF_LSRBaseEQDestWb;
+ UNDEF_LSRPCBaseWb;
+ lhs = LHS;
+ state->NtransSig = LOW;
+ if (StoreWord (state, instr, lhs))
+ LSBase = lhs + LSImmRHS;
+ state->NtransSig = (state->Mode & 3) ? HIGH : LOW;
+ break;
+
+ case 0x4b: /* Load Word, WriteBack, Post Inc, Immed */
+ UNDEF_LSRBaseEQDestWb;
+ UNDEF_LSRPCBaseWb;
+ lhs = LHS;
+ state->NtransSig = LOW;
+ if (LoadWord (state, instr, lhs))
+ LSBase = lhs + LSImmRHS;
+ state->NtransSig = (state->Mode & 3) ? HIGH : LOW;
+ break;
+
+ case 0x4c: /* Store Byte, No WriteBack, Post Inc, Immed */
+ lhs = LHS;
+ if (StoreByte (state, instr, lhs))
+ LSBase = lhs + LSImmRHS;
+ break;
+
+ case 0x4d: /* Load Byte, No WriteBack, Post Inc, Immed */
+ lhs = LHS;
+ if (LoadByte (state, instr, lhs, LUNSIGNED))
+ LSBase = lhs + LSImmRHS;
+ break;
+
+ case 0x4e: /* Store Byte, WriteBack, Post Inc, Immed */
+ UNDEF_LSRBaseEQDestWb;
+ UNDEF_LSRPCBaseWb;
+ lhs = LHS;
+ state->NtransSig = LOW;
+ if (StoreByte (state, instr, lhs))
+ LSBase = lhs + LSImmRHS;
+ state->NtransSig = (state->Mode & 3) ? HIGH : LOW;
+ break;
+
+ case 0x4f: /* Load Byte, WriteBack, Post Inc, Immed */
+ UNDEF_LSRBaseEQDestWb;
+ UNDEF_LSRPCBaseWb;
+ lhs = LHS;
+ state->NtransSig = LOW;
+ if (LoadByte (state, instr, lhs, LUNSIGNED))
+ LSBase = lhs + LSImmRHS;
+ state->NtransSig = (state->Mode & 3) ? HIGH : LOW;
+ break;
+
+
+ case 0x50: /* Store Word, No WriteBack, Pre Dec, Immed */
+ (void) StoreWord (state, instr, LHS - LSImmRHS);
+ break;
+
+ case 0x51: /* Load Word, No WriteBack, Pre Dec, Immed */
+ (void) LoadWord (state, instr, LHS - LSImmRHS);
+ break;
+
+ case 0x52: /* Store Word, WriteBack, Pre Dec, Immed */
+ UNDEF_LSRBaseEQDestWb;
+ UNDEF_LSRPCBaseWb;
+ temp = LHS - LSImmRHS;
+ if (StoreWord (state, instr, temp))
+ LSBase = temp;
+ break;
+
+ case 0x53: /* Load Word, WriteBack, Pre Dec, Immed */
+ UNDEF_LSRBaseEQDestWb;
+ UNDEF_LSRPCBaseWb;
+ temp = LHS - LSImmRHS;
+ if (LoadWord (state, instr, temp))
+ LSBase = temp;
+ break;
+
+ case 0x54: /* Store Byte, No WriteBack, Pre Dec, Immed */
+ (void) StoreByte (state, instr, LHS - LSImmRHS);
+ break;
+
+ case 0x55: /* Load Byte, No WriteBack, Pre Dec, Immed */
+ (void) LoadByte (state, instr, LHS - LSImmRHS, LUNSIGNED);
+ break;
+
+ case 0x56: /* Store Byte, WriteBack, Pre Dec, Immed */
+ UNDEF_LSRBaseEQDestWb;
+ UNDEF_LSRPCBaseWb;
+ temp = LHS - LSImmRHS;
+ if (StoreByte (state, instr, temp))
+ LSBase = temp;
+ break;
+
+ case 0x57: /* Load Byte, WriteBack, Pre Dec, Immed */
+ UNDEF_LSRBaseEQDestWb;
+ UNDEF_LSRPCBaseWb;
+ temp = LHS - LSImmRHS;
+ if (LoadByte (state, instr, temp, LUNSIGNED))
+ LSBase = temp;
+ break;
+
+ case 0x58: /* Store Word, No WriteBack, Pre Inc, Immed */
+ (void) StoreWord (state, instr, LHS + LSImmRHS);
+ break;
+
+ case 0x59: /* Load Word, No WriteBack, Pre Inc, Immed */
+ (void) LoadWord (state, instr, LHS + LSImmRHS);
+ break;
+
+ case 0x5a: /* Store Word, WriteBack, Pre Inc, Immed */
+ UNDEF_LSRBaseEQDestWb;
+ UNDEF_LSRPCBaseWb;
+ temp = LHS + LSImmRHS;
+ if (StoreWord (state, instr, temp))
+ LSBase = temp;
+ break;
+
+ case 0x5b: /* Load Word, WriteBack, Pre Inc, Immed */
+ UNDEF_LSRBaseEQDestWb;
+ UNDEF_LSRPCBaseWb;
+ temp = LHS + LSImmRHS;
+ if (LoadWord (state, instr, temp))
+ LSBase = temp;
+ break;
+
+ case 0x5c: /* Store Byte, No WriteBack, Pre Inc, Immed */
+ (void) StoreByte (state, instr, LHS + LSImmRHS);
+ break;
+
+ case 0x5d: /* Load Byte, No WriteBack, Pre Inc, Immed */
+ (void) LoadByte (state, instr, LHS + LSImmRHS, LUNSIGNED);
+ break;
+
+ case 0x5e: /* Store Byte, WriteBack, Pre Inc, Immed */
+ UNDEF_LSRBaseEQDestWb;
+ UNDEF_LSRPCBaseWb;
+ temp = LHS + LSImmRHS;
+ if (StoreByte (state, instr, temp))
+ LSBase = temp;
+ break;
+
+ case 0x5f: /* Load Byte, WriteBack, Pre Inc, Immed */
+ UNDEF_LSRBaseEQDestWb;
+ UNDEF_LSRPCBaseWb;
+ temp = LHS + LSImmRHS;
+ if (LoadByte (state, instr, temp, LUNSIGNED))
+ LSBase = temp;
+ break;
/***************************************************************************\
* Single Data Transfer Register RHS Instructions *
\***************************************************************************/
- case 0x60 : /* Store Word, No WriteBack, Post Dec, Reg */
- if (BIT(4)) {
- ARMul_UndefInstr(state,instr) ;
- break ;
- }
- UNDEF_LSRBaseEQOffWb ;
- UNDEF_LSRBaseEQDestWb ;
- UNDEF_LSRPCBaseWb ;
- UNDEF_LSRPCOffWb ;
- lhs = LHS ;
- if (StoreWord(state,instr,lhs))
- LSBase = lhs - LSRegRHS ;
- break ;
-
- case 0x61 : /* Load Word, No WriteBack, Post Dec, Reg */
- if (BIT(4)) {
- ARMul_UndefInstr(state,instr) ;
- break ;
- }
- UNDEF_LSRBaseEQOffWb ;
- UNDEF_LSRBaseEQDestWb ;
- UNDEF_LSRPCBaseWb ;
- UNDEF_LSRPCOffWb ;
- lhs = LHS ;
- if (LoadWord(state,instr,lhs))
- LSBase = lhs - LSRegRHS ;
- break ;
-
- case 0x62 : /* Store Word, WriteBack, Post Dec, Reg */
- if (BIT(4)) {
- ARMul_UndefInstr(state,instr) ;
- break ;
- }
- UNDEF_LSRBaseEQOffWb ;
- UNDEF_LSRBaseEQDestWb ;
- UNDEF_LSRPCBaseWb ;
- UNDEF_LSRPCOffWb ;
- lhs = LHS ;
- state->NtransSig = LOW ;
- if (StoreWord(state,instr,lhs))
- LSBase = lhs - LSRegRHS ;
- state->NtransSig = (state->Mode & 3)?HIGH:LOW ;
- break ;
-
- case 0x63 : /* Load Word, WriteBack, Post Dec, Reg */
- if (BIT(4)) {
- ARMul_UndefInstr(state,instr) ;
- break ;
- }
- UNDEF_LSRBaseEQOffWb ;
- UNDEF_LSRBaseEQDestWb ;
- UNDEF_LSRPCBaseWb ;
- UNDEF_LSRPCOffWb ;
- lhs = LHS ;
- state->NtransSig = LOW ;
- if (LoadWord(state,instr,lhs))
- LSBase = lhs - LSRegRHS ;
- state->NtransSig = (state->Mode & 3)?HIGH:LOW ;
- break ;
-
- case 0x64 : /* Store Byte, No WriteBack, Post Dec, Reg */
- if (BIT(4)) {
- ARMul_UndefInstr(state,instr) ;
- break ;
- }
- UNDEF_LSRBaseEQOffWb ;
- UNDEF_LSRBaseEQDestWb ;
- UNDEF_LSRPCBaseWb ;
- UNDEF_LSRPCOffWb ;
- lhs = LHS ;
- if (StoreByte(state,instr,lhs))
- LSBase = lhs - LSRegRHS ;
- break ;
-
- case 0x65 : /* Load Byte, No WriteBack, Post Dec, Reg */
- if (BIT(4)) {
- ARMul_UndefInstr(state,instr) ;
- break ;
- }
- UNDEF_LSRBaseEQOffWb ;
- UNDEF_LSRBaseEQDestWb ;
- UNDEF_LSRPCBaseWb ;
- UNDEF_LSRPCOffWb ;
- lhs = LHS ;
- if (LoadByte(state,instr,lhs,LUNSIGNED))
- LSBase = lhs - LSRegRHS ;
- break ;
-
- case 0x66 : /* Store Byte, WriteBack, Post Dec, Reg */
- if (BIT(4)) {
- ARMul_UndefInstr(state,instr) ;
- break ;
- }
- UNDEF_LSRBaseEQOffWb ;
- UNDEF_LSRBaseEQDestWb ;
- UNDEF_LSRPCBaseWb ;
- UNDEF_LSRPCOffWb ;
- lhs = LHS ;
- state->NtransSig = LOW ;
- if (StoreByte(state,instr,lhs))
- LSBase = lhs - LSRegRHS ;
- state->NtransSig = (state->Mode & 3)?HIGH:LOW ;
- break ;
-
- case 0x67 : /* Load Byte, WriteBack, Post Dec, Reg */
- if (BIT(4)) {
- ARMul_UndefInstr(state,instr) ;
- break ;
- }
- UNDEF_LSRBaseEQOffWb ;
- UNDEF_LSRBaseEQDestWb ;
- UNDEF_LSRPCBaseWb ;
- UNDEF_LSRPCOffWb ;
- lhs = LHS ;
- state->NtransSig = LOW ;
- if (LoadByte(state,instr,lhs,LUNSIGNED))
- LSBase = lhs - LSRegRHS ;
- state->NtransSig = (state->Mode & 3)?HIGH:LOW ;
- break ;
-
- case 0x68 : /* Store Word, No WriteBack, Post Inc, Reg */
- if (BIT(4)) {
- ARMul_UndefInstr(state,instr) ;
- break ;
- }
- UNDEF_LSRBaseEQOffWb ;
- UNDEF_LSRBaseEQDestWb ;
- UNDEF_LSRPCBaseWb ;
- UNDEF_LSRPCOffWb ;
- lhs = LHS ;
- if (StoreWord(state,instr,lhs))
- LSBase = lhs + LSRegRHS ;
- break ;
-
- case 0x69 : /* Load Word, No WriteBack, Post Inc, Reg */
- if (BIT(4)) {
- ARMul_UndefInstr(state,instr) ;
- break ;
- }
- UNDEF_LSRBaseEQOffWb ;
- UNDEF_LSRBaseEQDestWb ;
- UNDEF_LSRPCBaseWb ;
- UNDEF_LSRPCOffWb ;
- lhs = LHS ;
- if (LoadWord(state,instr,lhs))
- LSBase = lhs + LSRegRHS ;
- break ;
-
- case 0x6a : /* Store Word, WriteBack, Post Inc, Reg */
- if (BIT(4)) {
- ARMul_UndefInstr(state,instr) ;
- break ;
- }
- UNDEF_LSRBaseEQOffWb ;
- UNDEF_LSRBaseEQDestWb ;
- UNDEF_LSRPCBaseWb ;
- UNDEF_LSRPCOffWb ;
- lhs = LHS ;
- state->NtransSig = LOW ;
- if (StoreWord(state,instr,lhs))
- LSBase = lhs + LSRegRHS ;
- state->NtransSig = (state->Mode & 3)?HIGH:LOW ;
- break ;
-
- case 0x6b : /* Load Word, WriteBack, Post Inc, Reg */
- if (BIT(4)) {
- ARMul_UndefInstr(state,instr) ;
- break ;
- }
- UNDEF_LSRBaseEQOffWb ;
- UNDEF_LSRBaseEQDestWb ;
- UNDEF_LSRPCBaseWb ;
- UNDEF_LSRPCOffWb ;
- lhs = LHS ;
- state->NtransSig = LOW ;
- if (LoadWord(state,instr,lhs))
- LSBase = lhs + LSRegRHS ;
- state->NtransSig = (state->Mode & 3)?HIGH:LOW ;
- break ;
-
- case 0x6c : /* Store Byte, No WriteBack, Post Inc, Reg */
- if (BIT(4)) {
- ARMul_UndefInstr(state,instr) ;
- break ;
- }
- UNDEF_LSRBaseEQOffWb ;
- UNDEF_LSRBaseEQDestWb ;
- UNDEF_LSRPCBaseWb ;
- UNDEF_LSRPCOffWb ;
- lhs = LHS ;
- if (StoreByte(state,instr,lhs))
- LSBase = lhs + LSRegRHS ;
- break ;
-
- case 0x6d : /* Load Byte, No WriteBack, Post Inc, Reg */
- if (BIT(4)) {
- ARMul_UndefInstr(state,instr) ;
- break ;
- }
- UNDEF_LSRBaseEQOffWb ;
- UNDEF_LSRBaseEQDestWb ;
- UNDEF_LSRPCBaseWb ;
- UNDEF_LSRPCOffWb ;
- lhs = LHS ;
- if (LoadByte(state,instr,lhs,LUNSIGNED))
- LSBase = lhs + LSRegRHS ;
- break ;
-
- case 0x6e : /* Store Byte, WriteBack, Post Inc, Reg */
- if (BIT(4)) {
- ARMul_UndefInstr(state,instr) ;
- break ;
- }
- UNDEF_LSRBaseEQOffWb ;
- UNDEF_LSRBaseEQDestWb ;
- UNDEF_LSRPCBaseWb ;
- UNDEF_LSRPCOffWb ;
- lhs = LHS ;
- state->NtransSig = LOW ;
- if (StoreByte(state,instr,lhs))
- LSBase = lhs + LSRegRHS ;
- state->NtransSig = (state->Mode & 3)?HIGH:LOW ;
- break ;
-
- case 0x6f : /* Load Byte, WriteBack, Post Inc, Reg */
- if (BIT(4)) {
- ARMul_UndefInstr(state,instr) ;
- break ;
- }
- UNDEF_LSRBaseEQOffWb ;
- UNDEF_LSRBaseEQDestWb ;
- UNDEF_LSRPCBaseWb ;
- UNDEF_LSRPCOffWb ;
- lhs = LHS ;
- state->NtransSig = LOW ;
- if (LoadByte(state,instr,lhs,LUNSIGNED))
- LSBase = lhs + LSRegRHS ;
- state->NtransSig = (state->Mode & 3)?HIGH:LOW ;
- break ;
-
-
- case 0x70 : /* Store Word, No WriteBack, Pre Dec, Reg */
- if (BIT(4)) {
- ARMul_UndefInstr(state,instr) ;
- break ;
- }
- (void)StoreWord(state,instr,LHS - LSRegRHS) ;
- break ;
-
- case 0x71 : /* Load Word, No WriteBack, Pre Dec, Reg */
- if (BIT(4)) {
- ARMul_UndefInstr(state,instr) ;
- break ;
- }
- (void)LoadWord(state,instr,LHS - LSRegRHS) ;
- break ;
-
- case 0x72 : /* Store Word, WriteBack, Pre Dec, Reg */
- if (BIT(4)) {
- ARMul_UndefInstr(state,instr) ;
- break ;
- }
- UNDEF_LSRBaseEQOffWb ;
- UNDEF_LSRBaseEQDestWb ;
- UNDEF_LSRPCBaseWb ;
- UNDEF_LSRPCOffWb ;
- temp = LHS - LSRegRHS ;
- if (StoreWord(state,instr,temp))
- LSBase = temp ;
- break ;
-
- case 0x73 : /* Load Word, WriteBack, Pre Dec, Reg */
- if (BIT(4)) {
- ARMul_UndefInstr(state,instr) ;
- break ;
- }
- UNDEF_LSRBaseEQOffWb ;
- UNDEF_LSRBaseEQDestWb ;
- UNDEF_LSRPCBaseWb ;
- UNDEF_LSRPCOffWb ;
- temp = LHS - LSRegRHS ;
- if (LoadWord(state,instr,temp))
- LSBase = temp ;
- break ;
-
- case 0x74 : /* Store Byte, No WriteBack, Pre Dec, Reg */
- if (BIT(4)) {
- ARMul_UndefInstr(state,instr) ;
- break ;
- }
- (void)StoreByte(state,instr,LHS - LSRegRHS) ;
- break ;
-
- case 0x75 : /* Load Byte, No WriteBack, Pre Dec, Reg */
- if (BIT(4)) {
- ARMul_UndefInstr(state,instr) ;
- break ;
- }
- (void)LoadByte(state,instr,LHS - LSRegRHS,LUNSIGNED) ;
- break ;
-
- case 0x76 : /* Store Byte, WriteBack, Pre Dec, Reg */
- if (BIT(4)) {
- ARMul_UndefInstr(state,instr) ;
- break ;
- }
- UNDEF_LSRBaseEQOffWb ;
- UNDEF_LSRBaseEQDestWb ;
- UNDEF_LSRPCBaseWb ;
- UNDEF_LSRPCOffWb ;
- temp = LHS - LSRegRHS ;
- if (StoreByte(state,instr,temp))
- LSBase = temp ;
- break ;
-
- case 0x77 : /* Load Byte, WriteBack, Pre Dec, Reg */
- if (BIT(4)) {
- ARMul_UndefInstr(state,instr) ;
- break ;
- }
- UNDEF_LSRBaseEQOffWb ;
- UNDEF_LSRBaseEQDestWb ;
- UNDEF_LSRPCBaseWb ;
- UNDEF_LSRPCOffWb ;
- temp = LHS - LSRegRHS ;
- if (LoadByte(state,instr,temp,LUNSIGNED))
- LSBase = temp ;
- break ;
-
- case 0x78 : /* Store Word, No WriteBack, Pre Inc, Reg */
- if (BIT(4)) {
- ARMul_UndefInstr(state,instr) ;
- break ;
- }
- (void)StoreWord(state,instr,LHS + LSRegRHS) ;
- break ;
-
- case 0x79 : /* Load Word, No WriteBack, Pre Inc, Reg */
- if (BIT(4)) {
- ARMul_UndefInstr(state,instr) ;
- break ;
- }
- (void)LoadWord(state,instr,LHS + LSRegRHS) ;
- break ;
-
- case 0x7a : /* Store Word, WriteBack, Pre Inc, Reg */
- if (BIT(4)) {
- ARMul_UndefInstr(state,instr) ;
- break ;
- }
- UNDEF_LSRBaseEQOffWb ;
- UNDEF_LSRBaseEQDestWb ;
- UNDEF_LSRPCBaseWb ;
- UNDEF_LSRPCOffWb ;
- temp = LHS + LSRegRHS ;
- if (StoreWord(state,instr,temp))
- LSBase = temp ;
- break ;
-
- case 0x7b : /* Load Word, WriteBack, Pre Inc, Reg */
- if (BIT(4)) {
- ARMul_UndefInstr(state,instr) ;
- break ;
- }
- UNDEF_LSRBaseEQOffWb ;
- UNDEF_LSRBaseEQDestWb ;
- UNDEF_LSRPCBaseWb ;
- UNDEF_LSRPCOffWb ;
- temp = LHS + LSRegRHS ;
- if (LoadWord(state,instr,temp))
- LSBase = temp ;
- break ;
-
- case 0x7c : /* Store Byte, No WriteBack, Pre Inc, Reg */
- if (BIT(4)) {
- ARMul_UndefInstr(state,instr) ;
- break ;
- }
- (void)StoreByte(state,instr,LHS + LSRegRHS) ;
- break ;
-
- case 0x7d : /* Load Byte, No WriteBack, Pre Inc, Reg */
- if (BIT(4)) {
- ARMul_UndefInstr(state,instr) ;
- break ;
- }
- (void)LoadByte(state,instr,LHS + LSRegRHS,LUNSIGNED) ;
- break ;
-
- case 0x7e : /* Store Byte, WriteBack, Pre Inc, Reg */
- if (BIT(4)) {
- ARMul_UndefInstr(state,instr) ;
- break ;
- }
- UNDEF_LSRBaseEQOffWb ;
- UNDEF_LSRBaseEQDestWb ;
- UNDEF_LSRPCBaseWb ;
- UNDEF_LSRPCOffWb ;
- temp = LHS + LSRegRHS ;
- if (StoreByte(state,instr,temp))
- LSBase = temp ;
- break ;
-
- case 0x7f : /* Load Byte, WriteBack, Pre Inc, Reg */
- if (BIT(4)) {
- ARMul_UndefInstr(state,instr) ;
- break ;
- }
- UNDEF_LSRBaseEQOffWb ;
- UNDEF_LSRBaseEQDestWb ;
- UNDEF_LSRPCBaseWb ;
- UNDEF_LSRPCOffWb ;
- temp = LHS + LSRegRHS ;
- if (LoadByte(state,instr,temp,LUNSIGNED))
- LSBase = temp ;
- break ;
+ case 0x60: /* Store Word, No WriteBack, Post Dec, Reg */
+ if (BIT (4))
+ {
+ ARMul_UndefInstr (state, instr);
+ break;
+ }
+ UNDEF_LSRBaseEQOffWb;
+ UNDEF_LSRBaseEQDestWb;
+ UNDEF_LSRPCBaseWb;
+ UNDEF_LSRPCOffWb;
+ lhs = LHS;
+ if (StoreWord (state, instr, lhs))
+ LSBase = lhs - LSRegRHS;
+ break;
+
+ case 0x61: /* Load Word, No WriteBack, Post Dec, Reg */
+ if (BIT (4))
+ {
+ ARMul_UndefInstr (state, instr);
+ break;
+ }
+ UNDEF_LSRBaseEQOffWb;
+ UNDEF_LSRBaseEQDestWb;
+ UNDEF_LSRPCBaseWb;
+ UNDEF_LSRPCOffWb;
+ lhs = LHS;
+ if (LoadWord (state, instr, lhs))
+ LSBase = lhs - LSRegRHS;
+ break;
+
+ case 0x62: /* Store Word, WriteBack, Post Dec, Reg */
+ if (BIT (4))
+ {
+ ARMul_UndefInstr (state, instr);
+ break;
+ }
+ UNDEF_LSRBaseEQOffWb;
+ UNDEF_LSRBaseEQDestWb;
+ UNDEF_LSRPCBaseWb;
+ UNDEF_LSRPCOffWb;
+ lhs = LHS;
+ state->NtransSig = LOW;
+ if (StoreWord (state, instr, lhs))
+ LSBase = lhs - LSRegRHS;
+ state->NtransSig = (state->Mode & 3) ? HIGH : LOW;
+ break;
+
+ case 0x63: /* Load Word, WriteBack, Post Dec, Reg */
+ if (BIT (4))
+ {
+ ARMul_UndefInstr (state, instr);
+ break;
+ }
+ UNDEF_LSRBaseEQOffWb;
+ UNDEF_LSRBaseEQDestWb;
+ UNDEF_LSRPCBaseWb;
+ UNDEF_LSRPCOffWb;
+ lhs = LHS;
+ state->NtransSig = LOW;
+ if (LoadWord (state, instr, lhs))
+ LSBase = lhs - LSRegRHS;
+ state->NtransSig = (state->Mode & 3) ? HIGH : LOW;
+ break;
+
+ case 0x64: /* Store Byte, No WriteBack, Post Dec, Reg */
+ if (BIT (4))
+ {
+ ARMul_UndefInstr (state, instr);
+ break;
+ }
+ UNDEF_LSRBaseEQOffWb;
+ UNDEF_LSRBaseEQDestWb;
+ UNDEF_LSRPCBaseWb;
+ UNDEF_LSRPCOffWb;
+ lhs = LHS;
+ if (StoreByte (state, instr, lhs))
+ LSBase = lhs - LSRegRHS;
+ break;
+
+ case 0x65: /* Load Byte, No WriteBack, Post Dec, Reg */
+ if (BIT (4))
+ {
+ ARMul_UndefInstr (state, instr);
+ break;
+ }
+ UNDEF_LSRBaseEQOffWb;
+ UNDEF_LSRBaseEQDestWb;
+ UNDEF_LSRPCBaseWb;
+ UNDEF_LSRPCOffWb;
+ lhs = LHS;
+ if (LoadByte (state, instr, lhs, LUNSIGNED))
+ LSBase = lhs - LSRegRHS;
+ break;
+
+ case 0x66: /* Store Byte, WriteBack, Post Dec, Reg */
+ if (BIT (4))
+ {
+ ARMul_UndefInstr (state, instr);
+ break;
+ }
+ UNDEF_LSRBaseEQOffWb;
+ UNDEF_LSRBaseEQDestWb;
+ UNDEF_LSRPCBaseWb;
+ UNDEF_LSRPCOffWb;
+ lhs = LHS;
+ state->NtransSig = LOW;
+ if (StoreByte (state, instr, lhs))
+ LSBase = lhs - LSRegRHS;
+ state->NtransSig = (state->Mode & 3) ? HIGH : LOW;
+ break;
+
+ case 0x67: /* Load Byte, WriteBack, Post Dec, Reg */
+ if (BIT (4))
+ {
+ ARMul_UndefInstr (state, instr);
+ break;
+ }
+ UNDEF_LSRBaseEQOffWb;
+ UNDEF_LSRBaseEQDestWb;
+ UNDEF_LSRPCBaseWb;
+ UNDEF_LSRPCOffWb;
+ lhs = LHS;
+ state->NtransSig = LOW;
+ if (LoadByte (state, instr, lhs, LUNSIGNED))
+ LSBase = lhs - LSRegRHS;
+ state->NtransSig = (state->Mode & 3) ? HIGH : LOW;
+ break;
+
+ case 0x68: /* Store Word, No WriteBack, Post Inc, Reg */
+ if (BIT (4))
+ {
+ ARMul_UndefInstr (state, instr);
+ break;
+ }
+ UNDEF_LSRBaseEQOffWb;
+ UNDEF_LSRBaseEQDestWb;
+ UNDEF_LSRPCBaseWb;
+ UNDEF_LSRPCOffWb;
+ lhs = LHS;
+ if (StoreWord (state, instr, lhs))
+ LSBase = lhs + LSRegRHS;
+ break;
+
+ case 0x69: /* Load Word, No WriteBack, Post Inc, Reg */
+ if (BIT (4))
+ {
+ ARMul_UndefInstr (state, instr);
+ break;
+ }
+ UNDEF_LSRBaseEQOffWb;
+ UNDEF_LSRBaseEQDestWb;
+ UNDEF_LSRPCBaseWb;
+ UNDEF_LSRPCOffWb;
+ lhs = LHS;
+ if (LoadWord (state, instr, lhs))
+ LSBase = lhs + LSRegRHS;
+ break;
+
+ case 0x6a: /* Store Word, WriteBack, Post Inc, Reg */
+ if (BIT (4))
+ {
+ ARMul_UndefInstr (state, instr);
+ break;
+ }
+ UNDEF_LSRBaseEQOffWb;
+ UNDEF_LSRBaseEQDestWb;
+ UNDEF_LSRPCBaseWb;
+ UNDEF_LSRPCOffWb;
+ lhs = LHS;
+ state->NtransSig = LOW;
+ if (StoreWord (state, instr, lhs))
+ LSBase = lhs + LSRegRHS;
+ state->NtransSig = (state->Mode & 3) ? HIGH : LOW;
+ break;
+
+ case 0x6b: /* Load Word, WriteBack, Post Inc, Reg */
+ if (BIT (4))
+ {
+ ARMul_UndefInstr (state, instr);
+ break;
+ }
+ UNDEF_LSRBaseEQOffWb;
+ UNDEF_LSRBaseEQDestWb;
+ UNDEF_LSRPCBaseWb;
+ UNDEF_LSRPCOffWb;
+ lhs = LHS;
+ state->NtransSig = LOW;
+ if (LoadWord (state, instr, lhs))
+ LSBase = lhs + LSRegRHS;
+ state->NtransSig = (state->Mode & 3) ? HIGH : LOW;
+ break;
+
+ case 0x6c: /* Store Byte, No WriteBack, Post Inc, Reg */
+ if (BIT (4))
+ {
+ ARMul_UndefInstr (state, instr);
+ break;
+ }
+ UNDEF_LSRBaseEQOffWb;
+ UNDEF_LSRBaseEQDestWb;
+ UNDEF_LSRPCBaseWb;
+ UNDEF_LSRPCOffWb;
+ lhs = LHS;
+ if (StoreByte (state, instr, lhs))
+ LSBase = lhs + LSRegRHS;
+ break;
+
+ case 0x6d: /* Load Byte, No WriteBack, Post Inc, Reg */
+ if (BIT (4))
+ {
+ ARMul_UndefInstr (state, instr);
+ break;
+ }
+ UNDEF_LSRBaseEQOffWb;
+ UNDEF_LSRBaseEQDestWb;
+ UNDEF_LSRPCBaseWb;
+ UNDEF_LSRPCOffWb;
+ lhs = LHS;
+ if (LoadByte (state, instr, lhs, LUNSIGNED))
+ LSBase = lhs + LSRegRHS;
+ break;
+
+ case 0x6e: /* Store Byte, WriteBack, Post Inc, Reg */
+ if (BIT (4))
+ {
+ ARMul_UndefInstr (state, instr);
+ break;
+ }
+ UNDEF_LSRBaseEQOffWb;
+ UNDEF_LSRBaseEQDestWb;
+ UNDEF_LSRPCBaseWb;
+ UNDEF_LSRPCOffWb;
+ lhs = LHS;
+ state->NtransSig = LOW;
+ if (StoreByte (state, instr, lhs))
+ LSBase = lhs + LSRegRHS;
+ state->NtransSig = (state->Mode & 3) ? HIGH : LOW;
+ break;
+
+ case 0x6f: /* Load Byte, WriteBack, Post Inc, Reg */
+ if (BIT (4))
+ {
+ ARMul_UndefInstr (state, instr);
+ break;
+ }
+ UNDEF_LSRBaseEQOffWb;
+ UNDEF_LSRBaseEQDestWb;
+ UNDEF_LSRPCBaseWb;
+ UNDEF_LSRPCOffWb;
+ lhs = LHS;
+ state->NtransSig = LOW;
+ if (LoadByte (state, instr, lhs, LUNSIGNED))
+ LSBase = lhs + LSRegRHS;
+ state->NtransSig = (state->Mode & 3) ? HIGH : LOW;
+ break;
+
+
+ case 0x70: /* Store Word, No WriteBack, Pre Dec, Reg */
+ if (BIT (4))
+ {
+ ARMul_UndefInstr (state, instr);
+ break;
+ }
+ (void) StoreWord (state, instr, LHS - LSRegRHS);
+ break;
+
+ case 0x71: /* Load Word, No WriteBack, Pre Dec, Reg */
+ if (BIT (4))
+ {
+ ARMul_UndefInstr (state, instr);
+ break;
+ }
+ (void) LoadWord (state, instr, LHS - LSRegRHS);
+ break;
+
+ case 0x72: /* Store Word, WriteBack, Pre Dec, Reg */
+ if (BIT (4))
+ {
+ ARMul_UndefInstr (state, instr);
+ break;
+ }
+ UNDEF_LSRBaseEQOffWb;
+ UNDEF_LSRBaseEQDestWb;
+ UNDEF_LSRPCBaseWb;
+ UNDEF_LSRPCOffWb;
+ temp = LHS - LSRegRHS;
+ if (StoreWord (state, instr, temp))
+ LSBase = temp;
+ break;
+
+ case 0x73: /* Load Word, WriteBack, Pre Dec, Reg */
+ if (BIT (4))
+ {
+ ARMul_UndefInstr (state, instr);
+ break;
+ }
+ UNDEF_LSRBaseEQOffWb;
+ UNDEF_LSRBaseEQDestWb;
+ UNDEF_LSRPCBaseWb;
+ UNDEF_LSRPCOffWb;
+ temp = LHS - LSRegRHS;
+ if (LoadWord (state, instr, temp))
+ LSBase = temp;
+ break;
+
+ case 0x74: /* Store Byte, No WriteBack, Pre Dec, Reg */
+ if (BIT (4))
+ {
+ ARMul_UndefInstr (state, instr);
+ break;
+ }
+ (void) StoreByte (state, instr, LHS - LSRegRHS);
+ break;
+
+ case 0x75: /* Load Byte, No WriteBack, Pre Dec, Reg */
+ if (BIT (4))
+ {
+ ARMul_UndefInstr (state, instr);
+ break;
+ }
+ (void) LoadByte (state, instr, LHS - LSRegRHS, LUNSIGNED);
+ break;
+
+ case 0x76: /* Store Byte, WriteBack, Pre Dec, Reg */
+ if (BIT (4))
+ {
+ ARMul_UndefInstr (state, instr);
+ break;
+ }
+ UNDEF_LSRBaseEQOffWb;
+ UNDEF_LSRBaseEQDestWb;
+ UNDEF_LSRPCBaseWb;
+ UNDEF_LSRPCOffWb;
+ temp = LHS - LSRegRHS;
+ if (StoreByte (state, instr, temp))
+ LSBase = temp;
+ break;
+
+ case 0x77: /* Load Byte, WriteBack, Pre Dec, Reg */
+ if (BIT (4))
+ {
+ ARMul_UndefInstr (state, instr);
+ break;
+ }
+ UNDEF_LSRBaseEQOffWb;
+ UNDEF_LSRBaseEQDestWb;
+ UNDEF_LSRPCBaseWb;
+ UNDEF_LSRPCOffWb;
+ temp = LHS - LSRegRHS;
+ if (LoadByte (state, instr, temp, LUNSIGNED))
+ LSBase = temp;
+ break;
+
+ case 0x78: /* Store Word, No WriteBack, Pre Inc, Reg */
+ if (BIT (4))
+ {
+ ARMul_UndefInstr (state, instr);
+ break;
+ }
+ (void) StoreWord (state, instr, LHS + LSRegRHS);
+ break;
+
+ case 0x79: /* Load Word, No WriteBack, Pre Inc, Reg */
+ if (BIT (4))
+ {
+ ARMul_UndefInstr (state, instr);
+ break;
+ }
+ (void) LoadWord (state, instr, LHS + LSRegRHS);
+ break;
+
+ case 0x7a: /* Store Word, WriteBack, Pre Inc, Reg */
+ if (BIT (4))
+ {
+ ARMul_UndefInstr (state, instr);
+ break;
+ }
+ UNDEF_LSRBaseEQOffWb;
+ UNDEF_LSRBaseEQDestWb;
+ UNDEF_LSRPCBaseWb;
+ UNDEF_LSRPCOffWb;
+ temp = LHS + LSRegRHS;
+ if (StoreWord (state, instr, temp))
+ LSBase = temp;
+ break;
+
+ case 0x7b: /* Load Word, WriteBack, Pre Inc, Reg */
+ if (BIT (4))
+ {
+ ARMul_UndefInstr (state, instr);
+ break;
+ }
+ UNDEF_LSRBaseEQOffWb;
+ UNDEF_LSRBaseEQDestWb;
+ UNDEF_LSRPCBaseWb;
+ UNDEF_LSRPCOffWb;
+ temp = LHS + LSRegRHS;
+ if (LoadWord (state, instr, temp))
+ LSBase = temp;
+ break;
+
+ case 0x7c: /* Store Byte, No WriteBack, Pre Inc, Reg */
+ if (BIT (4))
+ {
+ ARMul_UndefInstr (state, instr);
+ break;
+ }
+ (void) StoreByte (state, instr, LHS + LSRegRHS);
+ break;
+
+ case 0x7d: /* Load Byte, No WriteBack, Pre Inc, Reg */
+ if (BIT (4))
+ {
+ ARMul_UndefInstr (state, instr);
+ break;
+ }
+ (void) LoadByte (state, instr, LHS + LSRegRHS, LUNSIGNED);
+ break;
+
+ case 0x7e: /* Store Byte, WriteBack, Pre Inc, Reg */
+ if (BIT (4))
+ {
+ ARMul_UndefInstr (state, instr);
+ break;
+ }
+ UNDEF_LSRBaseEQOffWb;
+ UNDEF_LSRBaseEQDestWb;
+ UNDEF_LSRPCBaseWb;
+ UNDEF_LSRPCOffWb;
+ temp = LHS + LSRegRHS;
+ if (StoreByte (state, instr, temp))
+ LSBase = temp;
+ break;
+
+ case 0x7f: /* Load Byte, WriteBack, Pre Inc, Reg */
+ if (BIT (4))
+ {
+ /* Check for the special breakpoint opcode.
+ This value should correspond to the value defined
+ as ARM_BE_BREAKPOINT in gdb/arm-tdep.c. */
+ if (BITS (0, 19) == 0xfdefe)
+ {
+ if (!ARMul_OSHandleSWI (state, SWI_Breakpoint))
+ ARMul_Abort (state, ARMul_SWIV);
+ }
+ else
+ ARMul_UndefInstr (state, instr);
+ break;
+ }
+ UNDEF_LSRBaseEQOffWb;
+ UNDEF_LSRBaseEQDestWb;
+ UNDEF_LSRPCBaseWb;
+ UNDEF_LSRPCOffWb;
+ temp = LHS + LSRegRHS;
+ if (LoadByte (state, instr, temp, LUNSIGNED))
+ LSBase = temp;
+ break;
/***************************************************************************\
* Multiple Data Transfer Instructions *
\***************************************************************************/
- case 0x80 : /* Store, No WriteBack, Post Dec */
- STOREMULT(instr,LSBase - LSMNumRegs + 4L,0L) ;
- break ;
-
- case 0x81 : /* Load, No WriteBack, Post Dec */
- LOADMULT(instr,LSBase - LSMNumRegs + 4L,0L) ;
- break ;
-
- case 0x82 : /* Store, WriteBack, Post Dec */
- temp = LSBase - LSMNumRegs ;
- STOREMULT(instr,temp + 4L,temp) ;
- break ;
+ case 0x80: /* Store, No WriteBack, Post Dec */
+ STOREMULT (instr, LSBase - LSMNumRegs + 4L, 0L);
+ break;
+
+ case 0x81: /* Load, No WriteBack, Post Dec */
+ LOADMULT (instr, LSBase - LSMNumRegs + 4L, 0L);
+ break;
+
+ case 0x82: /* Store, WriteBack, Post Dec */
+ temp = LSBase - LSMNumRegs;
+ STOREMULT (instr, temp + 4L, temp);
+ break;
- case 0x83 : /* Load, WriteBack, Post Dec */
- temp = LSBase - LSMNumRegs ;
- LOADMULT(instr,temp + 4L,temp) ;
- break ;
+ case 0x83: /* Load, WriteBack, Post Dec */
+ temp = LSBase - LSMNumRegs;
+ LOADMULT (instr, temp + 4L, temp);
+ break;
- case 0x84 : /* Store, Flags, No WriteBack, Post Dec */
- STORESMULT(instr,LSBase - LSMNumRegs + 4L,0L) ;
- break ;
+ case 0x84: /* Store, Flags, No WriteBack, Post Dec */
+ STORESMULT (instr, LSBase - LSMNumRegs + 4L, 0L);
+ break;
- case 0x85 : /* Load, Flags, No WriteBack, Post Dec */
- LOADSMULT(instr,LSBase - LSMNumRegs + 4L,0L) ;
- break ;
-
- case 0x86 : /* Store, Flags, WriteBack, Post Dec */
- temp = LSBase - LSMNumRegs ;
- STORESMULT(instr,temp + 4L,temp) ;
- break ;
-
- case 0x87 : /* Load, Flags, WriteBack, Post Dec */
- temp = LSBase - LSMNumRegs ;
- LOADSMULT(instr,temp + 4L,temp) ;
- break ;
+ case 0x85: /* Load, Flags, No WriteBack, Post Dec */
+ LOADSMULT (instr, LSBase - LSMNumRegs + 4L, 0L);
+ break;
+
+ case 0x86: /* Store, Flags, WriteBack, Post Dec */
+ temp = LSBase - LSMNumRegs;
+ STORESMULT (instr, temp + 4L, temp);
+ break;
+
+ case 0x87: /* Load, Flags, WriteBack, Post Dec */
+ temp = LSBase - LSMNumRegs;
+ LOADSMULT (instr, temp + 4L, temp);
+ break;
- case 0x88 : /* Store, No WriteBack, Post Inc */
- STOREMULT(instr,LSBase,0L) ;
- break ;
-
- case 0x89 : /* Load, No WriteBack, Post Inc */
- LOADMULT(instr,LSBase,0L) ;
- break ;
-
- case 0x8a : /* Store, WriteBack, Post Inc */
- temp = LSBase ;
- STOREMULT(instr,temp,temp + LSMNumRegs) ;
- break ;
-
- case 0x8b : /* Load, WriteBack, Post Inc */
- temp = LSBase ;
- LOADMULT(instr,temp,temp + LSMNumRegs) ;
- break ;
-
- case 0x8c : /* Store, Flags, No WriteBack, Post Inc */
- STORESMULT(instr,LSBase,0L) ;
- break ;
-
- case 0x8d : /* Load, Flags, No WriteBack, Post Inc */
- LOADSMULT(instr,LSBase,0L) ;
- break ;
-
- case 0x8e : /* Store, Flags, WriteBack, Post Inc */
- temp = LSBase ;
- STORESMULT(instr,temp,temp + LSMNumRegs) ;
- break ;
-
- case 0x8f : /* Load, Flags, WriteBack, Post Inc */
- temp = LSBase ;
- LOADSMULT(instr,temp,temp + LSMNumRegs) ;
- break ;
-
-
- case 0x90 : /* Store, No WriteBack, Pre Dec */
- STOREMULT(instr,LSBase - LSMNumRegs,0L) ;
- break ;
-
- case 0x91 : /* Load, No WriteBack, Pre Dec */
- LOADMULT(instr,LSBase - LSMNumRegs,0L) ;
- break ;
-
- case 0x92 : /* Store, WriteBack, Pre Dec */
- temp = LSBase - LSMNumRegs ;
- STOREMULT(instr,temp,temp) ;
- break ;
-
- case 0x93 : /* Load, WriteBack, Pre Dec */
- temp = LSBase - LSMNumRegs ;
- LOADMULT(instr,temp,temp) ;
- break ;
-
- case 0x94 : /* Store, Flags, No WriteBack, Pre Dec */
- STORESMULT(instr,LSBase - LSMNumRegs,0L) ;
- break ;
-
- case 0x95 : /* Load, Flags, No WriteBack, Pre Dec */
- LOADSMULT(instr,LSBase - LSMNumRegs,0L) ;
- break ;
-
- case 0x96 : /* Store, Flags, WriteBack, Pre Dec */
- temp = LSBase - LSMNumRegs ;
- STORESMULT(instr,temp,temp) ;
- break ;
-
- case 0x97 : /* Load, Flags, WriteBack, Pre Dec */
- temp = LSBase - LSMNumRegs ;
- LOADSMULT(instr,temp,temp) ;
- break ;
-
-
- case 0x98 : /* Store, No WriteBack, Pre Inc */
- STOREMULT(instr,LSBase + 4L,0L) ;
- break ;
-
- case 0x99 : /* Load, No WriteBack, Pre Inc */
- LOADMULT(instr,LSBase + 4L,0L) ;
- break ;
-
- case 0x9a : /* Store, WriteBack, Pre Inc */
- temp = LSBase ;
- STOREMULT(instr,temp + 4L,temp + LSMNumRegs) ;
- break ;
-
- case 0x9b : /* Load, WriteBack, Pre Inc */
- temp = LSBase ;
- LOADMULT(instr,temp + 4L,temp + LSMNumRegs) ;
- break ;
+ case 0x88: /* Store, No WriteBack, Post Inc */
+ STOREMULT (instr, LSBase, 0L);
+ break;
+
+ case 0x89: /* Load, No WriteBack, Post Inc */
+ LOADMULT (instr, LSBase, 0L);
+ break;
+
+ case 0x8a: /* Store, WriteBack, Post Inc */
+ temp = LSBase;
+ STOREMULT (instr, temp, temp + LSMNumRegs);
+ break;
+
+ case 0x8b: /* Load, WriteBack, Post Inc */
+ temp = LSBase;
+ LOADMULT (instr, temp, temp + LSMNumRegs);
+ break;
+
+ case 0x8c: /* Store, Flags, No WriteBack, Post Inc */
+ STORESMULT (instr, LSBase, 0L);
+ break;
+
+ case 0x8d: /* Load, Flags, No WriteBack, Post Inc */
+ LOADSMULT (instr, LSBase, 0L);
+ break;
+
+ case 0x8e: /* Store, Flags, WriteBack, Post Inc */
+ temp = LSBase;
+ STORESMULT (instr, temp, temp + LSMNumRegs);
+ break;
+
+ case 0x8f: /* Load, Flags, WriteBack, Post Inc */
+ temp = LSBase;
+ LOADSMULT (instr, temp, temp + LSMNumRegs);
+ break;
+
+
+ case 0x90: /* Store, No WriteBack, Pre Dec */
+ STOREMULT (instr, LSBase - LSMNumRegs, 0L);
+ break;
+
+ case 0x91: /* Load, No WriteBack, Pre Dec */
+ LOADMULT (instr, LSBase - LSMNumRegs, 0L);
+ break;
+
+ case 0x92: /* Store, WriteBack, Pre Dec */
+ temp = LSBase - LSMNumRegs;
+ STOREMULT (instr, temp, temp);
+ break;
+
+ case 0x93: /* Load, WriteBack, Pre Dec */
+ temp = LSBase - LSMNumRegs;
+ LOADMULT (instr, temp, temp);
+ break;
+
+ case 0x94: /* Store, Flags, No WriteBack, Pre Dec */
+ STORESMULT (instr, LSBase - LSMNumRegs, 0L);
+ break;
+
+ case 0x95: /* Load, Flags, No WriteBack, Pre Dec */
+ LOADSMULT (instr, LSBase - LSMNumRegs, 0L);
+ break;
+
+ case 0x96: /* Store, Flags, WriteBack, Pre Dec */
+ temp = LSBase - LSMNumRegs;
+ STORESMULT (instr, temp, temp);
+ break;
+
+ case 0x97: /* Load, Flags, WriteBack, Pre Dec */
+ temp = LSBase - LSMNumRegs;
+ LOADSMULT (instr, temp, temp);
+ break;
+
+
+ case 0x98: /* Store, No WriteBack, Pre Inc */
+ STOREMULT (instr, LSBase + 4L, 0L);
+ break;
+
+ case 0x99: /* Load, No WriteBack, Pre Inc */
+ LOADMULT (instr, LSBase + 4L, 0L);
+ break;
+
+ case 0x9a: /* Store, WriteBack, Pre Inc */
+ temp = LSBase;
+ STOREMULT (instr, temp + 4L, temp + LSMNumRegs);
+ break;
+
+ case 0x9b: /* Load, WriteBack, Pre Inc */
+ temp = LSBase;
+ LOADMULT (instr, temp + 4L, temp + LSMNumRegs);
+ break;
- case 0x9c : /* Store, Flags, No WriteBack, Pre Inc */
- STORESMULT(instr,LSBase + 4L,0L) ;
- break ;
+ case 0x9c: /* Store, Flags, No WriteBack, Pre Inc */
+ STORESMULT (instr, LSBase + 4L, 0L);
+ break;
- case 0x9d : /* Load, Flags, No WriteBack, Pre Inc */
- LOADSMULT(instr,LSBase + 4L,0L) ;
- break ;
+ case 0x9d: /* Load, Flags, No WriteBack, Pre Inc */
+ LOADSMULT (instr, LSBase + 4L, 0L);
+ break;
- case 0x9e : /* Store, Flags, WriteBack, Pre Inc */
- temp = LSBase ;
- STORESMULT(instr,temp + 4L,temp + LSMNumRegs) ;
- break ;
-
- case 0x9f : /* Load, Flags, WriteBack, Pre Inc */
- temp = LSBase ;
- LOADSMULT(instr,temp + 4L,temp + LSMNumRegs) ;
- break ;
+ case 0x9e: /* Store, Flags, WriteBack, Pre Inc */
+ temp = LSBase;
+ STORESMULT (instr, temp + 4L, temp + LSMNumRegs);
+ break;
+
+ case 0x9f: /* Load, Flags, WriteBack, Pre Inc */
+ temp = LSBase;
+ LOADSMULT (instr, temp + 4L, temp + LSMNumRegs);
+ break;
/***************************************************************************\
* Branch forward *
\***************************************************************************/
- case 0xa0 : case 0xa1 : case 0xa2 : case 0xa3 :
- case 0xa4 : case 0xa5 : case 0xa6 : case 0xa7 :
- state->Reg[15] = pc + 8 + POSBRANCH ;
- FLUSHPIPE ;
- break ;
+ case 0xa0:
+ case 0xa1:
+ case 0xa2:
+ case 0xa3:
+ case 0xa4:
+ case 0xa5:
+ case 0xa6:
+ case 0xa7:
+ state->Reg[15] = pc + 8 + POSBRANCH;
+ FLUSHPIPE;
+ break;
/***************************************************************************\
* Branch backward *
\***************************************************************************/
- case 0xa8 : case 0xa9 : case 0xaa : case 0xab :
- case 0xac : case 0xad : case 0xae : case 0xaf :
- state->Reg[15] = pc + 8 + NEGBRANCH ;
- FLUSHPIPE ;
- break ;
+ case 0xa8:
+ case 0xa9:
+ case 0xaa:
+ case 0xab:
+ case 0xac:
+ case 0xad:
+ case 0xae:
+ case 0xaf:
+ state->Reg[15] = pc + 8 + NEGBRANCH;
+ FLUSHPIPE;
+ break;
/***************************************************************************\
* Branch and Link forward *
\***************************************************************************/
- case 0xb0 : case 0xb1 : case 0xb2 : case 0xb3 :
- case 0xb4 : case 0xb5 : case 0xb6 : case 0xb7 :
+ case 0xb0:
+ case 0xb1:
+ case 0xb2:
+ case 0xb3:
+ case 0xb4:
+ case 0xb5:
+ case 0xb6:
+ case 0xb7:
#ifdef MODE32
- state->Reg[14] = pc + 4 ; /* put PC into Link */
+ state->Reg[14] = pc + 4; /* put PC into Link */
#else
- state->Reg[14] = pc + 4 | ECC | ER15INT | EMODE ; /* put PC into Link */
+ state->Reg[14] = (pc + 4) | ECC | ER15INT | EMODE; /* put PC into Link */
#endif
- state->Reg[15] = pc + 8 + POSBRANCH ;
- FLUSHPIPE ;
- break ;
+ state->Reg[15] = pc + 8 + POSBRANCH;
+ FLUSHPIPE;
+ break;
/***************************************************************************\
* Branch and Link backward *
\***************************************************************************/
- case 0xb8 : case 0xb9 : case 0xba : case 0xbb :
- case 0xbc : case 0xbd : case 0xbe : case 0xbf :
+ case 0xb8:
+ case 0xb9:
+ case 0xba:
+ case 0xbb:
+ case 0xbc:
+ case 0xbd:
+ case 0xbe:
+ case 0xbf:
#ifdef MODE32
- state->Reg[14] = pc + 4 ; /* put PC into Link */
+ state->Reg[14] = pc + 4; /* put PC into Link */
#else
- state->Reg[14] = (pc + 4) | ECC | ER15INT | EMODE ; /* put PC into Link */
+ state->Reg[14] = (pc + 4) | ECC | ER15INT | EMODE; /* put PC into Link */
#endif
- state->Reg[15] = pc + 8 + NEGBRANCH ;
- FLUSHPIPE ;
- break ;
+ state->Reg[15] = pc + 8 + NEGBRANCH;
+ FLUSHPIPE;
+ break;
/***************************************************************************\
* Co-Processor Data Transfers *
\***************************************************************************/
- case 0xc0 :
- case 0xc4 : /* Store , No WriteBack , Post Dec */
- ARMul_STC(state,instr,LHS) ;
- break ;
-
- case 0xc1 :
- case 0xc5 : /* Load , No WriteBack , Post Dec */
- ARMul_LDC(state,instr,LHS) ;
- break ;
-
- case 0xc2 :
- case 0xc6 : /* Store , WriteBack , Post Dec */
- lhs = LHS ;
- state->Base = lhs - LSCOff ;
- ARMul_STC(state,instr,lhs) ;
- break ;
-
- case 0xc3 :
- case 0xc7 : /* Load , WriteBack , Post Dec */
- lhs = LHS ;
- state->Base = lhs - LSCOff ;
- ARMul_LDC(state,instr,lhs) ;
- break ;
-
- case 0xc8 :
- case 0xcc : /* Store , No WriteBack , Post Inc */
- ARMul_STC(state,instr,LHS) ;
- break ;
-
- case 0xc9 :
- case 0xcd : /* Load , No WriteBack , Post Inc */
- ARMul_LDC(state,instr,LHS) ;
- break ;
-
- case 0xca :
- case 0xce : /* Store , WriteBack , Post Inc */
- lhs = LHS ;
- state->Base = lhs + LSCOff ;
- ARMul_STC(state,instr,LHS) ;
- break ;
-
- case 0xcb :
- case 0xcf : /* Load , WriteBack , Post Inc */
- lhs = LHS ;
- state->Base = lhs + LSCOff ;
- ARMul_LDC(state,instr,LHS) ;
- break ;
-
-
- case 0xd0 :
- case 0xd4 : /* Store , No WriteBack , Pre Dec */
- ARMul_STC(state,instr,LHS - LSCOff) ;
- break ;
-
- case 0xd1 :
- case 0xd5 : /* Load , No WriteBack , Pre Dec */
- ARMul_LDC(state,instr,LHS - LSCOff) ;
- break ;
-
- case 0xd2 :
- case 0xd6 : /* Store , WriteBack , Pre Dec */
- lhs = LHS - LSCOff ;
- state->Base = lhs ;
- ARMul_STC(state,instr,lhs) ;
- break ;
-
- case 0xd3 :
- case 0xd7 : /* Load , WriteBack , Pre Dec */
- lhs = LHS - LSCOff ;
- state->Base = lhs ;
- ARMul_LDC(state,instr,lhs) ;
- break ;
-
- case 0xd8 :
- case 0xdc : /* Store , No WriteBack , Pre Inc */
- ARMul_STC(state,instr,LHS + LSCOff) ;
- break ;
-
- case 0xd9 :
- case 0xdd : /* Load , No WriteBack , Pre Inc */
- ARMul_LDC(state,instr,LHS + LSCOff) ;
- break ;
-
- case 0xda :
- case 0xde : /* Store , WriteBack , Pre Inc */
- lhs = LHS + LSCOff ;
- state->Base = lhs ;
- ARMul_STC(state,instr,lhs) ;
- break ;
-
- case 0xdb :
- case 0xdf : /* Load , WriteBack , Pre Inc */
- lhs = LHS + LSCOff ;
- state->Base = lhs ;
- ARMul_LDC(state,instr,lhs) ;
- break ;
+ case 0xc4:
+ case 0xc0: /* Store , No WriteBack , Post Dec */
+ ARMul_STC (state, instr, LHS);
+ break;
+
+ case 0xc5:
+ case 0xc1: /* Load , No WriteBack , Post Dec */
+ ARMul_LDC (state, instr, LHS);
+ break;
+
+ case 0xc2:
+ case 0xc6: /* Store , WriteBack , Post Dec */
+ lhs = LHS;
+ state->Base = lhs - LSCOff;
+ ARMul_STC (state, instr, lhs);
+ break;
+
+ case 0xc3:
+ case 0xc7: /* Load , WriteBack , Post Dec */
+ lhs = LHS;
+ state->Base = lhs - LSCOff;
+ ARMul_LDC (state, instr, lhs);
+ break;
+
+ case 0xc8:
+ case 0xcc: /* Store , No WriteBack , Post Inc */
+ ARMul_STC (state, instr, LHS);
+ break;
+
+ case 0xc9:
+ case 0xcd: /* Load , No WriteBack , Post Inc */
+ ARMul_LDC (state, instr, LHS);
+ break;
+
+ case 0xca:
+ case 0xce: /* Store , WriteBack , Post Inc */
+ lhs = LHS;
+ state->Base = lhs + LSCOff;
+ ARMul_STC (state, instr, LHS);
+ break;
+
+ case 0xcb:
+ case 0xcf: /* Load , WriteBack , Post Inc */
+ lhs = LHS;
+ state->Base = lhs + LSCOff;
+ ARMul_LDC (state, instr, LHS);
+ break;
+
+
+ case 0xd0:
+ case 0xd4: /* Store , No WriteBack , Pre Dec */
+ ARMul_STC (state, instr, LHS - LSCOff);
+ break;
+
+ case 0xd1:
+ case 0xd5: /* Load , No WriteBack , Pre Dec */
+ ARMul_LDC (state, instr, LHS - LSCOff);
+ break;
+
+ case 0xd2:
+ case 0xd6: /* Store , WriteBack , Pre Dec */
+ lhs = LHS - LSCOff;
+ state->Base = lhs;
+ ARMul_STC (state, instr, lhs);
+ break;
+
+ case 0xd3:
+ case 0xd7: /* Load , WriteBack , Pre Dec */
+ lhs = LHS - LSCOff;
+ state->Base = lhs;
+ ARMul_LDC (state, instr, lhs);
+ break;
+
+ case 0xd8:
+ case 0xdc: /* Store , No WriteBack , Pre Inc */
+ ARMul_STC (state, instr, LHS + LSCOff);
+ break;
+
+ case 0xd9:
+ case 0xdd: /* Load , No WriteBack , Pre Inc */
+ ARMul_LDC (state, instr, LHS + LSCOff);
+ break;
+
+ case 0xda:
+ case 0xde: /* Store , WriteBack , Pre Inc */
+ lhs = LHS + LSCOff;
+ state->Base = lhs;
+ ARMul_STC (state, instr, lhs);
+ break;
+
+ case 0xdb:
+ case 0xdf: /* Load , WriteBack , Pre Inc */
+ lhs = LHS + LSCOff;
+ state->Base = lhs;
+ ARMul_LDC (state, instr, lhs);
+ break;
/***************************************************************************\
* Co-Processor Register Transfers (MCR) and Data Ops *
\***************************************************************************/
- case 0xe0 : case 0xe2 : case 0xe4 : case 0xe6 :
- case 0xe8 : case 0xea : case 0xec : case 0xee :
- if (BIT(4)) { /* MCR */
- if (DESTReg == 15) {
- UNDEF_MCRPC ;
+ case 0xe2:
+ case 0xe0:
+ case 0xe4:
+ case 0xe6:
+ case 0xe8:
+ case 0xea:
+ case 0xec:
+ case 0xee:
+ if (BIT (4))
+ { /* MCR */
+ if (DESTReg == 15)
+ {
+ UNDEF_MCRPC;
#ifdef MODE32
- ARMul_MCR(state,instr,state->Reg[15] + isize) ;
+ ARMul_MCR (state, instr, state->Reg[15] + isize);
#else
- ARMul_MCR(state,instr,ECC | ER15INT | EMODE |
- ((state->Reg[15] + isize) & R15PCBITS) ) ;
+ ARMul_MCR (state, instr, ECC | ER15INT | EMODE |
+ ((state->Reg[15] + isize) & R15PCBITS));
#endif
- }
- else
- ARMul_MCR(state,instr,DEST) ;
- }
- else /* CDP Part 1 */
- ARMul_CDP(state,instr) ;
- break ;
+ }
+ else
+ ARMul_MCR (state, instr, DEST);
+ }
+ else /* CDP Part 1 */
+ ARMul_CDP (state, instr);
+ break;
/***************************************************************************\
* Co-Processor Register Transfers (MRC) and Data Ops *
\***************************************************************************/
- case 0xe1 : case 0xe3 : case 0xe5 : case 0xe7 :
- case 0xe9 : case 0xeb : case 0xed : case 0xef :
- if (BIT(4)) { /* MRC */
- temp = ARMul_MRC(state,instr) ;
- if (DESTReg == 15) {
- ASSIGNN((temp & NBIT) != 0) ;
- ASSIGNZ((temp & ZBIT) != 0) ;
- ASSIGNC((temp & CBIT) != 0) ;
- ASSIGNV((temp & VBIT) != 0) ;
- }
- else
- DEST = temp ;
- }
- else /* CDP Part 2 */
- ARMul_CDP(state,instr) ;
- break ;
+ case 0xe1:
+ case 0xe3:
+ case 0xe5:
+ case 0xe7:
+ case 0xe9:
+ case 0xeb:
+ case 0xed:
+ case 0xef:
+ if (BIT (4))
+ { /* MRC */
+ temp = ARMul_MRC (state, instr);
+ if (DESTReg == 15)
+ {
+ ASSIGNN ((temp & NBIT) != 0);
+ ASSIGNZ ((temp & ZBIT) != 0);
+ ASSIGNC ((temp & CBIT) != 0);
+ ASSIGNV ((temp & VBIT) != 0);
+ }
+ else
+ DEST = temp;
+ }
+ else /* CDP Part 2 */
+ ARMul_CDP (state, instr);
+ break;
/***************************************************************************\
* SWI instruction *
\***************************************************************************/
- case 0xf0 : case 0xf1 : case 0xf2 : case 0xf3 :
- case 0xf4 : case 0xf5 : case 0xf6 : case 0xf7 :
- case 0xf8 : case 0xf9 : case 0xfa : case 0xfb :
- case 0xfc : case 0xfd : case 0xfe : case 0xff :
- if (instr == ARMul_ABORTWORD && state->AbortAddr == pc) { /* a prefetch abort */
- ARMul_Abort(state,ARMul_PrefetchAbortV) ;
- break ;
- }
-
- if (!ARMul_OSHandleSWI(state,BITS(0,23))) {
- ARMul_Abort(state,ARMul_SWIV) ;
- }
- break ;
- } /* 256 way main switch */
- } /* if temp */
+ case 0xf0:
+ case 0xf1:
+ case 0xf2:
+ case 0xf3:
+ case 0xf4:
+ case 0xf5:
+ case 0xf6:
+ case 0xf7:
+ case 0xf8:
+ case 0xf9:
+ case 0xfa:
+ case 0xfb:
+ case 0xfc:
+ case 0xfd:
+ case 0xfe:
+ case 0xff:
+ if (instr == ARMul_ABORTWORD && state->AbortAddr == pc)
+ { /* a prefetch abort */
+ ARMul_Abort (state, ARMul_PrefetchAbortV);
+ break;
+ }
+
+ if (!ARMul_OSHandleSWI (state, BITS (0, 23)))
+ {
+ ARMul_Abort (state, ARMul_SWIV);
+ }
+ break;
+ } /* 256 way main switch */
+ } /* if temp */
#ifdef MODET
-donext:
+ donext:
#endif
- if (state->Emulate == ONCE)
- state->Emulate = STOP;
- else if (state->Emulate != RUN)
- break;
- } while (1) ; /* do loop */
+#ifdef NEED_UI_LOOP_HOOK
+ if (ui_loop_hook != NULL && ui_loop_hook_counter-- < 0)
+ {
+ ui_loop_hook_counter = UI_LOOP_POLL_INTERVAL;
+ ui_loop_hook (0);
+ }
+#endif /* NEED_UI_LOOP_HOOK */
+
+ if (state->Emulate == ONCE)
+ state->Emulate = STOP;
+ else if (state->Emulate != RUN)
+ break;
+ }
+ while (!stop_simulator); /* do loop */
- state->decoded = decoded ;
- state->loaded = loaded ;
- state->pc = pc ;
- return(pc) ;
- } /* Emulate 26/32 in instruction based mode */
+ state->decoded = decoded;
+ state->loaded = loaded;
+ state->pc = pc;
+ return (pc);
+} /* Emulate 26/32 in instruction based mode */
/***************************************************************************\
* filters the common case of an unshifted register with in line code *
\***************************************************************************/
-static ARMword GetDPRegRHS(ARMul_State *state, ARMword instr)
-{ARMword shamt , base ;
+static ARMword
+GetDPRegRHS (ARMul_State * state, ARMword instr)
+{
+ ARMword shamt, base;
- base = RHSReg ;
- if (BIT(4)) { /* shift amount in a register */
- UNDEF_Shift ;
- INCPC ;
+ base = RHSReg;
+ if (BIT (4))
+ { /* shift amount in a register */
+ UNDEF_Shift;
+ INCPC;
#ifndef MODE32
- if (base == 15)
- base = ECC | ER15INT | R15PC | EMODE ;
- else
-#endif
- base = state->Reg[base] ;
- ARMul_Icycles(state,1,0L) ;
- shamt = state->Reg[BITS(8,11)] & 0xff ;
- switch ((int)BITS(5,6)) {
- case LSL : if (shamt == 0)
- return(base) ;
- else if (shamt >= 32)
- return(0) ;
- else
- return(base << shamt) ;
- case LSR : if (shamt == 0)
- return(base) ;
- else if (shamt >= 32)
- return(0) ;
- else
- return(base >> shamt) ;
- case ASR : if (shamt == 0)
- return(base) ;
- else if (shamt >= 32)
- return((ARMword)((long int)base >> 31L)) ;
- else
- return((ARMword)((long int)base >> (int)shamt)) ;
- case ROR : shamt &= 0x1f ;
- if (shamt == 0)
- return(base) ;
- else
- return((base << (32 - shamt)) | (base >> shamt)) ;
- }
+ if (base == 15)
+ base = ECC | ER15INT | R15PC | EMODE;
+ else
+#endif
+ base = state->Reg[base];
+ ARMul_Icycles (state, 1, 0L);
+ shamt = state->Reg[BITS (8, 11)] & 0xff;
+ switch ((int) BITS (5, 6))
+ {
+ case LSL:
+ if (shamt == 0)
+ return (base);
+ else if (shamt >= 32)
+ return (0);
+ else
+ return (base << shamt);
+ case LSR:
+ if (shamt == 0)
+ return (base);
+ else if (shamt >= 32)
+ return (0);
+ else
+ return (base >> shamt);
+ case ASR:
+ if (shamt == 0)
+ return (base);
+ else if (shamt >= 32)
+ return ((ARMword) ((long int) base >> 31L));
+ else
+ return ((ARMword) ((long int) base >> (int) shamt));
+ case ROR:
+ shamt &= 0x1f;
+ if (shamt == 0)
+ return (base);
+ else
+ return ((base << (32 - shamt)) | (base >> shamt));
+ }
}
- else { /* shift amount is a constant */
+ else
+ { /* shift amount is a constant */
#ifndef MODE32
- if (base == 15)
- base = ECC | ER15INT | R15PC | EMODE ;
- else
-#endif
- base = state->Reg[base] ;
- shamt = BITS(7,11) ;
- switch ((int)BITS(5,6)) {
- case LSL : return(base<<shamt) ;
- case LSR : if (shamt == 0)
- return(0) ;
- else
- return(base >> shamt) ;
- case ASR : if (shamt == 0)
- return((ARMword)((long int)base >> 31L)) ;
- else
- return((ARMword)((long int)base >> (int)shamt)) ;
- case ROR : if (shamt==0) /* its an RRX */
- return((base >> 1) | (CFLAG << 31)) ;
- else
- return((base << (32 - shamt)) | (base >> shamt)) ;
- }
+ if (base == 15)
+ base = ECC | ER15INT | R15PC | EMODE;
+ else
+#endif
+ base = state->Reg[base];
+ shamt = BITS (7, 11);
+ switch ((int) BITS (5, 6))
+ {
+ case LSL:
+ return (base << shamt);
+ case LSR:
+ if (shamt == 0)
+ return (0);
+ else
+ return (base >> shamt);
+ case ASR:
+ if (shamt == 0)
+ return ((ARMword) ((long int) base >> 31L));
+ else
+ return ((ARMword) ((long int) base >> (int) shamt));
+ case ROR:
+ if (shamt == 0) /* its an RRX */
+ return ((base >> 1) | (CFLAG << 31));
+ else
+ return ((base << (32 - shamt)) | (base >> shamt));
+ }
}
- return(0) ; /* just to shut up lint */
- }
+ return (0); /* just to shut up lint */
+}
+
/***************************************************************************\
* This routine evaluates most Logical Data Processing register RHS's *
* with the S bit set. It is intended to be called from the macro *
* with in line code *
\***************************************************************************/
-static ARMword GetDPSRegRHS(ARMul_State *state, ARMword instr)
-{ARMword shamt , base ;
+static ARMword
+GetDPSRegRHS (ARMul_State * state, ARMword instr)
+{
+ ARMword shamt, base;
- base = RHSReg ;
- if (BIT(4)) { /* shift amount in a register */
- UNDEF_Shift ;
- INCPC ;
+ base = RHSReg;
+ if (BIT (4))
+ { /* shift amount in a register */
+ UNDEF_Shift;
+ INCPC;
#ifndef MODE32
- if (base == 15)
- base = ECC | ER15INT | R15PC | EMODE ;
- else
-#endif
- base = state->Reg[base] ;
- ARMul_Icycles(state,1,0L) ;
- shamt = state->Reg[BITS(8,11)] & 0xff ;
- switch ((int)BITS(5,6)) {
- case LSL : if (shamt == 0)
- return(base) ;
- else if (shamt == 32) {
- ASSIGNC(base & 1) ;
- return(0) ;
- }
- else if (shamt > 32) {
- CLEARC ;
- return(0) ;
- }
- else {
- ASSIGNC((base >> (32-shamt)) & 1) ;
- return(base << shamt) ;
- }
- case LSR : if (shamt == 0)
- return(base) ;
- else if (shamt == 32) {
- ASSIGNC(base >> 31) ;
- return(0) ;
- }
- else if (shamt > 32) {
- CLEARC ;
- return(0) ;
- }
- else {
- ASSIGNC((base >> (shamt - 1)) & 1) ;
- return(base >> shamt) ;
- }
- case ASR : if (shamt == 0)
- return(base) ;
- else if (shamt >= 32) {
- ASSIGNC(base >> 31L) ;
- return((ARMword)((long int)base >> 31L)) ;
- }
- else {
- ASSIGNC((ARMword)((long int)base >> (int)(shamt-1)) & 1) ;
- return((ARMword)((long int)base >> (int)shamt)) ;
- }
- case ROR : if (shamt == 0)
- return(base) ;
- shamt &= 0x1f ;
- if (shamt == 0) {
- ASSIGNC(base >> 31) ;
- return(base) ;
- }
- else {
- ASSIGNC((base >> (shamt-1)) & 1) ;
- return((base << (32-shamt)) | (base >> shamt)) ;
- }
- }
+ if (base == 15)
+ base = ECC | ER15INT | R15PC | EMODE;
+ else
+#endif
+ base = state->Reg[base];
+ ARMul_Icycles (state, 1, 0L);
+ shamt = state->Reg[BITS (8, 11)] & 0xff;
+ switch ((int) BITS (5, 6))
+ {
+ case LSL:
+ if (shamt == 0)
+ return (base);
+ else if (shamt == 32)
+ {
+ ASSIGNC (base & 1);
+ return (0);
+ }
+ else if (shamt > 32)
+ {
+ CLEARC;
+ return (0);
+ }
+ else
+ {
+ ASSIGNC ((base >> (32 - shamt)) & 1);
+ return (base << shamt);
+ }
+ case LSR:
+ if (shamt == 0)
+ return (base);
+ else if (shamt == 32)
+ {
+ ASSIGNC (base >> 31);
+ return (0);
+ }
+ else if (shamt > 32)
+ {
+ CLEARC;
+ return (0);
+ }
+ else
+ {
+ ASSIGNC ((base >> (shamt - 1)) & 1);
+ return (base >> shamt);
+ }
+ case ASR:
+ if (shamt == 0)
+ return (base);
+ else if (shamt >= 32)
+ {
+ ASSIGNC (base >> 31L);
+ return ((ARMword) ((long int) base >> 31L));
+ }
+ else
+ {
+ ASSIGNC ((ARMword) ((long int) base >> (int) (shamt - 1)) & 1);
+ return ((ARMword) ((long int) base >> (int) shamt));
+ }
+ case ROR:
+ if (shamt == 0)
+ return (base);
+ shamt &= 0x1f;
+ if (shamt == 0)
+ {
+ ASSIGNC (base >> 31);
+ return (base);
+ }
+ else
+ {
+ ASSIGNC ((base >> (shamt - 1)) & 1);
+ return ((base << (32 - shamt)) | (base >> shamt));
+ }
+ }
}
- else { /* shift amount is a constant */
+ else
+ { /* shift amount is a constant */
#ifndef MODE32
- if (base == 15)
- base = ECC | ER15INT | R15PC | EMODE ;
- else
-#endif
- base = state->Reg[base] ;
- shamt = BITS(7,11) ;
- switch ((int)BITS(5,6)) {
- case LSL : ASSIGNC((base >> (32-shamt)) & 1) ;
- return(base << shamt) ;
- case LSR : if (shamt == 0) {
- ASSIGNC(base >> 31) ;
- return(0) ;
- }
- else {
- ASSIGNC((base >> (shamt - 1)) & 1) ;
- return(base >> shamt) ;
- }
- case ASR : if (shamt == 0) {
- ASSIGNC(base >> 31L) ;
- return((ARMword)((long int)base >> 31L)) ;
- }
- else {
- ASSIGNC((ARMword)((long int)base >> (int)(shamt-1)) & 1) ;
- return((ARMword)((long int)base >> (int)shamt)) ;
- }
- case ROR : if (shamt == 0) { /* its an RRX */
- shamt = CFLAG ;
- ASSIGNC(base & 1) ;
- return((base >> 1) | (shamt << 31)) ;
- }
- else {
- ASSIGNC((base >> (shamt - 1)) & 1) ;
- return((base << (32-shamt)) | (base >> shamt)) ;
- }
- }
+ if (base == 15)
+ base = ECC | ER15INT | R15PC | EMODE;
+ else
+#endif
+ base = state->Reg[base];
+ shamt = BITS (7, 11);
+ switch ((int) BITS (5, 6))
+ {
+ case LSL:
+ ASSIGNC ((base >> (32 - shamt)) & 1);
+ return (base << shamt);
+ case LSR:
+ if (shamt == 0)
+ {
+ ASSIGNC (base >> 31);
+ return (0);
+ }
+ else
+ {
+ ASSIGNC ((base >> (shamt - 1)) & 1);
+ return (base >> shamt);
+ }
+ case ASR:
+ if (shamt == 0)
+ {
+ ASSIGNC (base >> 31L);
+ return ((ARMword) ((long int) base >> 31L));
+ }
+ else
+ {
+ ASSIGNC ((ARMword) ((long int) base >> (int) (shamt - 1)) & 1);
+ return ((ARMword) ((long int) base >> (int) shamt));
+ }
+ case ROR:
+ if (shamt == 0)
+ { /* its an RRX */
+ shamt = CFLAG;
+ ASSIGNC (base & 1);
+ return ((base >> 1) | (shamt << 31));
+ }
+ else
+ {
+ ASSIGNC ((base >> (shamt - 1)) & 1);
+ return ((base << (32 - shamt)) | (base >> shamt));
+ }
+ }
}
- return(0) ; /* just to shut up lint */
- }
+ return (0); /* just to shut up lint */
+}
/***************************************************************************\
* This routine handles writes to register 15 when the S bit is not set. *
\***************************************************************************/
-static void WriteR15(ARMul_State *state, ARMword src)
+static void
+WriteR15 (ARMul_State * state, ARMword src)
{
/* The ARM documentation implies (but doe snot state) that the bottom bit of the PC is never set */
#ifdef MODE32
- state->Reg[15] = src & PCBITS & ~ 0x1 ;
+ state->Reg[15] = src & PCBITS & ~0x1;
#else
- state->Reg[15] = (src & R15PCBITS & ~ 0x1) | ECC | ER15INT | EMODE ;
- ARMul_R15Altered(state) ;
+ state->Reg[15] = (src & R15PCBITS & ~0x1) | ECC | ER15INT | EMODE;
+ ARMul_R15Altered (state);
#endif
- FLUSHPIPE ;
- }
+ FLUSHPIPE;
+}
/***************************************************************************\
* This routine handles writes to register 15 when the S bit is set. *
\***************************************************************************/
-static void WriteSR15(ARMul_State *state, ARMword src)
+static void
+WriteSR15 (ARMul_State * state, ARMword src)
{
#ifdef MODE32
- state->Reg[15] = src & PCBITS ;
- if (state->Bank > 0) {
- state->Cpsr = state->Spsr[state->Bank] ;
- ARMul_CPSRAltered(state) ;
+ state->Reg[15] = src & PCBITS;
+ if (state->Bank > 0)
+ {
+ state->Cpsr = state->Spsr[state->Bank];
+ ARMul_CPSRAltered (state);
}
#else
- if (state->Bank == USERBANK)
- state->Reg[15] = (src & (CCBITS | R15PCBITS)) | ER15INT | EMODE ;
- else
- state->Reg[15] = src ;
- ARMul_R15Altered(state) ;
+ if (state->Bank == USERBANK)
+ state->Reg[15] = (src & (CCBITS | R15PCBITS)) | ER15INT | EMODE;
+ else
+ state->Reg[15] = src;
+ ARMul_R15Altered (state);
#endif
- FLUSHPIPE ;
- }
+ FLUSHPIPE;
+}
/***************************************************************************\
* This routine evaluates most Load and Store register RHS's. It is *
* common case of an unshifted register with in line code *
\***************************************************************************/
-static ARMword GetLSRegRHS(ARMul_State *state, ARMword instr)
-{ARMword shamt, base ;
+static ARMword
+GetLSRegRHS (ARMul_State * state, ARMword instr)
+{
+ ARMword shamt, base;
- base = RHSReg ;
+ base = RHSReg;
#ifndef MODE32
- if (base == 15)
- base = ECC | ER15INT | R15PC | EMODE ; /* Now forbidden, but .... */
- else
-#endif
- base = state->Reg[base] ;
-
- shamt = BITS(7,11) ;
- switch ((int)BITS(5,6)) {
- case LSL : return(base << shamt) ;
- case LSR : if (shamt == 0)
- return(0) ;
- else
- return(base >> shamt) ;
- case ASR : if (shamt == 0)
- return((ARMword)((long int)base >> 31L)) ;
- else
- return((ARMword)((long int)base >> (int)shamt)) ;
- case ROR : if (shamt==0) /* its an RRX */
- return((base >> 1) | (CFLAG << 31)) ;
- else
- return((base << (32-shamt)) | (base >> shamt)) ;
+ if (base == 15)
+ base = ECC | ER15INT | R15PC | EMODE; /* Now forbidden, but .... */
+ else
+#endif
+ base = state->Reg[base];
+
+ shamt = BITS (7, 11);
+ switch ((int) BITS (5, 6))
+ {
+ case LSL:
+ return (base << shamt);
+ case LSR:
+ if (shamt == 0)
+ return (0);
+ else
+ return (base >> shamt);
+ case ASR:
+ if (shamt == 0)
+ return ((ARMword) ((long int) base >> 31L));
+ else
+ return ((ARMword) ((long int) base >> (int) shamt));
+ case ROR:
+ if (shamt == 0) /* its an RRX */
+ return ((base >> 1) | (CFLAG << 31));
+ else
+ return ((base << (32 - shamt)) | (base >> shamt));
}
- return(0) ; /* just to shut up lint */
- }
+ return (0); /* just to shut up lint */
+}
/***************************************************************************\
* This routine evaluates the ARM7T halfword and signed transfer RHS's. *
\***************************************************************************/
-static ARMword GetLS7RHS(ARMul_State *state, ARMword instr)
+static ARMword
+GetLS7RHS (ARMul_State * state, ARMword instr)
{
- if (BIT(22) == 0) { /* register */
+ if (BIT (22) == 0)
+ { /* register */
#ifndef MODE32
- if (RHSReg == 15)
- return ECC | ER15INT | R15PC | EMODE ; /* Now forbidden, but ... */
+ if (RHSReg == 15)
+ return ECC | ER15INT | R15PC | EMODE; /* Now forbidden, but ... */
#endif
- return state->Reg[RHSReg] ;
+ return state->Reg[RHSReg];
}
- /* else immediate */
- return BITS(0,3) | (BITS(8,11) << 4) ;
- }
+ /* else immediate */
+ return BITS (0, 3) | (BITS (8, 11) << 4);
+}
/***************************************************************************\
* This function does the work of loading a word for a LDR instruction. *
\***************************************************************************/
-static unsigned LoadWord(ARMul_State *state, ARMword instr, ARMword address)
+static unsigned
+LoadWord (ARMul_State * state, ARMword instr, ARMword address)
{
- ARMword dest ;
+ ARMword dest;
- BUSUSEDINCPCS ;
+ BUSUSEDINCPCS;
#ifndef MODE32
- if (ADDREXCEPT(address)) {
- INTERNALABORT(address) ;
+ if (ADDREXCEPT (address))
+ {
+ INTERNALABORT (address);
}
#endif
- dest = ARMul_LoadWordN(state,address) ;
- if (state->Aborted) {
- TAKEABORT ;
- return(state->lateabtSig) ;
+ dest = ARMul_LoadWordN (state, address);
+ if (state->Aborted)
+ {
+ TAKEABORT;
+ return (state->lateabtSig);
}
- if (address & 3)
- dest = ARMul_Align(state,address,dest) ;
- WRITEDEST(dest) ;
- ARMul_Icycles(state,1,0L) ;
+ if (address & 3)
+ dest = ARMul_Align (state, address, dest);
+ WRITEDEST (dest);
+ ARMul_Icycles (state, 1, 0L);
- return(DESTReg != LHSReg) ;
+ return (DESTReg != LHSReg);
}
#ifdef MODET
* This function does the work of loading a halfword. *
\***************************************************************************/
-static unsigned LoadHalfWord(ARMul_State *state, ARMword instr, ARMword address,int signextend)
+static unsigned
+LoadHalfWord (ARMul_State * state, ARMword instr, ARMword address,
+ int signextend)
{
- ARMword dest ;
+ ARMword dest;
- BUSUSEDINCPCS ;
+ BUSUSEDINCPCS;
#ifndef MODE32
- if (ADDREXCEPT(address)) {
- INTERNALABORT(address) ;
+ if (ADDREXCEPT (address))
+ {
+ INTERNALABORT (address);
}
#endif
- dest = ARMul_LoadHalfWord(state,address) ;
- if (state->Aborted) {
- TAKEABORT ;
- return(state->lateabtSig) ;
+ dest = ARMul_LoadHalfWord (state, address);
+ if (state->Aborted)
+ {
+ TAKEABORT;
+ return (state->lateabtSig);
}
- UNDEF_LSRBPC ;
- if (signextend)
- {
- if (dest & 1 << (16 - 1))
- dest = (dest & ((1 << 16) - 1)) - (1 << 16) ;
- }
- WRITEDEST(dest) ;
- ARMul_Icycles(state,1,0L) ;
- return(DESTReg != LHSReg) ;
+ UNDEF_LSRBPC;
+ if (signextend)
+ {
+ if (dest & 1 << (16 - 1))
+ dest = (dest & ((1 << 16) - 1)) - (1 << 16);
+ }
+ WRITEDEST (dest);
+ ARMul_Icycles (state, 1, 0L);
+ return (DESTReg != LHSReg);
}
+
#endif /* MODET */
/***************************************************************************\
* This function does the work of loading a byte for a LDRB instruction. *
\***************************************************************************/
-static unsigned LoadByte(ARMul_State *state, ARMword instr, ARMword address,int signextend)
+static unsigned
+LoadByte (ARMul_State * state, ARMword instr, ARMword address, int signextend)
{
- ARMword dest ;
+ ARMword dest;
- BUSUSEDINCPCS ;
+ BUSUSEDINCPCS;
#ifndef MODE32
- if (ADDREXCEPT(address)) {
- INTERNALABORT(address) ;
+ if (ADDREXCEPT (address))
+ {
+ INTERNALABORT (address);
}
#endif
- dest = ARMul_LoadByte(state,address) ;
- if (state->Aborted) {
- TAKEABORT ;
- return(state->lateabtSig) ;
+ dest = ARMul_LoadByte (state, address);
+ if (state->Aborted)
+ {
+ TAKEABORT;
+ return (state->lateabtSig);
+ }
+ UNDEF_LSRBPC;
+ if (signextend)
+ {
+ if (dest & 1 << (8 - 1))
+ dest = (dest & ((1 << 8) - 1)) - (1 << 8);
}
- UNDEF_LSRBPC ;
- if (signextend)
- {
- if (dest & 1 << (8 - 1))
- dest = (dest & ((1 << 8) - 1)) - (1 << 8) ;
- }
- WRITEDEST(dest) ;
- ARMul_Icycles(state,1,0L) ;
- return(DESTReg != LHSReg) ;
+ WRITEDEST (dest);
+ ARMul_Icycles (state, 1, 0L);
+ return (DESTReg != LHSReg);
}
/***************************************************************************\
* This function does the work of storing a word from a STR instruction. *
\***************************************************************************/
-static unsigned StoreWord(ARMul_State *state, ARMword instr, ARMword address)
-{BUSUSEDINCPCN ;
+static unsigned
+StoreWord (ARMul_State * state, ARMword instr, ARMword address)
+{
+ BUSUSEDINCPCN;
#ifndef MODE32
- if (DESTReg == 15)
- state->Reg[15] = ECC | ER15INT | R15PC | EMODE ;
+ if (DESTReg == 15)
+ state->Reg[15] = ECC | ER15INT | R15PC | EMODE;
#endif
#ifdef MODE32
- ARMul_StoreWordN(state,address,DEST) ;
+ ARMul_StoreWordN (state, address, DEST);
#else
- if (VECTORACCESS(address) || ADDREXCEPT(address)) {
- INTERNALABORT(address) ;
- (void)ARMul_LoadWordN(state,address) ;
+ if (VECTORACCESS (address) || ADDREXCEPT (address))
+ {
+ INTERNALABORT (address);
+ (void) ARMul_LoadWordN (state, address);
}
- else
- ARMul_StoreWordN(state,address,DEST) ;
+ else
+ ARMul_StoreWordN (state, address, DEST);
#endif
- if (state->Aborted) {
- TAKEABORT ;
- return(state->lateabtSig) ;
+ if (state->Aborted)
+ {
+ TAKEABORT;
+ return (state->lateabtSig);
}
- return(TRUE) ;
+ return (TRUE);
}
#ifdef MODET
* This function does the work of storing a byte for a STRH instruction. *
\***************************************************************************/
-static unsigned StoreHalfWord(ARMul_State *state, ARMword instr, ARMword address)
-{BUSUSEDINCPCN ;
+static unsigned
+StoreHalfWord (ARMul_State * state, ARMword instr, ARMword address)
+{
+ BUSUSEDINCPCN;
#ifndef MODE32
- if (DESTReg == 15)
- state->Reg[15] = ECC | ER15INT | R15PC | EMODE ;
+ if (DESTReg == 15)
+ state->Reg[15] = ECC | ER15INT | R15PC | EMODE;
#endif
#ifdef MODE32
- ARMul_StoreHalfWord(state,address,DEST);
+ ARMul_StoreHalfWord (state, address, DEST);
#else
- if (VECTORACCESS(address) || ADDREXCEPT(address)) {
- INTERNALABORT(address) ;
- (void)ARMul_LoadHalfWord(state,address) ;
+ if (VECTORACCESS (address) || ADDREXCEPT (address))
+ {
+ INTERNALABORT (address);
+ (void) ARMul_LoadHalfWord (state, address);
}
- else
- ARMul_StoreHalfWord(state,address,DEST) ;
+ else
+ ARMul_StoreHalfWord (state, address, DEST);
#endif
- if (state->Aborted) {
- TAKEABORT ;
- return(state->lateabtSig) ;
+ if (state->Aborted)
+ {
+ TAKEABORT;
+ return (state->lateabtSig);
}
- return(TRUE) ;
+ return (TRUE);
}
+
#endif /* MODET */
/***************************************************************************\
* This function does the work of storing a byte for a STRB instruction. *
\***************************************************************************/
-static unsigned StoreByte(ARMul_State *state, ARMword instr, ARMword address)
-{BUSUSEDINCPCN ;
+static unsigned
+StoreByte (ARMul_State * state, ARMword instr, ARMword address)
+{
+ BUSUSEDINCPCN;
#ifndef MODE32
- if (DESTReg == 15)
- state->Reg[15] = ECC | ER15INT | R15PC | EMODE ;
+ if (DESTReg == 15)
+ state->Reg[15] = ECC | ER15INT | R15PC | EMODE;
#endif
#ifdef MODE32
- ARMul_StoreByte(state,address,DEST) ;
+ ARMul_StoreByte (state, address, DEST);
#else
- if (VECTORACCESS(address) || ADDREXCEPT(address)) {
- INTERNALABORT(address) ;
- (void)ARMul_LoadByte(state,address) ;
+ if (VECTORACCESS (address) || ADDREXCEPT (address))
+ {
+ INTERNALABORT (address);
+ (void) ARMul_LoadByte (state, address);
}
- else
- ARMul_StoreByte(state,address,DEST) ;
+ else
+ ARMul_StoreByte (state, address, DEST);
#endif
- if (state->Aborted) {
- TAKEABORT ;
- return(state->lateabtSig) ;
+ if (state->Aborted)
+ {
+ TAKEABORT;
+ return (state->lateabtSig);
}
- UNDEF_LSRBPC ;
- return(TRUE) ;
+ UNDEF_LSRBPC;
+ return (TRUE);
}
/***************************************************************************\
* handle base register modification. *
\***************************************************************************/
-static void LoadMult(ARMul_State *state, ARMword instr,
- ARMword address, ARMword WBBase)
-{ARMword dest, temp ;
+static void
+LoadMult (ARMul_State * state, ARMword instr, ARMword address, ARMword WBBase)
+{
+ ARMword dest, temp;
- UNDEF_LSMNoRegs ;
- UNDEF_LSMPCBase ;
- UNDEF_LSMBaseInListWb ;
- BUSUSEDINCPCS ;
+ UNDEF_LSMNoRegs;
+ UNDEF_LSMPCBase;
+ UNDEF_LSMBaseInListWb;
+ BUSUSEDINCPCS;
#ifndef MODE32
- if (ADDREXCEPT(address)) {
- INTERNALABORT(address) ;
+ if (ADDREXCEPT (address))
+ {
+ INTERNALABORT (address);
}
#endif
- if (BIT(21) && LHSReg != 15)
- LSBase = WBBase ;
-
- for (temp = 0 ; !BIT(temp) ; temp++) ; /* N cycle first */
- dest = ARMul_LoadWordN(state,address) ;
- if (!state->abortSig && !state->Aborted)
- state->Reg[temp++] = dest ;
- else
- if (!state->Aborted)
- state->Aborted = ARMul_DataAbortV ;
-
- for (; temp < 16 ; temp++) /* S cycles from here on */
- if (BIT(temp)) { /* load this register */
- address += 4 ;
- dest = ARMul_LoadWordS(state,address) ;
- if (!state->abortSig && !state->Aborted)
- state->Reg[temp] = dest ;
- else
- if (!state->Aborted)
- state->Aborted = ARMul_DataAbortV ;
- }
-
- if (BIT(15)) { /* PC is in the reg list */
+ if (BIT (21) && LHSReg != 15)
+ LSBase = WBBase;
+
+ for (temp = 0; !BIT (temp); temp++); /* N cycle first */
+ dest = ARMul_LoadWordN (state, address);
+ if (!state->abortSig && !state->Aborted)
+ state->Reg[temp++] = dest;
+ else if (!state->Aborted)
+ state->Aborted = ARMul_DataAbortV;
+
+ for (; temp < 16; temp++) /* S cycles from here on */
+ if (BIT (temp))
+ { /* load this register */
+ address += 4;
+ dest = ARMul_LoadWordS (state, address);
+ if (!state->abortSig && !state->Aborted)
+ state->Reg[temp] = dest;
+ else if (!state->Aborted)
+ state->Aborted = ARMul_DataAbortV;
+ }
+
+ if (BIT (15))
+ { /* PC is in the reg list */
#ifdef MODE32
- state->Reg[15] = PC ;
+ state->Reg[15] = PC;
#endif
- FLUSHPIPE ;
+ FLUSHPIPE;
}
- ARMul_Icycles(state,1,0L) ; /* to write back the final register */
+ ARMul_Icycles (state, 1, 0L); /* to write back the final register */
- if (state->Aborted) {
- if (BIT(21) && LHSReg != 15)
- LSBase = WBBase ;
- TAKEABORT ;
+ if (state->Aborted)
+ {
+ if (BIT (21) && LHSReg != 15)
+ LSBase = WBBase;
+ TAKEABORT;
}
- }
+}
/***************************************************************************\
* This function does the work of loading the registers listed in an LDM *
* handle base register modification. *
\***************************************************************************/
-static void LoadSMult(ARMul_State *state, ARMword instr,
- ARMword address, ARMword WBBase)
-{ARMword dest, temp ;
+static void
+LoadSMult (ARMul_State * state, ARMword instr,
+ ARMword address, ARMword WBBase)
+{
+ ARMword dest, temp;
- UNDEF_LSMNoRegs ;
- UNDEF_LSMPCBase ;
- UNDEF_LSMBaseInListWb ;
- BUSUSEDINCPCS ;
+ UNDEF_LSMNoRegs;
+ UNDEF_LSMPCBase;
+ UNDEF_LSMBaseInListWb;
+ BUSUSEDINCPCS;
#ifndef MODE32
- if (ADDREXCEPT(address)) {
- INTERNALABORT(address) ;
+ if (ADDREXCEPT (address))
+ {
+ INTERNALABORT (address);
}
#endif
- if (!BIT(15) && state->Bank != USERBANK) {
- (void)ARMul_SwitchMode(state,state->Mode,USER26MODE) ; /* temporary reg bank switch */
- UNDEF_LSMUserBankWb ;
+ if (!BIT (15) && state->Bank != USERBANK)
+ {
+ (void) ARMul_SwitchMode (state, state->Mode, USER26MODE); /* temporary reg bank switch */
+ UNDEF_LSMUserBankWb;
}
- if (BIT(21) && LHSReg != 15)
- LSBase = WBBase ;
-
- for (temp = 0 ; !BIT(temp) ; temp++) ; /* N cycle first */
- dest = ARMul_LoadWordN(state,address) ;
- if (!state->abortSig)
- state->Reg[temp++] = dest ;
- else
- if (!state->Aborted)
- state->Aborted = ARMul_DataAbortV ;
-
- for (; temp < 16 ; temp++) /* S cycles from here on */
- if (BIT(temp)) { /* load this register */
- address += 4 ;
- dest = ARMul_LoadWordS(state,address) ;
- if (!state->abortSig || state->Aborted)
- state->Reg[temp] = dest ;
- else
- if (!state->Aborted)
- state->Aborted = ARMul_DataAbortV ;
- }
-
- if (BIT(15)) { /* PC is in the reg list */
+ if (BIT (21) && LHSReg != 15)
+ LSBase = WBBase;
+
+ for (temp = 0; !BIT (temp); temp++); /* N cycle first */
+ dest = ARMul_LoadWordN (state, address);
+ if (!state->abortSig)
+ state->Reg[temp++] = dest;
+ else if (!state->Aborted)
+ state->Aborted = ARMul_DataAbortV;
+
+ for (; temp < 16; temp++) /* S cycles from here on */
+ if (BIT (temp))
+ { /* load this register */
+ address += 4;
+ dest = ARMul_LoadWordS (state, address);
+ if (!state->abortSig || state->Aborted)
+ state->Reg[temp] = dest;
+ else if (!state->Aborted)
+ state->Aborted = ARMul_DataAbortV;
+ }
+
+ if (BIT (15))
+ { /* PC is in the reg list */
#ifdef MODE32
- if (state->Mode != USER26MODE && state->Mode != USER32MODE) {
- state->Cpsr = GETSPSR(state->Bank) ;
- ARMul_CPSRAltered(state) ;
- }
- state->Reg[15] = PC ;
+ if (state->Mode != USER26MODE && state->Mode != USER32MODE)
+ {
+ state->Cpsr = GETSPSR (state->Bank);
+ ARMul_CPSRAltered (state);
+ }
+ state->Reg[15] = PC;
#else
- if (state->Mode == USER26MODE || state->Mode == USER32MODE) { /* protect bits in user mode */
- ASSIGNN((state->Reg[15] & NBIT) != 0) ;
- ASSIGNZ((state->Reg[15] & ZBIT) != 0) ;
- ASSIGNC((state->Reg[15] & CBIT) != 0) ;
- ASSIGNV((state->Reg[15] & VBIT) != 0) ;
- }
- else
- ARMul_R15Altered(state) ;
-#endif
- FLUSHPIPE ;
+ if (state->Mode == USER26MODE || state->Mode == USER32MODE)
+ { /* protect bits in user mode */
+ ASSIGNN ((state->Reg[15] & NBIT) != 0);
+ ASSIGNZ ((state->Reg[15] & ZBIT) != 0);
+ ASSIGNC ((state->Reg[15] & CBIT) != 0);
+ ASSIGNV ((state->Reg[15] & VBIT) != 0);
+ }
+ else
+ ARMul_R15Altered (state);
+#endif
+ FLUSHPIPE;
}
- if (!BIT(15) && state->Mode != USER26MODE && state->Mode != USER32MODE)
- (void)ARMul_SwitchMode(state,USER26MODE,state->Mode) ; /* restore the correct bank */
+ if (!BIT (15) && state->Mode != USER26MODE && state->Mode != USER32MODE)
+ (void) ARMul_SwitchMode (state, USER26MODE, state->Mode); /* restore the correct bank */
- ARMul_Icycles(state,1,0L) ; /* to write back the final register */
+ ARMul_Icycles (state, 1, 0L); /* to write back the final register */
- if (state->Aborted) {
- if (BIT(21) && LHSReg != 15)
- LSBase = WBBase ;
- TAKEABORT ;
+ if (state->Aborted)
+ {
+ if (BIT (21) && LHSReg != 15)
+ LSBase = WBBase;
+ TAKEABORT;
}
}
* handle base register modification. *
\***************************************************************************/
-static void StoreMult(ARMul_State *state, ARMword instr,
- ARMword address, ARMword WBBase)
-{ARMword temp ;
+static void
+StoreMult (ARMul_State * state, ARMword instr,
+ ARMword address, ARMword WBBase)
+{
+ ARMword temp;
- UNDEF_LSMNoRegs ;
- UNDEF_LSMPCBase ;
- UNDEF_LSMBaseInListWb ;
- if (!TFLAG) {
- BUSUSEDINCPCN ; /* N-cycle, increment the PC and update the NextInstr state */
- }
+ UNDEF_LSMNoRegs;
+ UNDEF_LSMPCBase;
+ UNDEF_LSMBaseInListWb;
+ if (!TFLAG)
+ {
+ BUSUSEDINCPCN; /* N-cycle, increment the PC and update the NextInstr state */
+ }
#ifndef MODE32
- if (VECTORACCESS(address) || ADDREXCEPT(address)) {
- INTERNALABORT(address) ;
+ if (VECTORACCESS (address) || ADDREXCEPT (address))
+ {
+ INTERNALABORT (address);
}
- if (BIT(15))
- PATCHR15 ;
+ if (BIT (15))
+ PATCHR15;
#endif
- for (temp = 0 ; !BIT(temp) ; temp++) ; /* N cycle first */
+ for (temp = 0; !BIT (temp); temp++); /* N cycle first */
#ifdef MODE32
- ARMul_StoreWordN(state,address,state->Reg[temp++]) ;
+ ARMul_StoreWordN (state, address, state->Reg[temp++]);
#else
- if (state->Aborted) {
- (void)ARMul_LoadWordN(state,address) ;
- for ( ; temp < 16 ; temp++) /* Fake the Stores as Loads */
- if (BIT(temp)) { /* save this register */
- address += 4 ;
- (void)ARMul_LoadWordS(state,address) ;
- }
- if (BIT(21) && LHSReg != 15)
- LSBase = WBBase ;
- TAKEABORT ;
- return ;
+ if (state->Aborted)
+ {
+ (void) ARMul_LoadWordN (state, address);
+ for (; temp < 16; temp++) /* Fake the Stores as Loads */
+ if (BIT (temp))
+ { /* save this register */
+ address += 4;
+ (void) ARMul_LoadWordS (state, address);
+ }
+ if (BIT (21) && LHSReg != 15)
+ LSBase = WBBase;
+ TAKEABORT;
+ return;
+ }
+ else
+ ARMul_StoreWordN (state, address, state->Reg[temp++]);
+#endif
+ if (state->abortSig && !state->Aborted)
+ state->Aborted = ARMul_DataAbortV;
+
+ if (BIT (21) && LHSReg != 15)
+ LSBase = WBBase;
+
+ for (; temp < 16; temp++) /* S cycles from here on */
+ if (BIT (temp))
+ { /* save this register */
+ address += 4;
+ ARMul_StoreWordS (state, address, state->Reg[temp]);
+ if (state->abortSig && !state->Aborted)
+ state->Aborted = ARMul_DataAbortV;
+ }
+ if (state->Aborted)
+ {
+ TAKEABORT;
}
- else
- ARMul_StoreWordN(state,address,state->Reg[temp++]) ;
-#endif
- if (state->abortSig && !state->Aborted)
- state->Aborted = ARMul_DataAbortV ;
-
- if (BIT(21) && LHSReg != 15)
- LSBase = WBBase ;
-
- for ( ; temp < 16 ; temp++) /* S cycles from here on */
- if (BIT(temp)) { /* save this register */
- address += 4 ;
- ARMul_StoreWordS(state,address,state->Reg[temp]) ;
- if (state->abortSig && !state->Aborted)
- state->Aborted = ARMul_DataAbortV ;
- }
- if (state->Aborted) {
- TAKEABORT ;
- }
- }
+}
/***************************************************************************\
* This function does the work of storing the registers listed in an STM *
* handle base register modification. *
\***************************************************************************/
-static void StoreSMult(ARMul_State *state, ARMword instr,
- ARMword address, ARMword WBBase)
-{ARMword temp ;
+static void
+StoreSMult (ARMul_State * state, ARMword instr,
+ ARMword address, ARMword WBBase)
+{
+ ARMword temp;
- UNDEF_LSMNoRegs ;
- UNDEF_LSMPCBase ;
- UNDEF_LSMBaseInListWb ;
- BUSUSEDINCPCN ;
+ UNDEF_LSMNoRegs;
+ UNDEF_LSMPCBase;
+ UNDEF_LSMBaseInListWb;
+ BUSUSEDINCPCN;
#ifndef MODE32
- if (VECTORACCESS(address) || ADDREXCEPT(address)) {
- INTERNALABORT(address) ;
+ if (VECTORACCESS (address) || ADDREXCEPT (address))
+ {
+ INTERNALABORT (address);
}
- if (BIT(15))
- PATCHR15 ;
+ if (BIT (15))
+ PATCHR15;
#endif
- if (state->Bank != USERBANK) {
- (void)ARMul_SwitchMode(state,state->Mode,USER26MODE) ; /* Force User Bank */
- UNDEF_LSMUserBankWb ;
+ if (state->Bank != USERBANK)
+ {
+ (void) ARMul_SwitchMode (state, state->Mode, USER26MODE); /* Force User Bank */
+ UNDEF_LSMUserBankWb;
}
- for (temp = 0 ; !BIT(temp) ; temp++) ; /* N cycle first */
+ for (temp = 0; !BIT (temp); temp++); /* N cycle first */
#ifdef MODE32
- ARMul_StoreWordN(state,address,state->Reg[temp++]) ;
+ ARMul_StoreWordN (state, address, state->Reg[temp++]);
#else
- if (state->Aborted) {
- (void)ARMul_LoadWordN(state,address) ;
- for ( ; temp < 16 ; temp++) /* Fake the Stores as Loads */
- if (BIT(temp)) { /* save this register */
- address += 4 ;
- (void)ARMul_LoadWordS(state,address) ;
- }
- if (BIT(21) && LHSReg != 15)
- LSBase = WBBase ;
- TAKEABORT ;
- return ;
+ if (state->Aborted)
+ {
+ (void) ARMul_LoadWordN (state, address);
+ for (; temp < 16; temp++) /* Fake the Stores as Loads */
+ if (BIT (temp))
+ { /* save this register */
+ address += 4;
+ (void) ARMul_LoadWordS (state, address);
+ }
+ if (BIT (21) && LHSReg != 15)
+ LSBase = WBBase;
+ TAKEABORT;
+ return;
}
- else
- ARMul_StoreWordN(state,address,state->Reg[temp++]) ;
+ else
+ ARMul_StoreWordN (state, address, state->Reg[temp++]);
#endif
- if (state->abortSig && !state->Aborted)
- state->Aborted = ARMul_DataAbortV ;
+ if (state->abortSig && !state->Aborted)
+ state->Aborted = ARMul_DataAbortV;
- if (BIT(21) && LHSReg != 15)
- LSBase = WBBase ;
+ if (BIT (21) && LHSReg != 15)
+ LSBase = WBBase;
- for (; temp < 16 ; temp++) /* S cycles from here on */
- if (BIT(temp)) { /* save this register */
- address += 4 ;
- ARMul_StoreWordS(state,address,state->Reg[temp]) ;
- if (state->abortSig && !state->Aborted)
- state->Aborted = ARMul_DataAbortV ;
- }
+ for (; temp < 16; temp++) /* S cycles from here on */
+ if (BIT (temp))
+ { /* save this register */
+ address += 4;
+ ARMul_StoreWordS (state, address, state->Reg[temp]);
+ if (state->abortSig && !state->Aborted)
+ state->Aborted = ARMul_DataAbortV;
+ }
- if (state->Mode != USER26MODE && state->Mode != USER32MODE)
- (void)ARMul_SwitchMode(state,USER26MODE,state->Mode) ; /* restore the correct bank */
+ if (state->Mode != USER26MODE && state->Mode != USER32MODE)
+ (void) ARMul_SwitchMode (state, USER26MODE, state->Mode); /* restore the correct bank */
- if (state->Aborted) {
- TAKEABORT ;
+ if (state->Aborted)
+ {
+ TAKEABORT;
}
}
* calculating if a carry has occurred. *
\***************************************************************************/
-static ARMword Add32(ARMword a1,ARMword a2,int *carry)
+static ARMword
+Add32 (ARMword a1, ARMword a2, int *carry)
{
ARMword result = (a1 + a2);
- unsigned int uresult = (unsigned int)result;
- unsigned int ua1 = (unsigned int)a1;
+ unsigned int uresult = (unsigned int) result;
+ unsigned int ua1 = (unsigned int) a1;
/* If (result == RdLo) and (state->Reg[nRdLo] == 0),
or (result > RdLo) then we have no carry: */
if ((uresult == ua1) ? (a2 != 0) : (uresult < ua1))
- *carry = 1;
+ *carry = 1;
else
- *carry = 0;
+ *carry = 0;
- return(result);
+ return (result);
}
/***************************************************************************\
* 64bit result. *
\***************************************************************************/
-static unsigned Multiply64(ARMul_State *state,ARMword instr,int msigned,int scc)
+static unsigned
+Multiply64 (ARMul_State * state, ARMword instr, int msigned, int scc)
{
- int nRdHi, nRdLo, nRs, nRm; /* operand register numbers */
- ARMword RdHi, RdLo, Rm;
- int scount; /* cycle count */
+ int nRdHi, nRdLo, nRs, nRm; /* operand register numbers */
+ ARMword RdHi = 0, RdLo = 0, Rm;
+ int scount; /* cycle count */
- nRdHi = BITS(16,19);
- nRdLo = BITS(12,15);
- nRs = BITS(8,11);
- nRm = BITS(0,3);
+ nRdHi = BITS (16, 19);
+ nRdLo = BITS (12, 15);
+ nRs = BITS (8, 11);
+ nRm = BITS (0, 3);
/* Needed to calculate the cycle count: */
Rm = state->Reg[nRm];
/* Check for illegal operand combinations first: */
- if ( nRdHi != 15
+ if (nRdHi != 15
&& nRdLo != 15
- && nRs != 15
- && nRm != 15
- && nRdHi != nRdLo
- && nRdHi != nRm
- && nRdLo != nRm)
+ && nRs != 15
+ && nRm != 15 && nRdHi != nRdLo && nRdHi != nRm && nRdLo != nRm)
{
- ARMword lo, mid1, mid2, hi; /* intermediate results */
+ ARMword lo, mid1, mid2, hi; /* intermediate results */
int carry;
- ARMword Rs = state->Reg[ nRs ];
+ ARMword Rs = state->Reg[nRs];
int sign = 0;
if (msigned)
{
/* Compute sign of result and adjust operands if necessary. */
-
+
sign = (Rm ^ Rs) & 0x80000000;
-
- if (((signed long)Rm) < 0)
+
+ if (((signed long) Rm) < 0)
Rm = -Rm;
-
- if (((signed long)Rs) < 0)
+
+ if (((signed long) Rs) < 0)
Rs = -Rs;
}
-
+
/* We can split the 32x32 into four 16x16 operations. This ensures
- that we do not lose precision on 32bit only hosts: */
- lo = ((Rs & 0xFFFF) * (Rm & 0xFFFF));
+ that we do not lose precision on 32bit only hosts: */
+ lo = ((Rs & 0xFFFF) * (Rm & 0xFFFF));
mid1 = ((Rs & 0xFFFF) * ((Rm >> 16) & 0xFFFF));
mid2 = (((Rs >> 16) & 0xFFFF) * (Rm & 0xFFFF));
- hi = (((Rs >> 16) & 0xFFFF) * ((Rm >> 16) & 0xFFFF));
-
+ hi = (((Rs >> 16) & 0xFFFF) * ((Rm >> 16) & 0xFFFF));
+
/* We now need to add all of these results together, taking care
- to propogate the carries from the additions: */
- RdLo = Add32(lo,(mid1 << 16),&carry);
+ to propogate the carries from the additions: */
+ RdLo = Add32 (lo, (mid1 << 16), &carry);
RdHi = carry;
- RdLo = Add32(RdLo,(mid2 << 16),&carry);
- RdHi += (carry + ((mid1 >> 16) & 0xFFFF) + ((mid2 >> 16) & 0xFFFF) + hi);
+ RdLo = Add32 (RdLo, (mid2 << 16), &carry);
+ RdHi +=
+ (carry + ((mid1 >> 16) & 0xFFFF) + ((mid2 >> 16) & 0xFFFF) + hi);
if (sign)
{
/* Negate result if necessary. */
-
- RdLo = ~ RdLo;
- RdHi = ~ RdHi;
+
+ RdLo = ~RdLo;
+ RdHi = ~RdHi;
if (RdLo == 0xFFFFFFFF)
{
RdLo = 0;
else
RdLo += 1;
}
-
+
state->Reg[nRdLo] = RdLo;
state->Reg[nRdHi] = RdHi;
-
- } /* else undefined result */
- else fprintf (stderr, "MULTIPLY64 - INVALID ARGUMENTS\n");
-
+ } /* else undefined result */
+ else
+ fprintf (stderr, "MULTIPLY64 - INVALID ARGUMENTS\n");
+
if (scc)
{
if ((RdHi == 0) && (RdLo == 0))
- ARMul_NegZero(state,RdHi); /* zero value */
+ ARMul_NegZero (state, RdHi); /* zero value */
else
- ARMul_NegZero(state,scc); /* non-zero value */
+ ARMul_NegZero (state, scc); /* non-zero value */
}
-
+
/* The cycle count depends on whether the instruction is a signed or
unsigned multiply, and what bits are clear in the multiplier: */
- if (msigned && (Rm & ((unsigned)1 << 31)))
- Rm = ~Rm; /* invert the bits to make the check against zero */
-
+ if (msigned && (Rm & ((unsigned) 1 << 31)))
+ Rm = ~Rm; /* invert the bits to make the check against zero */
+
if ((Rm & 0xFFFFFF00) == 0)
- scount = 1 ;
+ scount = 1;
else if ((Rm & 0xFFFF0000) == 0)
- scount = 2 ;
+ scount = 2;
else if ((Rm & 0xFF000000) == 0)
- scount = 3 ;
+ scount = 3;
else
- scount = 4 ;
-
- return 2 + scount ;
+ scount = 4;
+
+ return 2 + scount;
}
/***************************************************************************\
* a 64bit value to give a 64bit result. *
\***************************************************************************/
-static unsigned MultiplyAdd64(ARMul_State *state,ARMword instr,int msigned,int scc)
+static unsigned
+MultiplyAdd64 (ARMul_State * state, ARMword instr, int msigned, int scc)
{
unsigned scount;
ARMword RdLo, RdHi;
int nRdHi, nRdLo;
int carry = 0;
- nRdHi = BITS(16,19);
- nRdLo = BITS(12,15);
+ nRdHi = BITS (16, 19);
+ nRdLo = BITS (12, 15);
- RdHi = state->Reg[nRdHi] ;
- RdLo = state->Reg[nRdLo] ;
+ RdHi = state->Reg[nRdHi];
+ RdLo = state->Reg[nRdLo];
- scount = Multiply64(state,instr,msigned,LDEFAULT);
+ scount = Multiply64 (state, instr, msigned, LDEFAULT);
- RdLo = Add32(RdLo,state->Reg[nRdLo],&carry);
+ RdLo = Add32 (RdLo, state->Reg[nRdLo], &carry);
RdHi = (RdHi + state->Reg[nRdHi]) + carry;
state->Reg[nRdLo] = RdLo;
state->Reg[nRdHi] = RdHi;
- if (scc) {
- if ((RdHi == 0) && (RdLo == 0))
- ARMul_NegZero(state,RdHi); /* zero value */
- else
- ARMul_NegZero(state,scc); /* non-zero value */
- }
+ if (scc)
+ {
+ if ((RdHi == 0) && (RdLo == 0))
+ ARMul_NegZero (state, RdHi); /* zero value */
+ else
+ ARMul_NegZero (state, scc); /* non-zero value */
+ }
- return scount + 1; /* extra cycle for addition */
+ return scount + 1; /* extra cycle for addition */
}
#define POS(i) ( (~(i)) >> 31 )
#define NEG(i) ( (i) >> 31 )
-#ifdef MODET /* Thumb support */
+#ifdef MODET /* Thumb support */
/* ??? This bit is actually in the low order bit of the PC in the hardware.
It isn't clear if the simulator needs to model that or not. */
#define TBIT (1L << 5)
#define CLEARV state->VFlag = 0
#define ASSIGNV(res) state->VFlag = res
+
#define IFLAG (state->IFFlags >> 1)
#define FFLAG (state->IFFlags & 1)
#define IFFLAGS state->IFFlags
ASSIGNV((state->Reg[15] & VBIT) != 0) ; \
} \
else { \
- state->Reg[15] = R15PC | (s) & (CCBITS | R15INTBITS | R15MODEBITS) ; \
- ARMul_R15Altered(state) ; \
+ state->Reg[15] = R15PC | ((s) & (CCBITS | R15INTBITS | R15MODEBITS)) ; \
+ ARMul_R15Altered (state) ; \
}
#define SETABORT(i,m) state->Cpsr = ECC | EINT | (i) | (m)
#define RESUME 8
#define NORMALCYCLE state->NextInstr = 0
-#define BUSUSEDN state->NextInstr |= 1 /* the next fetch will be an N cycle */
+#define BUSUSEDN state->NextInstr |= 1 /* the next fetch will be an N cycle */
#define BUSUSEDINCPCS state->Reg[15] += isize ; /* a standard PC inc and an S cycle */ \
state->NextInstr = (state->NextInstr & 0xff) | 2
#define BUSUSEDINCPCN state->Reg[15] += isize ; /* a standard PC inc and an N cycle */ \
* Values for Emulate *
\***************************************************************************/
-#define STOP 0 /* stop */
-#define CHANGEMODE 1 /* change mode */
-#define ONCE 2 /* execute just one interation */
-#define RUN 3 /* continuous execution */
+#define STOP 0 /* stop */
+#define CHANGEMODE 1 /* change mode */
+#define ONCE 2 /* execute just one interation */
+#define RUN 3 /* continuous execution */
/***************************************************************************\
* Stuff that is shared across modes *
\***************************************************************************/
-extern ARMword ARMul_Emulate26(ARMul_State *state) ;
-extern ARMword ARMul_Emulate32(ARMul_State *state) ;
-extern unsigned ARMul_MultTable[] ; /* Number of I cycles for a mult */
-extern ARMword ARMul_ImmedTable[] ; /* immediate DP LHS values */
-extern char ARMul_BitList[] ; /* number of bits in a byte table */
-extern void ARMul_Abort26(ARMul_State *state, ARMword) ;
-extern void ARMul_Abort32(ARMul_State *state, ARMword) ;
-extern unsigned ARMul_NthReg(ARMword instr,unsigned number) ;
-extern void ARMul_MSRCpsr(ARMul_State *state, ARMword instr, ARMword rhs) ;
-extern void ARMul_NegZero(ARMul_State *state, ARMword result) ;
-extern void ARMul_AddCarry(ARMul_State *state, ARMword a, ARMword b, ARMword result) ;
-extern void ARMul_AddOverflow(ARMul_State *state, ARMword a, ARMword b, ARMword result) ;
-extern void ARMul_SubCarry(ARMul_State *state, ARMword a, ARMword b, ARMword result) ;
-extern void ARMul_SubOverflow(ARMul_State *state, ARMword a, ARMword b, ARMword result) ;
-extern void ARMul_CPSRAltered(ARMul_State *state) ;
-extern void ARMul_R15Altered(ARMul_State *state) ;
-extern ARMword ARMul_SwitchMode(ARMul_State *state,ARMword oldmode, ARMword newmode) ;
-extern unsigned ARMul_NthReg(ARMword instr, unsigned number) ;
-extern void ARMul_LDC(ARMul_State *state,ARMword instr,ARMword address) ;
-extern void ARMul_STC(ARMul_State *state,ARMword instr,ARMword address) ;
-extern void ARMul_MCR(ARMul_State *state,ARMword instr, ARMword source) ;
-extern ARMword ARMul_MRC(ARMul_State *state,ARMword instr) ;
-extern void ARMul_CDP(ARMul_State *state,ARMword instr) ;
-extern unsigned IntPending(ARMul_State *state) ;
-extern ARMword ARMul_Align(ARMul_State *state, ARMword address, ARMword data) ;
+extern ARMword ARMul_Emulate26 (ARMul_State * state);
+extern ARMword ARMul_Emulate32 (ARMul_State * state);
+extern unsigned ARMul_MultTable[]; /* Number of I cycles for a mult */
+extern ARMword ARMul_ImmedTable[]; /* immediate DP LHS values */
+extern char ARMul_BitList[]; /* number of bits in a byte table */
+extern void ARMul_Abort26 (ARMul_State * state, ARMword);
+extern void ARMul_Abort32 (ARMul_State * state, ARMword);
+extern unsigned ARMul_NthReg (ARMword instr, unsigned number);
+extern void ARMul_MSRCpsr (ARMul_State * state, ARMword instr, ARMword rhs);
+extern void ARMul_NegZero (ARMul_State * state, ARMword result);
+extern void ARMul_AddCarry (ARMul_State * state, ARMword a, ARMword b,
+ ARMword result);
+extern int AddOverflow (ARMword a, ARMword b, ARMword result);
+extern int SubOverflow (ARMword a, ARMword b, ARMword result);
+extern void ARMul_AddOverflow (ARMul_State * state, ARMword a, ARMword b,
+ ARMword result);
+extern void ARMul_SubCarry (ARMul_State * state, ARMword a, ARMword b,
+ ARMword result);
+extern void ARMul_SubOverflow (ARMul_State * state, ARMword a, ARMword b,
+ ARMword result);
+extern void ARMul_CPSRAltered (ARMul_State * state);
+extern void ARMul_R15Altered (ARMul_State * state);
+extern ARMword ARMul_SwitchMode (ARMul_State * state, ARMword oldmode,
+ ARMword newmode);
+extern unsigned ARMul_NthReg (ARMword instr, unsigned number);
+extern void ARMul_LDC (ARMul_State * state, ARMword instr, ARMword address);
+extern void ARMul_STC (ARMul_State * state, ARMword instr, ARMword address);
+extern void ARMul_MCR (ARMul_State * state, ARMword instr, ARMword source);
+extern ARMword ARMul_MRC (ARMul_State * state, ARMword instr);
+extern void ARMul_CDP (ARMul_State * state, ARMword instr);
+extern unsigned IntPending (ARMul_State * state);
+extern ARMword ARMul_Align (ARMul_State * state, ARMword address,
+ ARMword data);
#define EVENTLISTSIZE 1024L
/* Thumb support: */
-typedef enum {
- t_undefined, /* undefined Thumb instruction */
- t_decoded, /* instruction decoded to ARM equivalent */
- t_branch /* Thumb branch (already processed) */
-} tdstate;
+typedef enum
+{
+ t_undefined, /* undefined Thumb instruction */
+ t_decoded, /* instruction decoded to ARM equivalent */
+ t_branch /* Thumb branch (already processed) */
+}
+tdstate;
-extern tdstate ARMul_ThumbDecode(ARMul_State *state,ARMword pc,ARMword tinstr, ARMword *ainstr);
+extern tdstate ARMul_ThumbDecode (ARMul_State * state, ARMword pc,
+ ARMword tinstr, ARMword * ainstr);
/***************************************************************************\
* Macros to scrutinize instructions *
#define UNDEF_IllegalMode
#define UNDEF_Prog32SigChange
#define UNDEF_Data32SigChange
-
0x11 to halt the emulator. */
#include "config.h"
+#include "ansidecl.h"
#include <time.h>
#include <errno.h>
#endif
#ifdef HAVE_UNISTD_H
-#include <unistd.h> /* For SEEK_SET etc */
+#include <unistd.h> /* For SEEK_SET etc */
#endif
#ifdef __riscos
-extern int _fisatty(FILE *);
+extern int _fisatty (FILE *);
#define isatty_(f) _fisatty(f)
#else
#ifdef __ZTC__
/* For RDIError_BreakpointReached. */
#include "dbg_rdi.h"
-extern unsigned ARMul_OSInit(ARMul_State *state) ;
-extern void ARMul_OSExit(ARMul_State *state) ;
-extern unsigned ARMul_OSHandleSWI(ARMul_State *state,ARMword number) ;
-extern unsigned ARMul_OSException(ARMul_State *state, ARMword vector, ARMword pc) ;
-extern ARMword ARMul_OSLastErrorP(ARMul_State *state) ;
-extern ARMword ARMul_Debug(ARMul_State *state, ARMword pc, ARMword instr) ;
+extern unsigned ARMul_OSInit (ARMul_State * state);
+extern void ARMul_OSExit (ARMul_State * state);
+extern unsigned ARMul_OSHandleSWI (ARMul_State * state, ARMword number);
+extern unsigned ARMul_OSException (ARMul_State * state, ARMword vector,
+ ARMword pc);
+extern ARMword ARMul_OSLastErrorP (ARMul_State * state);
+extern ARMword ARMul_Debug (ARMul_State * state, ARMword pc, ARMword instr);
#define BUFFERSIZE 4096
#ifndef FOPEN_MAX
#endif
#define UNIQUETEMPS 256
-#ifndef NOOS
-static void UnwindDataAbort(ARMul_State *state, ARMword addr);
-static void getstring(ARMul_State *state, ARMword from, char *to) ;
-#endif
-
/***************************************************************************\
* OS private Information *
\***************************************************************************/
-struct OSblock {
- ARMword Time0 ;
- ARMword ErrorP ;
- ARMword ErrorNo ;
- FILE *FileTable[FOPEN_MAX] ;
- char FileFlags[FOPEN_MAX] ;
- char *tempnames[UNIQUETEMPS] ;
- } ;
+struct OSblock
+{
+ ARMword Time0;
+ ARMword ErrorP;
+ ARMword ErrorNo;
+ FILE *FileTable[FOPEN_MAX];
+ char FileFlags[FOPEN_MAX];
+ char *tempnames[UNIQUETEMPS];
+};
#define NOOP 0
#define BINARY 1
c : \
((c == '\n' || c == '\r' ) ? (c ^ 7) : c) \
)
-#else
-#define FIXCRLF(t,c) c
+#else
+#define FIXCRLF(t,c) c
#endif
static ARMword softvectorcode[] =
-{ /* basic: swi tidyexception + event; mov pc, lr;
- ldmia r11,{r11,pc}; swi generateexception + event
- */
- 0xef000090, 0xe1a0e00f, 0xe89b8800, 0xef000080, /*Reset*/
- 0xef000091, 0xe1a0e00f, 0xe89b8800, 0xef000081, /*Undef*/
- 0xef000092, 0xe1a0e00f, 0xe89b8800, 0xef000082, /*SWI */
- 0xef000093, 0xe1a0e00f, 0xe89b8800, 0xef000083, /*Prefetch abort*/
- 0xef000094, 0xe1a0e00f, 0xe89b8800, 0xef000084, /*Data abort*/
- 0xef000095, 0xe1a0e00f, 0xe89b8800, 0xef000085, /*Address exception*/
+{ /* basic: swi tidyexception + event; mov pc, lr;
+ ldmia r11,{r11,pc}; swi generateexception + event. */
+ 0xef000090, 0xe1a0e00f, 0xe89b8800, 0xef000080, /*Reset */
+ 0xef000091, 0xe1a0e00f, 0xe89b8800, 0xef000081, /*Undef */
+ 0xef000092, 0xe1a0e00f, 0xe89b8800, 0xef000082, /*SWI */
+ 0xef000093, 0xe1a0e00f, 0xe89b8800, 0xef000083, /*Prefetch abort */
+ 0xef000094, 0xe1a0e00f, 0xe89b8800, 0xef000084, /*Data abort */
+ 0xef000095, 0xe1a0e00f, 0xe89b8800, 0xef000085, /*Address exception */
0xef000096, 0xe1a0e00f, 0xe89b8800, 0xef000086, /*IRQ*/
0xef000097, 0xe1a0e00f, 0xe89b8800, 0xef000087, /*FIQ*/
- 0xef000098, 0xe1a0e00f, 0xe89b8800, 0xef000088, /*Error*/
- 0xe1a0f00e /* default handler */
+ 0xef000098, 0xe1a0e00f, 0xe89b8800, 0xef000088, /*Error */
+ 0xe1a0f00e /* default handler */
};
/***************************************************************************\
* Time for the Operating System to initialise itself. *
\***************************************************************************/
-unsigned
-ARMul_OSInit (ARMul_State *state)
+unsigned
+ARMul_OSInit (ARMul_State * state)
{
#ifndef NOOS
#ifndef VALIDATE
- ARMword instr, i , j ;
- struct OSblock* OSptr = (struct OSblock*)state->OSptr;
-
- if (state->OSptr == NULL) {
- state->OSptr = (unsigned char *)malloc(sizeof(struct OSblock));
- if (state->OSptr == NULL) {
- perror("OS Memory");
- exit(15);
- }
+ ARMword instr, i, j;
+ struct OSblock *OSptr = (struct OSblock *) state->OSptr;
+
+ if (state->OSptr == NULL)
+ {
+ state->OSptr = (unsigned char *) malloc (sizeof (struct OSblock));
+ if (state->OSptr == NULL)
+ {
+ perror ("OS Memory");
+ exit (15);
+ }
}
- OSptr = (struct OSblock*)state->OSptr;
- OSptr->ErrorP = 0;
- state->Reg[13] = ADDRSUPERSTACK; /* set up a stack for the current mode */
- ARMul_SetReg(state,SVC32MODE,13,ADDRSUPERSTACK); /* and for supervisor mode */
- ARMul_SetReg(state,ABORT32MODE,13,ADDRSUPERSTACK); /* and for abort 32 mode */
- ARMul_SetReg(state,UNDEF32MODE,13,ADDRSUPERSTACK); /* and for undef 32 mode */
- instr = 0xe59ff000 | (ADDRSOFTVECTORS - 8); /* load pc from soft vector */
- for (i = ARMul_ResetV ; i <= ARMFIQV ; i += 4)
- ARMul_WriteWord(state, i, instr); /* write hardware vectors */
- for (i = ARMul_ResetV ; i <= ARMFIQV + 4 ; i += 4) {
- ARMul_WriteWord(state, ADDRSOFTVECTORS + i, SOFTVECTORCODE + i * 4);
- ARMul_WriteWord(state, ADDRSOFHANDLERS + 2*i + 4L, SOFTVECTORCODE + sizeof(softvectorcode) - 4L);
+ OSptr = (struct OSblock *) state->OSptr;
+ OSptr->ErrorP = 0;
+ state->Reg[13] = ADDRSUPERSTACK; /* set up a stack for the current mode */
+ ARMul_SetReg (state, SVC32MODE, 13, ADDRSUPERSTACK); /* and for supervisor mode */
+ ARMul_SetReg (state, ABORT32MODE, 13, ADDRSUPERSTACK); /* and for abort 32 mode */
+ ARMul_SetReg (state, UNDEF32MODE, 13, ADDRSUPERSTACK); /* and for undef 32 mode */
+ instr = 0xe59ff000 | (ADDRSOFTVECTORS - 8); /* load pc from soft vector */
+ for (i = ARMul_ResetV; i <= ARMFIQV; i += 4)
+ ARMul_WriteWord (state, i, instr); /* write hardware vectors */
+ for (i = ARMul_ResetV; i <= ARMFIQV + 4; i += 4)
+ {
+ ARMul_WriteWord (state, ADDRSOFTVECTORS + i, SOFTVECTORCODE + i * 4);
+ ARMul_WriteWord (state, ADDRSOFHANDLERS + 2 * i + 4L,
+ SOFTVECTORCODE + sizeof (softvectorcode) - 4L);
}
- for (i = 0 ; i < sizeof(softvectorcode) ; i += 4)
- ARMul_WriteWord(state, SOFTVECTORCODE + i, softvectorcode[i/4]);
- for (i = 0 ; i < FOPEN_MAX ; i++)
- OSptr->FileTable[i] = NULL ;
- for (i = 0 ; i < UNIQUETEMPS ; i++)
- OSptr->tempnames[i] = NULL ;
- ARMul_ConsolePrint (state, ", Demon 1.01");
+ for (i = 0; i < sizeof (softvectorcode); i += 4)
+ ARMul_WriteWord (state, SOFTVECTORCODE + i, softvectorcode[i / 4]);
+ for (i = 0; i < FOPEN_MAX; i++)
+ OSptr->FileTable[i] = NULL;
+ for (i = 0; i < UNIQUETEMPS; i++)
+ OSptr->tempnames[i] = NULL;
+ ARMul_ConsolePrint (state, ", Demon 1.01");
/* #ifndef ASIM */
- /* install fpe */
- for (i = 0 ; i < fpesize ; i+=4) /* copy the code */
- ARMul_WriteWord(state,FPESTART + i,fpecode[i >> 2]) ;
- for (i = FPESTART + fpesize ; ; i-=4) { /* reverse the error strings */
- if ((j = ARMul_ReadWord(state,i)) == 0xffffffff)
- break ;
- if (state->bigendSig && j < 0x80000000) { /* it's part of the string so swap it */
- j = ((j >> 0x18) & 0x000000ff) |
- ((j >> 0x08) & 0x0000ff00) |
- ((j << 0x08) & 0x00ff0000) |
- ((j << 0x18) & 0xff000000) ;
- ARMul_WriteWord(state,i,j) ;
- }
+ /* install fpe */
+ for (i = 0; i < fpesize; i += 4) /* copy the code */
+ ARMul_WriteWord (state, FPESTART + i, fpecode[i >> 2]);
+ for (i = FPESTART + fpesize;; i -= 4)
+ { /* reverse the error strings */
+ if ((j = ARMul_ReadWord (state, i)) == 0xffffffff)
+ break;
+ if (state->bigendSig && j < 0x80000000)
+ { /* it's part of the string so swap it */
+ j = ((j >> 0x18) & 0x000000ff) |
+ ((j >> 0x08) & 0x0000ff00) |
+ ((j << 0x08) & 0x00ff0000) | ((j << 0x18) & 0xff000000);
+ ARMul_WriteWord (state, i, j);
+ }
}
- ARMul_WriteWord(state,FPEOLDVECT,ARMul_ReadWord(state,4)) ; /* copy old illegal instr vector */
- ARMul_WriteWord(state,4,FPENEWVECT(ARMul_ReadWord(state,i-4))) ; /* install new vector */
- ARMul_ConsolePrint (state, ", FPE") ;
+ ARMul_WriteWord (state, FPEOLDVECT, ARMul_ReadWord (state, 4)); /* copy old illegal instr vector */
+ ARMul_WriteWord (state, 4, FPENEWVECT (ARMul_ReadWord (state, i - 4))); /* install new vector */
+ ARMul_ConsolePrint (state, ", FPE");
-/* #endif /* ASIM */
+/* #endif ASIM */
#endif /* VALIDATE */
#endif /* NOOS */
- return(TRUE) ;
+ return (TRUE);
}
-void
-ARMul_OSExit (ARMul_State *state)
+void
+ARMul_OSExit (ARMul_State * state)
{
- free((char *)state->OSptr);
+ free ((char *) state->OSptr);
}
* Return the last Operating System Error. *
\***************************************************************************/
-ARMword
-ARMul_OSLastErrorP (ARMul_State *state)
+ARMword ARMul_OSLastErrorP (ARMul_State * state)
{
- return ((struct OSblock *)state->OSptr)->ErrorP;
+ return ((struct OSblock *) state->OSptr)->ErrorP;
}
-#if 1 /* CYGNUS LOCAL */
-/* This is the cygnus way of doing it, which makes it simple to do our tests */
-
-static int translate_open_mode[] =
-{
- O_RDONLY, /* "r" */
- O_RDONLY+O_BINARY, /* "rb" */
- O_RDWR, /* "r+" */
- O_RDWR +O_BINARY, /* "r+b" */
- O_WRONLY +O_CREAT+O_TRUNC, /* "w" */
- O_WRONLY+O_BINARY+O_CREAT+O_TRUNC, /* "wb" */
- O_RDWR +O_CREAT+O_TRUNC, /* "w+" */
- O_RDWR +O_BINARY+O_CREAT+O_TRUNC, /* "w+b" */
- O_WRONLY +O_APPEND+O_CREAT,/* "a" */
- O_WRONLY+O_BINARY+O_APPEND+O_CREAT,/* "ab" */
- O_RDWR +O_APPEND+O_CREAT,/* "a+" */
- O_RDWR +O_BINARY+O_APPEND+O_CREAT /* "a+b" */
+static int translate_open_mode[] = {
+ O_RDONLY, /* "r" */
+ O_RDONLY + O_BINARY, /* "rb" */
+ O_RDWR, /* "r+" */
+ O_RDWR + O_BINARY, /* "r+b" */
+ O_WRONLY + O_CREAT + O_TRUNC, /* "w" */
+ O_WRONLY + O_BINARY + O_CREAT + O_TRUNC, /* "wb" */
+ O_RDWR + O_CREAT + O_TRUNC, /* "w+" */
+ O_RDWR + O_BINARY + O_CREAT + O_TRUNC, /* "w+b" */
+ O_WRONLY + O_APPEND + O_CREAT, /* "a" */
+ O_WRONLY + O_BINARY + O_APPEND + O_CREAT, /* "ab" */
+ O_RDWR + O_APPEND + O_CREAT, /* "a+" */
+ O_RDWR + O_BINARY + O_APPEND + O_CREAT /* "a+b" */
};
-static void
-SWIWrite0 (ARMul_State *state, ARMword addr)
+static void
+SWIWrite0 (ARMul_State * state, ARMword addr)
{
ARMword temp;
- struct OSblock* OSptr = (struct OSblock*) state->OSptr;
+ struct OSblock *OSptr = (struct OSblock *) state->OSptr;
while ((temp = ARMul_ReadByte (state, addr++)) != 0)
- (void) fputc ((char) temp, stderr);
+ (void) fputc ((char) temp, stdout);
OSptr->ErrorNo = errno;
}
-static void
-WriteCommandLineTo (ARMul_State *state, ARMword addr)
+static void
+WriteCommandLineTo (ARMul_State * state, ARMword addr)
{
ARMword temp;
char *cptr = state->CommandLine;
if (cptr == NULL)
cptr = "\0";
- do {
- temp = (ARMword) *cptr++;
- ARMul_WriteByte (state, addr++, temp);
- } while (temp != 0);
+ do
+ {
+ temp = (ARMword) * cptr++;
+ ARMul_WriteByte (state, addr++, temp);
+ }
+ while (temp != 0);
}
-static void
-SWIopen (ARMul_State *state, ARMword name, ARMword SWIflags)
+static void
+SWIopen (ARMul_State * state, ARMword name, ARMword SWIflags)
{
- struct OSblock* OSptr = (struct OSblock*)state->OSptr;
+ struct OSblock *OSptr = (struct OSblock *) state->OSptr;
char dummy[2000];
int flags;
int i;
- for (i = 0;
- dummy[i] = ARMul_ReadByte (state, name + i);
- i++)
+ for (i = 0; (dummy[i] = ARMul_ReadByte (state, name + i)); i++)
;
/* Now we need to decode the Demon open mode */
/* Filename ":tt" is special: it denotes stdin/out */
if (strcmp (dummy, ":tt") == 0)
{
- if (flags == O_RDONLY) /* opening tty "r" */
- state->Reg[0] = 0; /* stdin */
- else
- state->Reg[0] = 1; /* stdout */
+ if (flags == O_RDONLY) /* opening tty "r" */
+ state->Reg[0] = 0; /* stdin */
+ else
+ state->Reg[0] = 1; /* stdout */
}
else
{
- state->Reg[0] = (int) open (dummy, flags);
+ state->Reg[0] = (int) open (dummy, flags, 0666);
OSptr->ErrorNo = errno;
}
}
-static void
-SWIread (ARMul_State *state, ARMword f, ARMword ptr, ARMword len)
+static void
+SWIread (ARMul_State * state, ARMword f, ARMword ptr, ARMword len)
{
- struct OSblock* OSptr = (struct OSblock*) state->OSptr;
+ struct OSblock *OSptr = (struct OSblock *) state->OSptr;
int res;
int i;
char *local = malloc (len);
+ if (local == NULL)
+ {
+ fprintf (stderr, "sim: Unable to read 0x%ulx bytes - out of memory\n",
+ len);
+ return;
+ }
+
res = read (f, local, len);
if (res > 0)
- for (i = 0; i < res; i++)
+ for (i = 0; i < res; i++)
ARMul_WriteByte (state, ptr + i, local[i]);
free (local);
state->Reg[0] = res == -1 ? -1 : len - res;
OSptr->ErrorNo = errno;
}
-static void
-SWIwrite (ARMul_State *state, ARMword f, ARMword ptr, ARMword len)
+static void
+SWIwrite (ARMul_State * state, ARMword f, ARMword ptr, ARMword len)
{
- struct OSblock* OSptr = (struct OSblock*) state->OSptr;
+ struct OSblock *OSptr = (struct OSblock *) state->OSptr;
int res;
- int i;
+ ARMword i;
char *local = malloc (len);
- for (i = 0; i < len; i++)
+ if (local == NULL)
{
- local[i] = ARMul_ReadByte (state, ptr + i);
+ fprintf (stderr, "sim: Unable to write 0x%lx bytes - out of memory\n",
+ (long) len);
+ return;
}
+
+ for (i = 0; i < len; i++)
+ local[i] = ARMul_ReadByte (state, ptr + i);
+
res = write (f, local, len);
state->Reg[0] = res == -1 ? -1 : len - res;
free (local);
OSptr->ErrorNo = errno;
}
-static void
-SWIflen (ARMul_State *state, ARMword fh)
+static void
+SWIflen (ARMul_State * state, ARMword fh)
{
- struct OSblock* OSptr = (struct OSblock*) state->OSptr;
+ struct OSblock *OSptr = (struct OSblock *) state->OSptr;
ARMword addr;
if (fh == 0 || fh > FOPEN_MAX)
}
addr = lseek (fh, 0, SEEK_CUR);
- if (addr < 0)
- state->Reg[0] = -1L;
- else
- {
- state->Reg[0] = lseek (fh, 0L, SEEK_END);
- (void) lseek (fh, addr, SEEK_SET);
- }
+
+ state->Reg[0] = lseek (fh, 0L, SEEK_END);
+ (void) lseek (fh, addr, SEEK_SET);
OSptr->ErrorNo = errno;
}
* parameter passed is the SWI number (lower 24 bits of the instruction). *
\***************************************************************************/
-unsigned
-ARMul_OSHandleSWI (ARMul_State *state, ARMword number)
+unsigned
+ARMul_OSHandleSWI (ARMul_State * state, ARMword number)
{
- ARMword addr, temp, fildes;
- char buffer[BUFFERSIZE], *cptr;
- FILE *fptr;
- struct OSblock* OSptr = (struct OSblock*)state->OSptr;
+ ARMword addr, temp;
+ struct OSblock *OSptr = (struct OSblock *) state->OSptr;
switch (number)
{
case SWI_Read:
- SWIread (state, state->Reg[0], state->Reg[1], state->Reg[2]);
- return TRUE;
+ SWIread (state, state->Reg[0], state->Reg[1], state->Reg[2]);
+ return TRUE;
case SWI_Write:
- SWIwrite (state, state->Reg[0], state->Reg[1], state->Reg[2]);
- return TRUE;
+ SWIwrite (state, state->Reg[0], state->Reg[1], state->Reg[2]);
+ return TRUE;
case SWI_Open:
- SWIopen (state, state->Reg[0],state->Reg[1]);
- return TRUE;
+ SWIopen (state, state->Reg[0], state->Reg[1]);
+ return TRUE;
- case SWI_Clock :
- /* return number of centi-seconds... */
- state->Reg[0] =
+ case SWI_Clock:
+ /* return number of centi-seconds... */
+ state->Reg[0] =
#ifdef CLOCKS_PER_SEC
- (CLOCKS_PER_SEC >= 100)
- ? (ARMword) (clock() / (CLOCKS_PER_SEC / 100))
- : (ARMword) ((clock() * 100) / CLOCKS_PER_SEC) ;
+ (CLOCKS_PER_SEC >= 100)
+ ? (ARMword) (clock () / (CLOCKS_PER_SEC / 100))
+ : (ARMword) ((clock () * 100) / CLOCKS_PER_SEC);
#else
- /* presume unix... clock() returns microseconds */
- (ARMword) (clock() / 10000) ;
+ /* presume unix... clock() returns microseconds */
+ (ARMword) (clock () / 10000);
#endif
- OSptr->ErrorNo = errno ;
- return(TRUE) ;
-
- case SWI_Time :
- state->Reg[0] = (ARMword)time(NULL) ;
- OSptr->ErrorNo = errno ;
- return(TRUE) ;
-
+ OSptr->ErrorNo = errno;
+ return (TRUE);
+
+ case SWI_Time:
+ state->Reg[0] = (ARMword) time (NULL);
+ OSptr->ErrorNo = errno;
+ return (TRUE);
+
case SWI_Close:
state->Reg[0] = close (state->Reg[0]);
OSptr->ErrorNo = errno;
return TRUE;
- case SWI_Flen :
+ case SWI_Flen:
SWIflen (state, state->Reg[0]);
- return(TRUE) ;
+ return (TRUE);
case SWI_Exit:
- state->Emulate = FALSE ;
+ state->Emulate = FALSE;
return TRUE;
case SWI_Seek:
{
/* We must return non-zero for failure */
- state->Reg[0] = -1 >= lseek (state->Reg[0],
- state->Reg[1],
- SEEK_SET);
+ state->Reg[0] = -1 >= lseek (state->Reg[0], state->Reg[1], SEEK_SET);
OSptr->ErrorNo = errno;
return TRUE;
}
- case SWI_WriteC :
- (void)fputc((int)state->Reg[0],stderr) ;
- OSptr->ErrorNo = errno ;
- return(TRUE) ;
+ case SWI_WriteC:
+ (void) fputc ((int) state->Reg[0], stdout);
+ OSptr->ErrorNo = errno;
+ return (TRUE);
- case SWI_Write0 :
+ case SWI_Write0:
SWIWrite0 (state, state->Reg[0]);
- return(TRUE) ;
+ return (TRUE);
- case SWI_GetErrno :
- state->Reg[0] = OSptr->ErrorNo ;
- return(TRUE) ;
+ case SWI_GetErrno:
+ state->Reg[0] = OSptr->ErrorNo;
+ return (TRUE);
- case SWI_Breakpoint :
- state->EndCondition = RDIError_BreakpointReached ;
- state->Emulate = FALSE ;
- return(TRUE) ;
+ case SWI_Breakpoint:
+ state->EndCondition = RDIError_BreakpointReached;
+ state->Emulate = FALSE;
+ return (TRUE);
- case SWI_GetEnv :
- state->Reg[0] = ADDRCMDLINE ;
- if (state->MemSize)
- state->Reg[1] = state->MemSize ;
- else
- state->Reg[1] = ADDRUSERSTACK ;
+ case SWI_GetEnv:
+ state->Reg[0] = ADDRCMDLINE;
+ if (state->MemSize)
+ state->Reg[1] = state->MemSize;
+ else
+ state->Reg[1] = ADDRUSERSTACK;
- WriteCommandLineTo (state, state->Reg[0]);
- return(TRUE) ;
+ WriteCommandLineTo (state, state->Reg[0]);
+ return (TRUE);
- /* Handle Angel SWIs as well as Demon ones */
+ /* Handle Angel SWIs as well as Demon ones */
case AngelSWI_ARM:
case AngelSWI_Thumb:
/* R1 is almost always a parameter block */
case AngelSWI_Reason_EnterSVC:
default:
state->Emulate = FALSE;
- return(FALSE);
+ return (FALSE);
case AngelSWI_Reason_Clock:
- /* return number of centi-seconds... */
+ /* return number of centi-seconds... */
state->Reg[0] =
#ifdef CLOCKS_PER_SEC
(CLOCKS_PER_SEC >= 100)
- ? (ARMword) (clock() / (CLOCKS_PER_SEC / 100))
- : (ARMword) ((clock() * 100) / CLOCKS_PER_SEC) ;
+ ? (ARMword) (clock () / (CLOCKS_PER_SEC / 100))
+ : (ARMword) ((clock () * 100) / CLOCKS_PER_SEC);
#else
- /* presume unix... clock() returns microseconds */
- (ARMword) (clock() / 10000) ;
+ /* presume unix... clock() returns microseconds */
+ (ARMword) (clock () / 10000);
#endif
OSptr->ErrorNo = errno;
return (TRUE);
return (TRUE);
case AngelSWI_Reason_WriteC:
- (void) fputc ((int) ARMul_ReadByte (state,addr), stderr);
+ (void) fputc ((int) ARMul_ReadByte (state, addr), stdout);
OSptr->ErrorNo = errno;
return (TRUE);
return (TRUE);
case AngelSWI_Reason_Seek:
- state->Reg[0] = -1 >= lseek (ARMul_ReadWord(state,addr),
- ARMul_ReadWord(state,addr+4),
+ state->Reg[0] = -1 >= lseek (ARMul_ReadWord (state, addr),
+ ARMul_ReadWord (state, addr + 4),
SEEK_SET);
OSptr->ErrorNo = errno;
return (TRUE);
SWIflen (state, ARMul_ReadWord (state, addr));
return (TRUE);
- case AngelSWI_Reason_GetCmdLine:
+ case AngelSWI_Reason_GetCmdLine:
WriteCommandLineTo (state, ARMul_ReadWord (state, addr));
return (TRUE);
else
temp = ADDRUSERSTACK;
- ARMul_WriteWord (state, addr, 0); /* Heap base */
- ARMul_WriteWord (state, addr+4, temp); /* Heap limit */
- ARMul_WriteWord (state, addr+8, temp); /* Stack base */
- ARMul_WriteWord (state, addr+12, temp); /* Stack limit */
+ ARMul_WriteWord (state, addr, 0); /* Heap base */
+ ARMul_WriteWord (state, addr + 4, temp); /* Heap limit */
+ ARMul_WriteWord (state, addr + 8, temp); /* Stack base */
+ ARMul_WriteWord (state, addr + 12, temp); /* Stack limit */
return (TRUE);
case AngelSWI_Reason_ReportException:
state->Reg[0] = 0;
else
state->Reg[0] = -1;
- state->Emulate = FALSE ;
- return (TRUE);
+ state->Emulate = FALSE;
+ return TRUE;
case ADP_Stopped_ApplicationExit:
state->Reg[0] = 0;
- state->Emulate = FALSE ;
+ state->Emulate = FALSE;
return (TRUE);
-
+
case ADP_Stopped_RunTimeError:
state->Reg[0] = -1;
- state->Emulate = FALSE ;
+ state->Emulate = FALSE;
return (TRUE);
case AngelSWI_Reason_Errno:
return (TRUE);
case AngelSWI_Reason_Open:
- SWIopen(state,
- ARMul_ReadWord(state, addr),
- ARMul_ReadWord(state, addr+4));
+ SWIopen (state,
+ ARMul_ReadWord (state, addr),
+ ARMul_ReadWord (state, addr + 4));
return TRUE;
case AngelSWI_Reason_Read:
- SWIread(state,
- ARMul_ReadWord(state, addr),
- ARMul_ReadWord(state, addr+4),
- ARMul_ReadWord(state, addr+8));
+ SWIread (state,
+ ARMul_ReadWord (state, addr),
+ ARMul_ReadWord (state, addr + 4),
+ ARMul_ReadWord (state, addr + 8));
return TRUE;
case AngelSWI_Reason_Write:
- SWIwrite(state,
- ARMul_ReadWord(state, addr),
- ARMul_ReadWord(state, addr+4),
- ARMul_ReadWord(state, addr+8));
+ SWIwrite (state,
+ ARMul_ReadWord (state, addr),
+ ARMul_ReadWord (state, addr + 4),
+ ARMul_ReadWord (state, addr + 8));
return TRUE;
}
- default :
- state->Emulate = FALSE ;
- return(FALSE) ;
+ default:
+ state->Emulate = FALSE;
+ return (FALSE);
}
}
-#else /* CYGNUS LOCAL: #if 1 */
-
-unsigned
-ARMul_OSHandleSWI (ARMul_State *state, ARMword number)
-{
-#ifdef NOOS
- return(FALSE) ;
-#else
-#ifdef VALIDATE
- switch (number) {
- case 0x11 :
- state->Emulate = FALSE ;
- return(TRUE) ;
- case 0x01 :
- if (ARM32BITMODE)
- ARMul_SetCPSR(state, (ARMul_GetCPSR(state) & 0xffffffc0) | 0x13) ;
- else
- ARMul_SetCPSR(state, (ARMul_GetCPSR(state) & 0xffffffc0) | 0x3) ;
- return(TRUE) ;
- default :
- return(FALSE) ;
- }
-#else
- ARMword addr, temp ;
- char buffer[BUFFERSIZE], *cptr ;
- FILE *fptr ;
- struct OSblock* OSptr = (struct OSblock*)state->OSptr ;
-
- switch (number) {
- case SWI_WriteC :
- (void)fputc((int)state->Reg[0],stderr) ;
- OSptr->ErrorNo = errno ;
- return(TRUE) ;
-
- case SWI_Write0 :
- addr = state->Reg[0] ;
- while ((temp = ARMul_ReadByte(state,addr++)) != 0)
- fputc((char)temp,stderr) ;
- OSptr->ErrorNo = errno ;
- return(TRUE) ;
-
- case SWI_ReadC :
- state->Reg[0] = (ARMword)fgetc(stdin) ;
- OSptr->ErrorNo = errno ;
- return(TRUE) ;
-
- case SWI_CLI :
- addr = state->Reg[0] ;
- getstring(state,state->Reg[0],buffer) ;
- state->Reg[0] = (ARMword)system(buffer) ;
- OSptr->ErrorNo = errno ;
- return(TRUE) ;
-
- case SWI_GetEnv :
- state->Reg[0] = ADDRCMDLINE ;
- if (state->MemSize)
- state->Reg[1] = state->MemSize ;
- else
- state->Reg[1] = ADDRUSERSTACK ;
-
- addr = state->Reg[0] ;
- cptr = state->CommandLine ;
- if (cptr == NULL)
- cptr = "\0" ;
- do {
- temp = (ARMword)*cptr++ ;
- ARMul_WriteByte(state,addr++,temp) ;
- } while (temp != 0) ;
- return(TRUE) ;
-
- case SWI_Exit :
-#ifdef ASIM
- simkernel1_abort_run() ;
-#else
- state->Emulate = FALSE ;
-#endif
- return(TRUE) ;
-
- case SWI_EnterOS :
- if (ARM32BITMODE)
- ARMul_SetCPSR(state, (ARMul_GetCPSR(state) & 0xffffffc0) | 0x13) ;
- else
- ARMul_SetCPSR(state, (ARMul_GetCPSR(state) & 0xffffffc0) | 0x3) ;
- return(TRUE) ;
-
- case SWI_GetErrno :
- state->Reg[0] = OSptr->ErrorNo ;
- return(TRUE) ;
-
- case SWI_Clock :
- /* return muber of centi-seconds... */
- state->Reg[0] =
-#ifdef CLOCKS_PER_SEC
- (CLOCKS_PER_SEC >= 100)
- ? (ARMword) (clock() / (CLOCKS_PER_SEC / 100))
- : (ARMword) ((clock() * 100) / CLOCKS_PER_SEC) ;
-#else
- /* presume unix... clock() returns microseconds */
- (ARMword) (clock() / 10000) ;
-#endif
- OSptr->ErrorNo = errno ;
- return(TRUE) ;
-
- case SWI_Time :
- state->Reg[0] = (ARMword)time(NULL) ;
- OSptr->ErrorNo = errno ;
- return(TRUE) ;
-
- case SWI_Remove :
- getstring(state,state->Reg[0],buffer) ;
- state->Reg[0] = unlink(buffer) ;
- OSptr->ErrorNo = errno ;
- return(TRUE) ;
-
- case SWI_Rename : {
- char buffer2[BUFFERSIZE] ;
-
- getstring(state,state->Reg[0],buffer) ;
- getstring(state,state->Reg[1],buffer2) ;
- state->Reg[0] = rename(buffer,buffer2) ;
- OSptr->ErrorNo = errno ;
- return(TRUE) ;
- }
-
- case SWI_Open : {
-#if 0
- /* It seems to me that these are in the wrong order
- sac@cygnus.com, so I've redone it to use the
- flags instead, with the functionality which was already
- there -- ahh, perhaps the TRUNC bit is in a different
- place on the original host ?*/
- static char* fmode[] = {"r","rb","r+","r+b",
- "w","wb","w+","w+b",
- "a","ab","a+","a+b",
- "r","r","r","r"} /* last 4 are illegal */ ;
-#endif
-
- unsigned type ;
-
- type = (unsigned)(state->Reg[1] & 3L) ;
- getstring(state,state->Reg[0],buffer) ;
- if (strcmp(buffer,":tt")==0 && (type == O_RDONLY )) /* opening tty "r" */
- fptr = stdin ;
- else if (strcmp(buffer,":tt")==0 && (type == O_WRONLY)) /* opening tty "w" */
- fptr = stderr ;
- else
- {
- switch (type)
- {
- case O_RDONLY:
- fptr = fopen(buffer,"r") ;
- break;
- case O_WRONLY:
- fptr = fopen(buffer,"w") ;
- break;
- case O_RDWR:
- fptr = fopen(buffer,"rw") ;
- break;
- }
- }
-
- state->Reg[0] = 0 ;
- if (fptr != NULL) {
- for (temp = 0 ; temp < FOPEN_MAX ; temp++)
- if (OSptr->FileTable[temp] == NULL) {
- OSptr->FileTable[temp] = fptr ;
- OSptr->FileFlags[temp] = type & 1 ; /* preserve the binary bit */
- state->Reg[0] = (ARMword)(temp + 1) ;
- break ;
- }
- if (state->Reg[0] == 0)
- OSptr->ErrorNo = EMFILE ; /* too many open files */
- else
- OSptr->ErrorNo = errno ;
- }
- else
- OSptr->ErrorNo = errno ;
- return(TRUE) ;
- }
-
- case SWI_Close :
- temp = state->Reg[0] ;
- if (temp == 0 || temp > FOPEN_MAX || OSptr->FileTable[temp - 1] == 0) {
- OSptr->ErrorNo = EBADF ;
- state->Reg[0] = -1L ;
- return(TRUE) ;
- }
- temp-- ;
- fptr = OSptr->FileTable[temp] ;
- if (fptr == stdin || fptr == stderr)
- state->Reg[0] = 0 ;
- else
- state->Reg[0] = fclose(fptr) ;
- OSptr->FileTable[temp] = NULL ;
- OSptr->ErrorNo = errno ;
- return(TRUE) ;
-
- case SWI_Write : {
- unsigned size, upto, type ;
- char ch ;
-
- temp = state->Reg[0] ;
- if (temp == 0 || temp > FOPEN_MAX || OSptr->FileTable[temp - 1] == 0) {
- OSptr->ErrorNo = EBADF ;
- state->Reg[0] = -1L ;
- return(TRUE) ;
- }
- temp-- ;
- fptr = OSptr->FileTable[temp] ;
- type = OSptr->FileFlags[temp] ;
- addr = state->Reg[1] ;
- size = (unsigned)state->Reg[2] ;
-
- if (type & READOP)
- fseek(fptr,0L,SEEK_CUR) ;
- OSptr->FileFlags[temp] = (type & BINARY) | WRITEOP ; ;
- while (size > 0) {
- if (size >= BUFFERSIZE)
- upto = BUFFERSIZE ;
- else
- upto = size ;
- for (cptr = buffer ; (cptr - buffer) < upto ; cptr++) {
- ch = (char)ARMul_ReadByte(state,(ARMword)addr++) ;
- *cptr = FIXCRLF(type,ch) ;
- }
- temp = fwrite(buffer,1,upto,fptr) ;
- if (temp < upto) {
- state->Reg[0] = (ARMword)(size - temp) ;
- OSptr->ErrorNo = errno ;
- return(TRUE) ;
- }
- size -= upto ;
- }
- state->Reg[0] = 0 ;
- OSptr->ErrorNo = errno ;
- return(TRUE) ;
- }
-
- case SWI_Read : {
- unsigned size, upto, type ;
- char ch ;
-
- temp = state->Reg[0] ;
- if (temp == 0 || temp > FOPEN_MAX || OSptr->FileTable[temp - 1] == 0) {
- OSptr->ErrorNo = EBADF ;
- state->Reg[0] = -1L ;
- return(TRUE) ;
- }
- temp-- ;
- fptr = OSptr->FileTable[temp] ;
- addr = state->Reg[1] ;
- size = (unsigned)state->Reg[2] ;
- type = OSptr->FileFlags[temp] ;
-
- if (type & WRITEOP)
- fseek(fptr,0L,SEEK_CUR) ;
- OSptr->FileFlags[temp] = (type & BINARY) | READOP ; ;
- while (size > 0) {
- if (isatty_(fptr)) {
- upto = (size >= BUFFERSIZE)?BUFFERSIZE:size + 1 ;
- if (fgets(buffer, upto, fptr) != 0)
- temp = strlen(buffer) ;
- else
- temp = 0 ;
- upto-- ; /* 1 char used for terminating null */
- }
- else {
- upto = (size>=BUFFERSIZE)?BUFFERSIZE:size ;
- temp = fread(buffer,1,upto,fptr) ;
- }
- for (cptr = buffer ; (cptr - buffer) < temp ; cptr++) {
- ch = *cptr ;
- ARMul_WriteByte(state,(ARMword)addr++,FIXCRLF(type,ch)) ;
- }
- if (temp < upto) {
- state->Reg[0] = (ARMword)(size - temp) ;
- OSptr->ErrorNo = errno ;
- return(TRUE) ;
- }
- size -= upto ;
- }
- state->Reg[0] = 0 ;
- OSptr->ErrorNo = errno ;
- return(TRUE) ;
- }
-
- case SWI_Seek :
- if (state->Reg[0] == 0 || state->Reg[0] > FOPEN_MAX
- || OSptr->FileTable[state->Reg[0] - 1] == 0) {
- OSptr->ErrorNo = EBADF ;
- state->Reg[0] = -1L ;
- return(TRUE) ;
- }
- fptr = OSptr->FileTable[state->Reg[0] - 1] ;
- state->Reg[0] = fseek(fptr,(long)state->Reg[1],SEEK_SET) ;
- OSptr->ErrorNo = errno ;
- return(TRUE) ;
-
- case SWI_Flen :
- if (state->Reg[0] == 0 || state->Reg[0] > FOPEN_MAX
- || OSptr->FileTable[state->Reg[0] - 1] == 0) {
- OSptr->ErrorNo = EBADF ;
- state->Reg[0] = -1L ;
- return(TRUE) ;
- }
- fptr = OSptr->FileTable[state->Reg[0] - 1] ;
- addr = (ARMword)ftell(fptr) ;
- if (fseek(fptr,0L,SEEK_END) < 0)
- state->Reg[0] = -1 ;
- else {
- state->Reg[0] = (ARMword)ftell(fptr) ;
- (void)fseek(fptr,addr,SEEK_SET) ;
- }
- OSptr->ErrorNo = errno ;
- return(TRUE) ;
-
- case SWI_IsTTY :
- if (state->Reg[0] == 0 || state->Reg[0] > FOPEN_MAX
- || OSptr->FileTable[state->Reg[0] - 1] == 0) {
- OSptr->ErrorNo = EBADF ;
- state->Reg[0] = -1L ;
- return(TRUE) ;
- }
- fptr = OSptr->FileTable[state->Reg[0] - 1] ;
- state->Reg[0] = isatty_(fptr) ;
- OSptr->ErrorNo = errno ;
- return(TRUE) ;
-
- case SWI_TmpNam :{
- ARMword size ;
-
- addr = state->Reg[0] ;
- temp = state->Reg[1] & 0xff ;
- size = state->Reg[2] ;
- if (OSptr->tempnames[temp] == NULL) {
- if ((OSptr->tempnames[temp] = malloc(L_tmpnam)) == NULL) {
- state->Reg[0] = 0 ;
- return(TRUE) ;
- }
- (void)tmpnam(OSptr->tempnames[temp]) ;
- }
- cptr = OSptr->tempnames[temp] ;
- if (strlen(cptr) > state->Reg[2])
- state->Reg[0] = 0 ;
- else
- do {
- ARMul_WriteByte(state,addr++,*cptr) ;
- } while (*cptr++ != 0) ;
- OSptr->ErrorNo = errno ;
- return(TRUE) ;
- }
-
- case SWI_InstallHandler:
- { ARMword handlerp = ADDRSOFHANDLERS + state->Reg[0] * 8;
- ARMword oldr1 = ARMul_ReadWord(state, handlerp),
- oldr2 = ARMul_ReadWord(state, handlerp + 4);
- ARMul_WriteWord(state, handlerp, state->Reg[1]);
- ARMul_WriteWord(state, handlerp + 4, state->Reg[2]);
- state->Reg[1] = oldr1;
- state->Reg[2] = oldr2;
- return(TRUE);
- }
-
- case SWI_GenerateError:
- ARMul_Abort(state, ARMSWIV) ;
- if (state->Emulate)
- ARMul_SetR15(state, ARMul_ReadWord(state, ADDRSOFTVECTORS + ARMErrorV));
- return(TRUE);
-
-/* SWI's 0x9x unwind the state of the CPU after an abort of type x */
-
- case 0x90: /* Branch through zero */
- { ARMword oldpsr = ARMul_GetCPSR(state) ;
- ARMul_SetCPSR(state, (oldpsr & 0xffffffc0) | 0x13) ;
- ARMul_SetSPSR(state, SVC32MODE, oldpsr) ;
- state->Reg[14] = 0;
- goto TidyCommon;
- }
-
- case 0x98: /* Error */
- { ARMword errorp = state->Reg[0],
- regp = state->Reg[1];
- unsigned i;
- ARMword errorpsr = ARMul_ReadWord(state, regp + 16*4);
- for (i = 0; i < 15; i++)
- ARMul_SetReg(state,errorpsr,i,ARMul_ReadWord(state, regp + i*4L)) ;
- state->Reg[14] = ARMul_ReadWord(state, regp + 15*4L);
- state->Reg[10] = errorp;
- ARMul_SetSPSR(state,state->Mode,errorpsr) ;
- OSptr->ErrorP = errorp;
- goto TidyCommon;
- }
-
- case 0x94: /* Data abort */
- { ARMword addr = state->Reg[14] - 8;
- ARMword cpsr = ARMul_GetCPSR(state) ;
- if (ARM26BITMODE)
- addr = addr & 0x3fffffc ;
- ARMul_SetCPSR(state,ARMul_GetSPSR(state,cpsr)) ;
- UnwindDataAbort(state, addr);
- if (addr >= FPESTART && addr < FPEEND) { /* in the FPE */
- ARMword sp, spsr ;
- unsigned i ;
-
- sp = state->Reg[13] ;
- state->Reg[13] += 64 ; /* fix the aborting mode sp */
- state->Reg[14] = ARMul_ReadWord(state,sp + 60) ; /* and its lr */
- spsr = ARMul_GetSPSR(state,state->Mode) ;
- state->Mode = ARMul_SwitchMode(state, state->Mode, spsr);
- for (i = 0 ; i < 15 ; i++) {
- ARMul_SetReg(state,spsr,i,ARMul_ReadWord(state,sp)) ;
- sp += 4 ;
- }
- ARMul_SetCPSR(state,cpsr) ;
- state->Reg[14] = ARMul_ReadWord(state,sp) + 4 ; /* botch it */
- ARMul_SetSPSR(state,state->Mode,spsr) ;
- }
- else
- ARMul_SetCPSR(state,cpsr) ;
-
- /* and fall through to correct r14 */
- }
- case 0x95: /* Address Exception */
- state->Reg[14] -= 4;
- case 0x91: /* Undefined instruction */
- case 0x92: /* SWI */
- case 0x93: /* Prefetch abort */
- case 0x96: /* IRQ */
- case 0x97: /* FIQ */
- state->Reg[14] -= 4;
- TidyCommon:
- if (state->VectorCatch & (1 << (number - 0x90))) {
- ARMul_SetR15(state, state->Reg[14] + 8) ; /* the 8 is the pipelining the the RDI will undo */
- ARMul_SetCPSR(state,ARMul_GetSPSR(state,ARMul_GetCPSR(state))) ;
- if (number == 0x90)
- state->EndCondition = 10 ; /* Branch through Zero Error */
- else
- state->EndCondition = (unsigned)number - 0x8f;
- state->Emulate = FALSE ;
- }
- else {
- ARMword sp = state->Reg[13];
- ARMul_WriteWord(state, sp - 4, state->Reg[14]);
- ARMul_WriteWord(state, sp - 8, state->Reg[12]);
- ARMul_WriteWord(state, sp - 12, state->Reg[11]);
- ARMul_WriteWord(state, sp - 16, state->Reg[10]);
- state->Reg[13] = sp - 16;
- state->Reg[11] = ADDRSOFHANDLERS + 8 * (number - 0x90);
- }
- return(TRUE);
-
-/* SWI's 0x8x pass an abort of type x to the debugger if a handler returns */
-
- case 0x80: case 0x81: case 0x82: case 0x83:
- case 0x84: case 0x85: case 0x86: case 0x87: case 0x88:
- { ARMword sp = state->Reg[13];
- state->Reg[10] = ARMul_ReadWord(state, sp);
- state->Reg[11] = ARMul_ReadWord(state, sp + 4);
- state->Reg[12] = ARMul_ReadWord(state, sp + 8);
- state->Reg[14] = ARMul_ReadWord(state, sp + 12);
- state->Reg[13] = sp + 16;
- ARMul_SetR15(state, state->Reg[14] + 8) ; /* the 8 is the pipelining the the RDI will undo */
- ARMul_SetCPSR(state,ARMul_GetSPSR(state,ARMul_GetCPSR(state))) ;
- if (number == 0x80)
- state->EndCondition = 10 ; /* Branch through Zero Error */
- else
- state->EndCondition = (unsigned)number - 0x7f;
- state->Emulate = FALSE ;
- return(TRUE);
- }
-
- default :
- state->Emulate = FALSE ;
- return(FALSE) ;
- }
-#endif
-#endif
- }
-#endif /* CYGNUS LOCAL: #if 1 */
-
#ifndef NOOS
#ifndef ASIM
* be ignored (so set state->Emulate to FALSE!). *
\***************************************************************************/
-unsigned
-ARMul_OSException (ARMul_State *state, ARMword vector, ARMword pc)
-{ /* don't use this here */
- return(FALSE) ;
+unsigned
+ARMul_OSException (ARMul_State * state ATTRIBUTE_UNUSED, ARMword vector ATTRIBUTE_UNUSED, ARMword pc ATTRIBUTE_UNUSED)
+{ /* don't use this here */
+ return (FALSE);
}
#endif
-/***************************************************************************\
-* Unwind a data abort *
-\***************************************************************************/
-
-static void
-UnwindDataAbort (ARMul_State *state, ARMword addr)
-{
- ARMword instr = ARMul_ReadWord(state, addr);
- ARMword rn = BITS(16, 19);
- ARMword itype = BITS(24, 27);
- ARMword offset;
- if (rn == 15) return;
- if (itype == 8 || itype == 9) {
- /* LDM or STM */
- unsigned long regs = BITS(0, 15);
- offset = 0;
- if (!BIT(21)) return; /* no wb */
- for (; regs != 0; offset++)
- regs ^= (regs & -regs);
- if (offset == 0) offset = 16;
- } else if (itype == 12 || /* post-indexed CPDT */
- (itype == 13 && BIT(21))) { /* pre_indexed CPDT with WB */
- offset = BITS(0, 7);
- } else
- return;
-
- if (BIT(23))
- state->Reg[rn] -= offset * 4;
- else
- state->Reg[rn] += offset * 4;
-}
-
-/***************************************************************************\
-* Copy a string from the debuggee's memory to the host's *
-\***************************************************************************/
-
-static void
-getstring (ARMul_State *state, ARMword from, char *to)
-{
- do
- {
- *to = (char) ARMul_ReadByte (state, from++);
- } while (*to++ != '\0');
-}
#endif /* NOOS */
#include "armdefs.h"
#include "armemu.h"
+#include "ansidecl.h"
/***************************************************************************\
* Definitions for the support routines *
\***************************************************************************/
-ARMword ARMul_GetReg(ARMul_State *state, unsigned mode, unsigned reg) ;
-void ARMul_SetReg(ARMul_State *state, unsigned mode, unsigned reg, ARMword value) ;
-ARMword ARMul_GetPC(ARMul_State *state) ;
-ARMword ARMul_GetNextPC(ARMul_State *state) ;
-void ARMul_SetPC(ARMul_State *state, ARMword value) ;
-ARMword ARMul_GetR15(ARMul_State *state) ;
-void ARMul_SetR15(ARMul_State *state, ARMword value) ;
-
-ARMword ARMul_GetCPSR(ARMul_State *state) ;
-void ARMul_SetCPSR(ARMul_State *state, ARMword value) ;
-void ARMul_FixCPSR(ARMul_State *state, ARMword instr, ARMword rhs) ;
-ARMword ARMul_GetSPSR(ARMul_State *state, ARMword mode) ;
-void ARMul_SetSPSR(ARMul_State *state, ARMword mode, ARMword value) ;
-void ARMul_FixSPSR(ARMul_State *state, ARMword instr, ARMword rhs) ;
-
-void ARMul_CPSRAltered(ARMul_State *state) ;
-void ARMul_R15Altered(ARMul_State *state) ;
-
-ARMword ARMul_SwitchMode(ARMul_State *state,ARMword oldmode, ARMword newmode) ;
-static ARMword ModeToBank(ARMul_State *state,ARMword mode) ;
-
-unsigned ARMul_NthReg(ARMword instr, unsigned number) ;
-
-void ARMul_NegZero(ARMul_State *state, ARMword result) ;
-void ARMul_AddCarry(ARMul_State *state, ARMword a, ARMword b, ARMword result) ;
-void ARMul_AddOverflow(ARMul_State *state, ARMword a, ARMword b, ARMword result) ;
-void ARMul_SubCarry(ARMul_State *state, ARMword a, ARMword b, ARMword result) ;
-void ARMul_SubOverflow(ARMul_State *state, ARMword a, ARMword b, ARMword result) ;
-
-void ARMul_LDC(ARMul_State *state,ARMword instr,ARMword address) ;
-void ARMul_STC(ARMul_State *state,ARMword instr,ARMword address) ;
-void ARMul_MCR(ARMul_State *state,ARMword instr, ARMword source) ;
-ARMword ARMul_MRC(ARMul_State *state,ARMword instr) ;
-void ARMul_CDP(ARMul_State *state,ARMword instr) ;
-void ARMul_UndefInstr(ARMul_State *state,ARMword instr) ;
-unsigned IntPending(ARMul_State *state) ;
-
-ARMword ARMul_Align(ARMul_State *state, ARMword address, ARMword data) ;
-
-void ARMul_ScheduleEvent(ARMul_State *state, unsigned long delay,
- unsigned (*what)()) ;
-void ARMul_EnvokeEvent(ARMul_State *state) ;
-unsigned long ARMul_Time(ARMul_State *state) ;
-static void EnvokeList(ARMul_State *state, unsigned long from, unsigned long to) ;
-
-struct EventNode { /* An event list node */
- unsigned (*func)() ; /* The function to call */
- struct EventNode *next ;
- } ;
+ARMword ARMul_GetReg (ARMul_State * state, unsigned mode, unsigned reg);
+void ARMul_SetReg (ARMul_State * state, unsigned mode, unsigned reg,
+ ARMword value);
+ARMword ARMul_GetPC (ARMul_State * state);
+ARMword ARMul_GetNextPC (ARMul_State * state);
+void ARMul_SetPC (ARMul_State * state, ARMword value);
+ARMword ARMul_GetR15 (ARMul_State * state);
+void ARMul_SetR15 (ARMul_State * state, ARMword value);
+
+ARMword ARMul_GetCPSR (ARMul_State * state);
+void ARMul_SetCPSR (ARMul_State * state, ARMword value);
+ARMword ARMul_GetSPSR (ARMul_State * state, ARMword mode);
+void ARMul_SetSPSR (ARMul_State * state, ARMword mode, ARMword value);
+
+void ARMul_CPSRAltered (ARMul_State * state);
+void ARMul_R15Altered (ARMul_State * state);
+
+ARMword ARMul_SwitchMode (ARMul_State * state, ARMword oldmode,
+ ARMword newmode);
+static ARMword ModeToBank (ARMul_State * state, ARMword mode);
+
+unsigned ARMul_NthReg (ARMword instr, unsigned number);
+
+void ARMul_NegZero (ARMul_State * state, ARMword result);
+void ARMul_AddCarry (ARMul_State * state, ARMword a, ARMword b,
+ ARMword result);
+void ARMul_AddOverflow (ARMul_State * state, ARMword a, ARMword b,
+ ARMword result);
+void ARMul_SubCarry (ARMul_State * state, ARMword a, ARMword b,
+ ARMword result);
+void ARMul_SubOverflow (ARMul_State * state, ARMword a, ARMword b,
+ ARMword result);
+
+void ARMul_LDC (ARMul_State * state, ARMword instr, ARMword address);
+void ARMul_STC (ARMul_State * state, ARMword instr, ARMword address);
+void ARMul_MCR (ARMul_State * state, ARMword instr, ARMword source);
+ARMword ARMul_MRC (ARMul_State * state, ARMword instr);
+void ARMul_CDP (ARMul_State * state, ARMword instr);
+unsigned IntPending (ARMul_State * state);
+
+ARMword ARMul_Align (ARMul_State * state, ARMword address, ARMword data);
+
+void ARMul_ScheduleEvent (ARMul_State * state, unsigned long delay,
+ unsigned (*what) ());
+void ARMul_EnvokeEvent (ARMul_State * state);
+unsigned long ARMul_Time (ARMul_State * state);
+static void EnvokeList (ARMul_State * state, unsigned long from,
+ unsigned long to);
+
+struct EventNode
+{ /* An event list node */
+ unsigned (*func) (); /* The function to call */
+ struct EventNode *next;
+};
/***************************************************************************\
* This routine returns the value of a register from a mode. *
\***************************************************************************/
-ARMword ARMul_GetReg(ARMul_State *state, unsigned mode, unsigned reg)
-{mode &= MODEBITS ;
- if (mode != state->Mode)
- return(state->RegBank[ModeToBank(state,(ARMword)mode)][reg]) ;
- else
- return(state->Reg[reg]) ;
+ARMword
+ARMul_GetReg (ARMul_State * state, unsigned mode, unsigned reg)
+{
+ mode &= MODEBITS;
+ if (mode != state->Mode)
+ return (state->RegBank[ModeToBank (state, (ARMword) mode)][reg]);
+ else
+ return (state->Reg[reg]);
}
/***************************************************************************\
* This routine sets the value of a register for a mode. *
\***************************************************************************/
-void ARMul_SetReg(ARMul_State *state, unsigned mode, unsigned reg, ARMword value)
-{mode &= MODEBITS ;
- if (mode != state->Mode)
- state->RegBank[ModeToBank(state,(ARMword)mode)][reg] = value ;
- else
- state->Reg[reg] = value ;
+void
+ARMul_SetReg (ARMul_State * state, unsigned mode, unsigned reg, ARMword value)
+{
+ mode &= MODEBITS;
+ if (mode != state->Mode)
+ state->RegBank[ModeToBank (state, (ARMword) mode)][reg] = value;
+ else
+ state->Reg[reg] = value;
}
/***************************************************************************\
* This routine returns the value of the PC, mode independently. *
\***************************************************************************/
-ARMword ARMul_GetPC(ARMul_State *state)
-{if (state->Mode > SVC26MODE)
- return(state->Reg[15]) ;
- else
- return(R15PC) ;
+ARMword
+ARMul_GetPC (ARMul_State * state)
+{
+ if (state->Mode > SVC26MODE)
+ return (state->Reg[15]);
+ else
+ return (R15PC);
}
/***************************************************************************\
* This routine returns the value of the PC, mode independently. *
\***************************************************************************/
-ARMword ARMul_GetNextPC(ARMul_State *state)
-{if (state->Mode > SVC26MODE)
- return(state->Reg[15] + isize) ;
- else
- return((state->Reg[15] + isize) & R15PCBITS) ;
+ARMword
+ARMul_GetNextPC (ARMul_State * state)
+{
+ if (state->Mode > SVC26MODE)
+ return (state->Reg[15] + isize);
+ else
+ return ((state->Reg[15] + isize) & R15PCBITS);
}
/***************************************************************************\
* This routine sets the value of the PC. *
\***************************************************************************/
-void ARMul_SetPC(ARMul_State *state, ARMword value)
-{if (ARMul_MODE32BIT)
- state->Reg[15] = value & PCBITS ;
- else
- state->Reg[15] = R15CCINTMODE | (value & R15PCBITS) ;
- FLUSHPIPE ;
+void
+ARMul_SetPC (ARMul_State * state, ARMword value)
+{
+ if (ARMul_MODE32BIT)
+ state->Reg[15] = value & PCBITS;
+ else
+ state->Reg[15] = R15CCINTMODE | (value & R15PCBITS);
+ FLUSHPIPE;
}
/***************************************************************************\
* This routine returns the value of register 15, mode independently. *
\***************************************************************************/
-ARMword ARMul_GetR15(ARMul_State *state)
-{if (state->Mode > SVC26MODE)
- return(state->Reg[15]) ;
- else
- return(R15PC | ECC | ER15INT | EMODE) ;
+ARMword
+ARMul_GetR15 (ARMul_State * state)
+{
+ if (state->Mode > SVC26MODE)
+ return (state->Reg[15]);
+ else
+ return (R15PC | ECC | ER15INT | EMODE);
}
/***************************************************************************\
* This routine sets the value of Register 15. *
\***************************************************************************/
-void ARMul_SetR15(ARMul_State *state, ARMword value)
+void
+ARMul_SetR15 (ARMul_State * state, ARMword value)
{
- if (ARMul_MODE32BIT)
- state->Reg[15] = value & PCBITS ;
- else {
- state->Reg[15] = value ;
- ARMul_R15Altered(state) ;
+ if (ARMul_MODE32BIT)
+ state->Reg[15] = value & PCBITS;
+ else
+ {
+ state->Reg[15] = value;
+ ARMul_R15Altered (state);
}
- FLUSHPIPE ;
+ FLUSHPIPE;
}
/***************************************************************************\
* This routine returns the value of the CPSR *
\***************************************************************************/
-ARMword ARMul_GetCPSR(ARMul_State *state)
+ARMword
+ARMul_GetCPSR (ARMul_State * state)
{
- return(CPSR) ;
- }
+ return (CPSR);
+}
/***************************************************************************\
* This routine sets the value of the CPSR *
\***************************************************************************/
-void ARMul_SetCPSR(ARMul_State *state, ARMword value)
-{state->Cpsr = CPSR ;
- SETPSR(state->Cpsr,value) ;
- ARMul_CPSRAltered(state) ;
- }
+void
+ARMul_SetCPSR (ARMul_State * state, ARMword value)
+{
+ state->Cpsr = CPSR;
+ SETPSR (state->Cpsr, value);
+ ARMul_CPSRAltered (state);
+}
/***************************************************************************\
* This routine does all the nasty bits involved in a write to the CPSR, *
* including updating the register bank, given a MSR instruction. *
\***************************************************************************/
-void ARMul_FixCPSR(ARMul_State *state, ARMword instr, ARMword rhs)
-{state->Cpsr = CPSR ;
- if (state->Bank==USERBANK) { /* Only write flags in user mode */
- if (BIT(19)) {
- SETCC(state->Cpsr,rhs) ;
- }
+void
+ARMul_FixCPSR (ARMul_State * state, ARMword instr, ARMword rhs)
+{
+ state->Cpsr = CPSR;
+ if (state->Bank == USERBANK)
+ { /* Only write flags in user mode */
+ if (BIT (19))
+ {
+ SETCC (state->Cpsr, rhs);
+ }
}
- else { /* Not a user mode */
- if (BITS(16,19)==9) SETPSR(state->Cpsr,rhs) ;
- else if (BIT(16)) SETINTMODE(state->Cpsr,rhs) ;
- else if (BIT(19)) SETCC(state->Cpsr,rhs) ;
+ else
+ { /* Not a user mode */
+ if (BITS (16, 19) == 9)
+ SETPSR (state->Cpsr, rhs);
+ else if (BIT (16))
+ SETINTMODE (state->Cpsr, rhs);
+ else if (BIT (19))
+ SETCC (state->Cpsr, rhs);
}
- ARMul_CPSRAltered(state) ;
- }
+ ARMul_CPSRAltered (state);
+}
/***************************************************************************\
* Get an SPSR from the specified mode *
\***************************************************************************/
-ARMword ARMul_GetSPSR(ARMul_State *state, ARMword mode)
-{ARMword bank = ModeToBank(state,mode & MODEBITS) ;
- if (bank == USERBANK || bank == DUMMYBANK)
- return(CPSR) ;
- else
- return(state->Spsr[bank]) ;
+ARMword
+ARMul_GetSPSR (ARMul_State * state, ARMword mode)
+{
+ ARMword bank = ModeToBank (state, mode & MODEBITS);
+ if (bank == USERBANK || bank == DUMMYBANK)
+ return (CPSR);
+ else
+ return (state->Spsr[bank]);
}
/***************************************************************************\
* This routine does a write to an SPSR *
\***************************************************************************/
-void ARMul_SetSPSR(ARMul_State *state, ARMword mode, ARMword value)
-{ARMword bank = ModeToBank(state,mode & MODEBITS) ;
- if (bank != USERBANK && bank !=DUMMYBANK)
- state->Spsr[bank] = value ;
+void
+ARMul_SetSPSR (ARMul_State * state, ARMword mode, ARMword value)
+{
+ ARMword bank = ModeToBank (state, mode & MODEBITS);
+ if (bank != USERBANK && bank != DUMMYBANK)
+ state->Spsr[bank] = value;
}
/***************************************************************************\
* This routine does a write to the current SPSR, given an MSR instruction *
\***************************************************************************/
-void ARMul_FixSPSR(ARMul_State *state, ARMword instr, ARMword rhs)
-{if (state->Bank != USERBANK && state->Bank !=DUMMYBANK) {
- if (BITS(16,19)==9) SETPSR(state->Spsr[state->Bank],rhs) ;
- else if (BIT(16)) SETINTMODE(state->Spsr[state->Bank],rhs) ;
- else if (BIT(19)) SETCC(state->Spsr[state->Bank],rhs) ;
+void
+ARMul_FixSPSR (ARMul_State * state, ARMword instr, ARMword rhs)
+{
+ if (state->Bank != USERBANK && state->Bank != DUMMYBANK)
+ {
+ if (BITS (16, 19) == 9)
+ SETPSR (state->Spsr[state->Bank], rhs);
+ else if (BIT (16))
+ SETINTMODE (state->Spsr[state->Bank], rhs);
+ else if (BIT (19))
+ SETCC (state->Spsr[state->Bank], rhs);
}
}
* changed. Both the processor flags and register bank are updated. *
\***************************************************************************/
-void ARMul_CPSRAltered(ARMul_State *state)
-{ARMword oldmode ;
-
- if (state->prog32Sig == LOW)
- state->Cpsr &= (CCBITS | INTBITS | R15MODEBITS) ;
- oldmode = state->Mode ;
- if (state->Mode != (state->Cpsr & MODEBITS)) {
- state->Mode = ARMul_SwitchMode(state,state->Mode,state->Cpsr & MODEBITS) ;
- state->NtransSig = (state->Mode & 3)?HIGH:LOW ;
+void
+ARMul_CPSRAltered (ARMul_State * state)
+{
+ ARMword oldmode;
+
+ if (state->prog32Sig == LOW)
+ state->Cpsr &= (CCBITS | INTBITS | R15MODEBITS);
+ oldmode = state->Mode;
+ if (state->Mode != (state->Cpsr & MODEBITS))
+ {
+ state->Mode =
+ ARMul_SwitchMode (state, state->Mode, state->Cpsr & MODEBITS);
+ state->NtransSig = (state->Mode & 3) ? HIGH : LOW;
}
- ASSIGNINT(state->Cpsr & INTBITS) ;
- ASSIGNN((state->Cpsr & NBIT) != 0) ;
- ASSIGNZ((state->Cpsr & ZBIT) != 0) ;
- ASSIGNC((state->Cpsr & CBIT) != 0) ;
- ASSIGNV((state->Cpsr & VBIT) != 0) ;
+ ASSIGNINT (state->Cpsr & INTBITS);
+ ASSIGNN ((state->Cpsr & NBIT) != 0);
+ ASSIGNZ ((state->Cpsr & ZBIT) != 0);
+ ASSIGNC ((state->Cpsr & CBIT) != 0);
+ ASSIGNV ((state->Cpsr & VBIT) != 0);
#ifdef MODET
- ASSIGNT((state->Cpsr & TBIT) != 0);
+ ASSIGNT ((state->Cpsr & TBIT) != 0);
#endif
- if (oldmode > SVC26MODE) {
- if (state->Mode <= SVC26MODE) {
- state->Emulate = CHANGEMODE ;
- state->Reg[15] = ECC | ER15INT | EMODE | R15PC ;
- }
+ if (oldmode > SVC26MODE)
+ {
+ if (state->Mode <= SVC26MODE)
+ {
+ state->Emulate = CHANGEMODE;
+ state->Reg[15] = ECC | ER15INT | EMODE | R15PC;
+ }
}
- else {
- if (state->Mode > SVC26MODE) {
- state->Emulate = CHANGEMODE ;
- state->Reg[15] = R15PC ;
- }
- else
- state->Reg[15] = ECC | ER15INT | EMODE | R15PC ;
+ else
+ {
+ if (state->Mode > SVC26MODE)
+ {
+ state->Emulate = CHANGEMODE;
+ state->Reg[15] = R15PC;
+ }
+ else
+ state->Reg[15] = ECC | ER15INT | EMODE | R15PC;
}
}
* This routine should only be called from a 26 bit mode. *
\***************************************************************************/
-void ARMul_R15Altered(ARMul_State *state)
+void
+ARMul_R15Altered (ARMul_State * state)
{
- if (state->Mode != R15MODE) {
- state->Mode = ARMul_SwitchMode(state,state->Mode,R15MODE) ;
- state->NtransSig = (state->Mode & 3)?HIGH:LOW ;
+ if (state->Mode != R15MODE)
+ {
+ state->Mode = ARMul_SwitchMode (state, state->Mode, R15MODE);
+ state->NtransSig = (state->Mode & 3) ? HIGH : LOW;
}
- if (state->Mode > SVC26MODE)
- state->Emulate = CHANGEMODE ;
- ASSIGNR15INT(R15INT) ;
- ASSIGNN((state->Reg[15] & NBIT) != 0) ;
- ASSIGNZ((state->Reg[15] & ZBIT) != 0) ;
- ASSIGNC((state->Reg[15] & CBIT) != 0) ;
- ASSIGNV((state->Reg[15] & VBIT) != 0) ;
+ if (state->Mode > SVC26MODE)
+ state->Emulate = CHANGEMODE;
+ ASSIGNR15INT (R15INT);
+ ASSIGNN ((state->Reg[15] & NBIT) != 0);
+ ASSIGNZ ((state->Reg[15] & ZBIT) != 0);
+ ASSIGNC ((state->Reg[15] & CBIT) != 0);
+ ASSIGNV ((state->Reg[15] & VBIT) != 0);
}
/***************************************************************************\
* Notice the side effect of changing the Bank variable. *
\***************************************************************************/
-ARMword ARMul_SwitchMode(ARMul_State *state,ARMword oldmode, ARMword newmode)
-{unsigned i ;
-
- oldmode = ModeToBank(state,oldmode) ;
- state->Bank = ModeToBank(state,newmode) ;
- if (oldmode != state->Bank) { /* really need to do it */
- switch (oldmode) { /* save away the old registers */
- case USERBANK :
- case IRQBANK :
- case SVCBANK :
- case ABORTBANK :
- case UNDEFBANK : if (state->Bank == FIQBANK)
- for (i = 8 ; i < 13 ; i++)
- state->RegBank[USERBANK][i] = state->Reg[i] ;
- state->RegBank[oldmode][13] = state->Reg[13] ;
- state->RegBank[oldmode][14] = state->Reg[14] ;
- break ;
- case FIQBANK : for (i = 8 ; i < 15 ; i++)
- state->RegBank[FIQBANK][i] = state->Reg[i] ;
- break ;
- case DUMMYBANK : for (i = 8 ; i < 15 ; i++)
- state->RegBank[DUMMYBANK][i] = 0 ;
- break ;
-
- }
- switch (state->Bank) { /* restore the new registers */
- case USERBANK :
- case IRQBANK :
- case SVCBANK :
- case ABORTBANK :
- case UNDEFBANK : if (oldmode == FIQBANK)
- for (i = 8 ; i < 13 ; i++)
- state->Reg[i] = state->RegBank[USERBANK][i] ;
- state->Reg[13] = state->RegBank[state->Bank][13] ;
- state->Reg[14] = state->RegBank[state->Bank][14] ;
- break ;
- case FIQBANK : for (i = 8 ; i < 15 ; i++)
- state->Reg[i] = state->RegBank[FIQBANK][i] ;
- break ;
- case DUMMYBANK : for (i = 8 ; i < 15 ; i++)
- state->Reg[i] = 0 ;
- break ;
- } /* switch */
- } /* if */
- return(newmode) ;
+ARMword
+ARMul_SwitchMode (ARMul_State * state, ARMword oldmode, ARMword newmode)
+{
+ unsigned i;
+
+ oldmode = ModeToBank (state, oldmode);
+ state->Bank = ModeToBank (state, newmode);
+ if (oldmode != state->Bank)
+ { /* really need to do it */
+ switch (oldmode)
+ { /* save away the old registers */
+ case USERBANK:
+ case IRQBANK:
+ case SVCBANK:
+ case ABORTBANK:
+ case UNDEFBANK:
+ if (state->Bank == FIQBANK)
+ for (i = 8; i < 13; i++)
+ state->RegBank[USERBANK][i] = state->Reg[i];
+ state->RegBank[oldmode][13] = state->Reg[13];
+ state->RegBank[oldmode][14] = state->Reg[14];
+ break;
+ case FIQBANK:
+ for (i = 8; i < 15; i++)
+ state->RegBank[FIQBANK][i] = state->Reg[i];
+ break;
+ case DUMMYBANK:
+ for (i = 8; i < 15; i++)
+ state->RegBank[DUMMYBANK][i] = 0;
+ break;
+
+ }
+ switch (state->Bank)
+ { /* restore the new registers */
+ case USERBANK:
+ case IRQBANK:
+ case SVCBANK:
+ case ABORTBANK:
+ case UNDEFBANK:
+ if (oldmode == FIQBANK)
+ for (i = 8; i < 13; i++)
+ state->Reg[i] = state->RegBank[USERBANK][i];
+ state->Reg[13] = state->RegBank[state->Bank][13];
+ state->Reg[14] = state->RegBank[state->Bank][14];
+ break;
+ case FIQBANK:
+ for (i = 8; i < 15; i++)
+ state->Reg[i] = state->RegBank[FIQBANK][i];
+ break;
+ case DUMMYBANK:
+ for (i = 8; i < 15; i++)
+ state->Reg[i] = 0;
+ break;
+ } /* switch */
+ } /* if */
+ return (newmode);
}
/***************************************************************************\
* will be accessed in that mode. *
\***************************************************************************/
-static ARMword ModeToBank(ARMul_State *state, ARMword mode)
-{static ARMword bankofmode[] = {USERBANK, FIQBANK, IRQBANK, SVCBANK,
- DUMMYBANK, DUMMYBANK, DUMMYBANK, DUMMYBANK,
- DUMMYBANK, DUMMYBANK, DUMMYBANK, DUMMYBANK,
- DUMMYBANK, DUMMYBANK, DUMMYBANK, DUMMYBANK,
- USERBANK, FIQBANK, IRQBANK, SVCBANK,
- DUMMYBANK, DUMMYBANK, DUMMYBANK, ABORTBANK,
- DUMMYBANK, DUMMYBANK, DUMMYBANK, UNDEFBANK
- } ;
-
- if (mode > UNDEF32MODE)
- return(DUMMYBANK) ;
- else
- return(bankofmode[mode]) ;
- }
+static ARMword
+ModeToBank (ARMul_State * state ATTRIBUTE_UNUSED, ARMword mode)
+{
+ static ARMword bankofmode[] = { USERBANK, FIQBANK, IRQBANK, SVCBANK,
+ DUMMYBANK, DUMMYBANK, DUMMYBANK, DUMMYBANK,
+ DUMMYBANK, DUMMYBANK, DUMMYBANK, DUMMYBANK,
+ DUMMYBANK, DUMMYBANK, DUMMYBANK, DUMMYBANK,
+ USERBANK, FIQBANK, IRQBANK, SVCBANK,
+ DUMMYBANK, DUMMYBANK, DUMMYBANK, ABORTBANK,
+ DUMMYBANK, DUMMYBANK, DUMMYBANK, UNDEFBANK
+ };
+
+ if (mode > UNDEF32MODE)
+ return (DUMMYBANK);
+ else
+ return (bankofmode[mode]);
+}
/***************************************************************************\
* Returns the register number of the nth register in a reg list. *
\***************************************************************************/
-unsigned ARMul_NthReg(ARMword instr, unsigned number)
-{unsigned bit, upto ;
+unsigned
+ARMul_NthReg (ARMword instr, unsigned number)
+{
+ unsigned bit, upto;
- for (bit = 0, upto = 0 ; upto <= number ; bit++)
- if (BIT(bit)) upto++ ;
- return(bit - 1) ;
+ for (bit = 0, upto = 0; upto <= number; bit++)
+ if (BIT (bit))
+ upto++;
+ return (bit - 1);
}
/***************************************************************************\
* Assigns the N and Z flags depending on the value of result *
\***************************************************************************/
-void ARMul_NegZero(ARMul_State *state, ARMword result)
+void
+ARMul_NegZero (ARMul_State * state, ARMword result)
{
- if (NEG(result)) { SETN ; CLEARZ ; }
- else if (result == 0) { CLEARN ; SETZ ; }
- else { CLEARN ; CLEARZ ; } ;
- }
+ if (NEG (result))
+ {
+ SETN;
+ CLEARZ;
+ }
+ else if (result == 0)
+ {
+ CLEARN;
+ SETZ;
+ }
+ else
+ {
+ CLEARN;
+ CLEARZ;
+ };
+}
+
+/* Compute whether an addition of A and B, giving RESULT, overflowed. */
+int
+AddOverflow (ARMword a, ARMword b, ARMword result)
+{
+ return ((NEG (a) && NEG (b) && POS (result))
+ || (POS (a) && POS (b) && NEG (result)));
+}
+
+/* Compute whether a subtraction of A and B, giving RESULT, overflowed. */
+int
+SubOverflow (ARMword a, ARMword b, ARMword result)
+{
+ return ((NEG (a) && POS (b) && POS (result))
+ || (POS (a) && NEG (b) && NEG (result)));
+}
/***************************************************************************\
* Assigns the C flag after an addition of a and b to give result *
\***************************************************************************/
-void ARMul_AddCarry(ARMul_State *state, ARMword a,ARMword b,ARMword result)
+void
+ARMul_AddCarry (ARMul_State * state, ARMword a, ARMword b, ARMword result)
{
- ASSIGNC( (NEG(a) && NEG(b)) ||
- (NEG(a) && POS(result)) ||
- (NEG(b) && POS(result)) ) ;
- }
+ ASSIGNC ((NEG (a) && NEG (b)) ||
+ (NEG (a) && POS (result)) || (NEG (b) && POS (result)));
+}
/***************************************************************************\
* Assigns the V flag after an addition of a and b to give result *
\***************************************************************************/
-void ARMul_AddOverflow(ARMul_State *state, ARMword a,ARMword b,ARMword result)
+void
+ARMul_AddOverflow (ARMul_State * state, ARMword a, ARMword b, ARMword result)
{
- ASSIGNV( (NEG(a) && NEG(b) && POS(result)) ||
- (POS(a) && POS(b) && NEG(result)) ) ;
- }
+ ASSIGNV (AddOverflow (a, b, result));
+}
/***************************************************************************\
* Assigns the C flag after an subtraction of a and b to give result *
\***************************************************************************/
-void ARMul_SubCarry(ARMul_State *state, ARMword a,ARMword b,ARMword result)
+void
+ARMul_SubCarry (ARMul_State * state, ARMword a, ARMword b, ARMword result)
{
-ASSIGNC( (NEG(a) && POS(b)) ||
- (NEG(a) && POS(result)) ||
- (POS(b) && POS(result)) ) ;
+ ASSIGNC ((NEG (a) && POS (b)) ||
+ (NEG (a) && POS (result)) || (POS (b) && POS (result)));
}
/***************************************************************************\
* Assigns the V flag after an subtraction of a and b to give result *
\***************************************************************************/
-void ARMul_SubOverflow(ARMul_State *state,ARMword a,ARMword b,ARMword result)
+void
+ARMul_SubOverflow (ARMul_State * state, ARMword a, ARMword b, ARMword result)
{
-ASSIGNV( (NEG(a) && POS(b) && POS(result)) ||
- (POS(a) && NEG(b) && NEG(result)) ) ;
+ ASSIGNV (SubOverflow (a, b, result));
}
/***************************************************************************\
* modification. It also handles the Busy-Waiting. *
\***************************************************************************/
-void ARMul_LDC(ARMul_State *state,ARMword instr,ARMword address)
-{unsigned cpab ;
- ARMword data ;
+void
+ARMul_LDC (ARMul_State * state, ARMword instr, ARMword address)
+{
+ unsigned cpab;
+ ARMword data;
- UNDEF_LSCPCBaseWb ;
- if (ADDREXCEPT(address)) {
- INTERNALABORT(address) ;
+ UNDEF_LSCPCBaseWb;
+ if (ADDREXCEPT (address))
+ {
+ INTERNALABORT (address);
}
- cpab = (state->LDC[CPNum])(state,ARMul_FIRST,instr,0) ;
- while (cpab == ARMul_BUSY) {
- ARMul_Icycles(state,1,0) ;
- if (IntPending(state)) {
- cpab = (state->LDC[CPNum])(state,ARMul_INTERRUPT,instr,0) ;
- return ;
- }
- else
- cpab = (state->LDC[CPNum])(state,ARMul_BUSY,instr,0) ;
+ cpab = (state->LDC[CPNum]) (state, ARMul_FIRST, instr, 0);
+ while (cpab == ARMul_BUSY)
+ {
+ ARMul_Icycles (state, 1, 0);
+ if (IntPending (state))
+ {
+ cpab = (state->LDC[CPNum]) (state, ARMul_INTERRUPT, instr, 0);
+ return;
+ }
+ else
+ cpab = (state->LDC[CPNum]) (state, ARMul_BUSY, instr, 0);
}
- if (cpab == ARMul_CANT) {
- CPTAKEABORT ;
- return ;
+ if (cpab == ARMul_CANT)
+ {
+ CPTAKEABORT;
+ return;
}
- cpab = (state->LDC[CPNum])(state,ARMul_TRANSFER,instr,0) ;
- data = ARMul_LoadWordN(state,address) ;
- BUSUSEDINCPCN ;
- if (BIT(21))
- LSBase = state->Base ;
- cpab = (state->LDC[CPNum])(state,ARMul_DATA,instr,data) ;
- while (cpab == ARMul_INC) {
- address += 4 ;
- data = ARMul_LoadWordN(state,address) ;
- cpab = (state->LDC[CPNum])(state,ARMul_DATA,instr,data) ;
+ cpab = (state->LDC[CPNum]) (state, ARMul_TRANSFER, instr, 0);
+ data = ARMul_LoadWordN (state, address);
+ BUSUSEDINCPCN;
+ if (BIT (21))
+ LSBase = state->Base;
+ cpab = (state->LDC[CPNum]) (state, ARMul_DATA, instr, data);
+ while (cpab == ARMul_INC)
+ {
+ address += 4;
+ data = ARMul_LoadWordN (state, address);
+ cpab = (state->LDC[CPNum]) (state, ARMul_DATA, instr, data);
}
- if (state->abortSig || state->Aborted) {
- TAKEABORT ;
+ if (state->abortSig || state->Aborted)
+ {
+ TAKEABORT;
}
- }
+}
/***************************************************************************\
* This function does the work of generating the addresses used in an *
* modification. It also handles the Busy-Waiting. *
\***************************************************************************/
-void ARMul_STC(ARMul_State *state,ARMword instr,ARMword address)
-{unsigned cpab ;
- ARMword data ;
+void
+ARMul_STC (ARMul_State * state, ARMword instr, ARMword address)
+{
+ unsigned cpab;
+ ARMword data;
- UNDEF_LSCPCBaseWb ;
- if (ADDREXCEPT(address) || VECTORACCESS(address)) {
- INTERNALABORT(address) ;
+ UNDEF_LSCPCBaseWb;
+ if (ADDREXCEPT (address) || VECTORACCESS (address))
+ {
+ INTERNALABORT (address);
}
- cpab = (state->STC[CPNum])(state,ARMul_FIRST,instr,&data) ;
- while (cpab == ARMul_BUSY) {
- ARMul_Icycles(state,1,0) ;
- if (IntPending(state)) {
- cpab = (state->STC[CPNum])(state,ARMul_INTERRUPT,instr,0) ;
- return ;
- }
- else
- cpab = (state->STC[CPNum])(state,ARMul_BUSY,instr,&data) ;
+ cpab = (state->STC[CPNum]) (state, ARMul_FIRST, instr, &data);
+ while (cpab == ARMul_BUSY)
+ {
+ ARMul_Icycles (state, 1, 0);
+ if (IntPending (state))
+ {
+ cpab = (state->STC[CPNum]) (state, ARMul_INTERRUPT, instr, 0);
+ return;
+ }
+ else
+ cpab = (state->STC[CPNum]) (state, ARMul_BUSY, instr, &data);
}
- if (cpab == ARMul_CANT) {
- CPTAKEABORT ;
- return ;
+ if (cpab == ARMul_CANT)
+ {
+ CPTAKEABORT;
+ return;
}
#ifndef MODE32
- if (ADDREXCEPT(address) || VECTORACCESS(address)) {
- INTERNALABORT(address) ;
+ if (ADDREXCEPT (address) || VECTORACCESS (address))
+ {
+ INTERNALABORT (address);
}
#endif
- BUSUSEDINCPCN ;
- if (BIT(21))
- LSBase = state->Base ;
- cpab = (state->STC[CPNum])(state,ARMul_DATA,instr,&data) ;
- ARMul_StoreWordN(state,address,data) ;
- while (cpab == ARMul_INC) {
- address += 4 ;
- cpab = (state->STC[CPNum])(state,ARMul_DATA,instr,&data) ;
- ARMul_StoreWordN(state,address,data) ;
+ BUSUSEDINCPCN;
+ if (BIT (21))
+ LSBase = state->Base;
+ cpab = (state->STC[CPNum]) (state, ARMul_DATA, instr, &data);
+ ARMul_StoreWordN (state, address, data);
+ while (cpab == ARMul_INC)
+ {
+ address += 4;
+ cpab = (state->STC[CPNum]) (state, ARMul_DATA, instr, &data);
+ ARMul_StoreWordN (state, address, data);
}
- if (state->abortSig || state->Aborted) {
- TAKEABORT ;
+ if (state->abortSig || state->Aborted)
+ {
+ TAKEABORT;
}
- }
+}
/***************************************************************************\
* This function does the Busy-Waiting for an MCR instruction. *
\***************************************************************************/
-void ARMul_MCR(ARMul_State *state,ARMword instr, ARMword source)
-{unsigned cpab ;
-
- cpab = (state->MCR[CPNum])(state,ARMul_FIRST,instr,source) ;
- while (cpab == ARMul_BUSY) {
- ARMul_Icycles(state,1,0) ;
- if (IntPending(state)) {
- cpab = (state->MCR[CPNum])(state,ARMul_INTERRUPT,instr,0) ;
- return ;
- }
- else
- cpab = (state->MCR[CPNum])(state,ARMul_BUSY,instr,source) ;
+void
+ARMul_MCR (ARMul_State * state, ARMword instr, ARMword source)
+{
+ unsigned cpab;
+
+ cpab = (state->MCR[CPNum]) (state, ARMul_FIRST, instr, source);
+ while (cpab == ARMul_BUSY)
+ {
+ ARMul_Icycles (state, 1, 0);
+ if (IntPending (state))
+ {
+ cpab = (state->MCR[CPNum]) (state, ARMul_INTERRUPT, instr, 0);
+ return;
+ }
+ else
+ cpab = (state->MCR[CPNum]) (state, ARMul_BUSY, instr, source);
}
- if (cpab == ARMul_CANT)
- ARMul_Abort(state,ARMul_UndefinedInstrV) ;
- else {
- BUSUSEDINCPCN ;
- ARMul_Ccycles(state,1,0) ;
+ if (cpab == ARMul_CANT)
+ ARMul_Abort (state, ARMul_UndefinedInstrV);
+ else
+ {
+ BUSUSEDINCPCN;
+ ARMul_Ccycles (state, 1, 0);
}
- }
+}
/***************************************************************************\
* This function does the Busy-Waiting for an MRC instruction. *
\***************************************************************************/
-ARMword ARMul_MRC(ARMul_State *state,ARMword instr)
-{unsigned cpab ;
- ARMword result = 0 ;
-
- cpab = (state->MRC[CPNum])(state,ARMul_FIRST,instr,&result) ;
- while (cpab == ARMul_BUSY) {
- ARMul_Icycles(state,1,0) ;
- if (IntPending(state)) {
- cpab = (state->MRC[CPNum])(state,ARMul_INTERRUPT,instr,0) ;
- return(0) ;
- }
- else
- cpab = (state->MRC[CPNum])(state,ARMul_BUSY,instr,&result) ;
+ARMword
+ARMul_MRC (ARMul_State * state, ARMword instr)
+{
+ unsigned cpab;
+ ARMword result = 0;
+
+ cpab = (state->MRC[CPNum]) (state, ARMul_FIRST, instr, &result);
+ while (cpab == ARMul_BUSY)
+ {
+ ARMul_Icycles (state, 1, 0);
+ if (IntPending (state))
+ {
+ cpab = (state->MRC[CPNum]) (state, ARMul_INTERRUPT, instr, 0);
+ return (0);
+ }
+ else
+ cpab = (state->MRC[CPNum]) (state, ARMul_BUSY, instr, &result);
}
- if (cpab == ARMul_CANT) {
- ARMul_Abort(state,ARMul_UndefinedInstrV) ;
- result = ECC ; /* Parent will destroy the flags otherwise */
+ if (cpab == ARMul_CANT)
+ {
+ ARMul_Abort (state, ARMul_UndefinedInstrV);
+ result = ECC; /* Parent will destroy the flags otherwise */
}
- else {
- BUSUSEDINCPCN ;
- ARMul_Ccycles(state,1,0) ;
- ARMul_Icycles(state,1,0) ;
+ else
+ {
+ BUSUSEDINCPCN;
+ ARMul_Ccycles (state, 1, 0);
+ ARMul_Icycles (state, 1, 0);
}
- return(result) ;
+ return (result);
}
/***************************************************************************\
* This function does the Busy-Waiting for an CDP instruction. *
\***************************************************************************/
-void ARMul_CDP(ARMul_State *state,ARMword instr)
-{unsigned cpab ;
-
- cpab = (state->CDP[CPNum])(state,ARMul_FIRST,instr) ;
- while (cpab == ARMul_BUSY) {
- ARMul_Icycles(state,1,0) ;
- if (IntPending(state)) {
- cpab = (state->CDP[CPNum])(state,ARMul_INTERRUPT,instr) ;
- return ;
- }
- else
- cpab = (state->CDP[CPNum])(state,ARMul_BUSY,instr) ;
+void
+ARMul_CDP (ARMul_State * state, ARMword instr)
+{
+ unsigned cpab;
+
+ cpab = (state->CDP[CPNum]) (state, ARMul_FIRST, instr);
+ while (cpab == ARMul_BUSY)
+ {
+ ARMul_Icycles (state, 1, 0);
+ if (IntPending (state))
+ {
+ cpab = (state->CDP[CPNum]) (state, ARMul_INTERRUPT, instr);
+ return;
+ }
+ else
+ cpab = (state->CDP[CPNum]) (state, ARMul_BUSY, instr);
}
- if (cpab == ARMul_CANT)
- ARMul_Abort(state,ARMul_UndefinedInstrV) ;
- else
- BUSUSEDN ;
+ if (cpab == ARMul_CANT)
+ ARMul_Abort (state, ARMul_UndefinedInstrV);
+ else
+ BUSUSEDN;
}
/***************************************************************************\
* This function handles Undefined instructions, as CP isntruction *
\***************************************************************************/
-void ARMul_UndefInstr(ARMul_State *state,ARMword instr)
+void
+ARMul_UndefInstr (ARMul_State * state, ARMword instr ATTRIBUTE_UNUSED)
{
- ARMul_Abort(state,ARMul_UndefinedInstrV) ;
+ ARMul_Abort (state, ARMul_UndefinedInstrV);
}
/***************************************************************************\
* Return TRUE if an interrupt is pending, FALSE otherwise. *
\***************************************************************************/
-unsigned IntPending(ARMul_State *state)
-{
- if (state->Exception) { /* Any exceptions */
- if (state->NresetSig == LOW) {
- ARMul_Abort(state,ARMul_ResetV) ;
- return(TRUE) ;
- }
- else if (!state->NfiqSig && !FFLAG) {
- ARMul_Abort(state,ARMul_FIQV) ;
- return(TRUE) ;
- }
- else if (!state->NirqSig && !IFLAG) {
- ARMul_Abort(state,ARMul_IRQV) ;
- return(TRUE) ;
- }
+unsigned
+IntPending (ARMul_State * state)
+{
+ if (state->Exception)
+ { /* Any exceptions */
+ if (state->NresetSig == LOW)
+ {
+ ARMul_Abort (state, ARMul_ResetV);
+ return (TRUE);
+ }
+ else if (!state->NfiqSig && !FFLAG)
+ {
+ ARMul_Abort (state, ARMul_FIQV);
+ return (TRUE);
+ }
+ else if (!state->NirqSig && !IFLAG)
+ {
+ ARMul_Abort (state, ARMul_IRQV);
+ return (TRUE);
+ }
}
- return(FALSE) ;
- }
+ return (FALSE);
+}
/***************************************************************************\
* Align a word access to a non word boundary *
\***************************************************************************/
-ARMword ARMul_Align(ARMul_State *state, ARMword address, ARMword data)
-{/* this code assumes the address is really unaligned,
- as a shift by 32 is undefined in C */
+ARMword
+ARMul_Align (state, address, data)
+ ARMul_State * state ATTRIBUTE_UNUSED;
+ ARMword address;
+ ARMword data;
+{
+ /* This code assumes the address is really unaligned,
+ as a shift by 32 is undefined in C. */
- address = (address & 3) << 3 ; /* get the word address */
- return( ( data >> address) | (data << (32 - address)) ) ; /* rot right */
+ address = (address & 3) << 3; /* get the word address */
+ return ((data >> address) | (data << (32 - address))); /* rot right */
}
/***************************************************************************\
* to the function. A delay of zero doesn't work, just call the function. *
\***************************************************************************/
-void ARMul_ScheduleEvent(ARMul_State *state, unsigned long delay, unsigned (*what)())
-{unsigned long when ;
- struct EventNode *event ;
-
- if (state->EventSet++ == 0)
- state->Now = ARMul_Time(state) ;
- when = (state->Now + delay) % EVENTLISTSIZE ;
- event = (struct EventNode *)malloc(sizeof(struct EventNode)) ;
- event->func = what ;
- event->next = *(state->EventPtr + when) ;
- *(state->EventPtr + when) = event ;
+void
+ARMul_ScheduleEvent (ARMul_State * state, unsigned long delay,
+ unsigned (*what) ())
+{
+ unsigned long when;
+ struct EventNode *event;
+
+ if (state->EventSet++ == 0)
+ state->Now = ARMul_Time (state);
+ when = (state->Now + delay) % EVENTLISTSIZE;
+ event = (struct EventNode *) malloc (sizeof (struct EventNode));
+ event->func = what;
+ event->next = *(state->EventPtr + when);
+ *(state->EventPtr + when) = event;
}
/***************************************************************************\
* scheduled events. *
\***************************************************************************/
-void ARMul_EnvokeEvent(ARMul_State *state)
-{static unsigned long then ;
-
- then = state->Now ;
- state->Now = ARMul_Time(state) % EVENTLISTSIZE ;
- if (then < state->Now) /* schedule events */
- EnvokeList(state,then,state->Now) ;
- else if (then > state->Now) { /* need to wrap around the list */
- EnvokeList(state,then,EVENTLISTSIZE-1L) ;
- EnvokeList(state,0L,state->Now) ;
+void
+ARMul_EnvokeEvent (ARMul_State * state)
+{
+ static unsigned long then;
+
+ then = state->Now;
+ state->Now = ARMul_Time (state) % EVENTLISTSIZE;
+ if (then < state->Now) /* schedule events */
+ EnvokeList (state, then, state->Now);
+ else if (then > state->Now)
+ { /* need to wrap around the list */
+ EnvokeList (state, then, EVENTLISTSIZE - 1L);
+ EnvokeList (state, 0L, state->Now);
}
- }
+}
-static void EnvokeList(ARMul_State *state, unsigned long from, unsigned long to)
+static void
+EnvokeList (ARMul_State * state, unsigned long from, unsigned long to)
/* envokes all the entries in a range */
-{struct EventNode *anevent ;
-
- for (; from <= to ; from++) {
- anevent = *(state->EventPtr + from) ;
- while (anevent) {
- (anevent->func)(state) ;
- state->EventSet-- ;
- anevent = anevent->next ;
- }
- *(state->EventPtr + from) = NULL ;
+{
+ struct EventNode *anevent;
+
+ for (; from <= to; from++)
+ {
+ anevent = *(state->EventPtr + from);
+ while (anevent)
+ {
+ (anevent->func) (state);
+ state->EventSet--;
+ anevent = anevent->next;
+ }
+ *(state->EventPtr + from) = NULL;
}
- }
+}
/***************************************************************************\
* This routine is returns the number of clock ticks since the last reset. *
\***************************************************************************/
-unsigned long ARMul_Time(ARMul_State *state)
-{return(state->NumScycles + state->NumNcycles +
- state->NumIcycles + state->NumCcycles + state->NumFcycles) ;
+unsigned long
+ARMul_Time (ARMul_State * state)
+{
+ return (state->NumScycles + state->NumNcycles +
+ state->NumIcycles + state->NumCcycles + state->NumFcycles);
}
#include "armopts.h"
#include "armdefs.h"
+#include "ansidecl.h"
-#ifdef VALIDATE /* for running the validate suite */
-#define TUBE 48 * 1024 * 1024 /* write a char on the screen */
+#ifdef VALIDATE /* for running the validate suite */
+#define TUBE 48 * 1024 * 1024 /* write a char on the screen */
#define ABORTS 1
#endif
#define ABORTS
-#ifdef ABORTS /* the memory system will abort */
+#ifdef ABORTS /* the memory system will abort */
/* For the old test suite Abort between 32 Kbytes and 32 Mbytes
For the new test suite Abort between 8 Mbytes and 26 Mbytes */
/* #define LOWABORT 32 * 1024
static ARMword
GetWord (ARMul_State * state, ARMword address)
{
- ARMword page;
- ARMword offset;
- ARMword ** pagetable;
- ARMword * pageptr;
+ ARMword page;
+ ARMword offset;
+ ARMword **pagetable;
+ ARMword *pageptr;
- page = address >> PAGEBITS;
- offset = (address & OFFSETBITS) >> 2;
+ page = address >> PAGEBITS;
+ offset = (address & OFFSETBITS) >> 2;
pagetable = (ARMword **) state->MemDataPtr;
- pageptr = *(pagetable + page);
-
+ pageptr = *(pagetable + page);
+
if (pageptr == NULL)
{
pageptr = (ARMword *) malloc (PAGESIZE);
-
+
if (pageptr == NULL)
{
perror ("ARMulator can't allocate VM page");
exit (12);
}
-
+
*(pagetable + page) = pageptr;
}
-
+
return *(pageptr + offset);
}
static void
PutWord (ARMul_State * state, ARMword address, ARMword data)
{
- ARMword page;
- ARMword offset;
- ARMword ** pagetable;
- ARMword * pageptr;
-
- page = address >> PAGEBITS;
- offset = (address & OFFSETBITS) >> 2;
- pagetable = (ARMword **)state->MemDataPtr;
- pageptr = *(pagetable + page);
-
+ ARMword page;
+ ARMword offset;
+ ARMword **pagetable;
+ ARMword *pageptr;
+
+ page = address >> PAGEBITS;
+ offset = (address & OFFSETBITS) >> 2;
+ pagetable = (ARMword **) state->MemDataPtr;
+ pageptr = *(pagetable + page);
+
if (pageptr == NULL)
{
pageptr = (ARMword *) malloc (PAGESIZE);
if (pageptr == NULL)
{
perror ("ARMulator can't allocate VM page");
- exit(13);
+ exit (13);
}
-
+
*(pagetable + page) = pageptr;
}
-
+
*(pageptr + offset) = data;
}
unsigned
ARMul_MemoryInit (ARMul_State * state, unsigned long initmemsize)
{
- ARMword ** pagetable;
- unsigned page;
+ ARMword **pagetable;
+ unsigned page;
if (initmemsize)
state->MemSize = initmemsize;
-
+
pagetable = (ARMword **) malloc (sizeof (ARMword) * NUMPAGES);
-
+
if (pagetable == NULL)
return FALSE;
-
- for (page = 0 ; page < NUMPAGES ; page++)
+
+ for (page = 0; page < NUMPAGES; page++)
*(pagetable + page) = NULL;
-
- state->MemDataPtr = (unsigned char *)pagetable;
+
+ state->MemDataPtr = (unsigned char *) pagetable;
ARMul_ConsolePrint (state, ", 4 Gb memory");
-
- return TRUE;
+
+ return TRUE;
}
/***************************************************************************\
void
ARMul_MemoryExit (ARMul_State * state)
{
- ARMword page;
- ARMword ** pagetable;
- ARMword * pageptr;
+ ARMword page;
+ ARMword **pagetable;
+ ARMword *pageptr;
- pagetable = (ARMword **)state->MemDataPtr;
- for (page = 0 ; page < NUMPAGES ; page++)
+ pagetable = (ARMword **) state->MemDataPtr;
+ for (page = 0; page < NUMPAGES; page++)
{
pageptr = *(pagetable + page);
if (pageptr != NULL)
- free ((char *)pageptr);
+ free ((char *) pageptr);
}
- free ((char *)pagetable);
+ free ((char *) pagetable);
return;
}
ARMul_ReLoadInstr (ARMul_State * state, ARMword address, ARMword isize)
{
#ifdef ABORTS
- if (address >= LOWABORT && address < HIGHABORT)
+ if (address >= LOWABORT && address < HIGHABORT)
{
ARMul_PREFETCHABORT (address);
return ARMul_ABORTWORD;
}
- else
- {
- ARMul_CLEARABORT;
- }
+ else
+ {
+ ARMul_CLEARABORT;
+ }
#endif
- if ((isize == 2) && (address & 0x2))
- {
- /* We return the next two halfwords: */
- ARMword lo = GetWord (state, address);
- ARMword hi = GetWord (state, address + 4);
+ if ((isize == 2) && (address & 0x2))
+ {
+ /* We return the next two halfwords: */
+ ARMword lo = GetWord (state, address);
+ ARMword hi = GetWord (state, address + 4);
- if (state->bigendSig == HIGH)
- return (lo << 16) | (hi >> 16);
- else
- return ((hi & 0xFFFF) << 16) | (lo >> 16);
- }
+ if (state->bigendSig == HIGH)
+ return (lo << 16) | (hi >> 16);
+ else
+ return ((hi & 0xFFFF) << 16) | (lo >> 16);
+ }
return GetWord (state, address);
}
* Load Instruction, Sequential Cycle *
\***************************************************************************/
-ARMword
-ARMul_LoadInstrS (ARMul_State * state, ARMword address, ARMword isize)
+ARMword ARMul_LoadInstrS (ARMul_State * state, ARMword address, ARMword isize)
{
- state->NumScycles ++;
+ state->NumScycles++;
#ifdef HOURGLASS
- if (( state->NumScycles & HOURGLASS_RATE ) == 0)
+ if ((state->NumScycles & HOURGLASS_RATE) == 0)
{
HOURGLASS;
}
* Load Instruction, Non Sequential Cycle *
\***************************************************************************/
-ARMword
-ARMul_LoadInstrN (ARMul_State * state, ARMword address, ARMword isize)
+ARMword ARMul_LoadInstrN (ARMul_State * state, ARMword address, ARMword isize)
{
- state->NumNcycles ++;
+ state->NumNcycles++;
return ARMul_ReLoadInstr (state, address, isize);
}
* Read Word (but don't tell anyone!) *
\***************************************************************************/
-ARMword
-ARMul_ReadWord (ARMul_State * state, ARMword address)
+ARMword ARMul_ReadWord (ARMul_State * state, ARMword address)
{
#ifdef ABORTS
if (address >= LOWABORT && address < HIGHABORT)
* Load Word, Sequential Cycle *
\***************************************************************************/
-ARMword
-ARMul_LoadWordS (ARMul_State * state, ARMword address)
+ARMword ARMul_LoadWordS (ARMul_State * state, ARMword address)
{
- state->NumScycles ++;
+ state->NumScycles++;
return ARMul_ReadWord (state, address);
}
* Load Word, Non Sequential Cycle *
\***************************************************************************/
-ARMword
-ARMul_LoadWordN (ARMul_State * state, ARMword address)
+ARMword ARMul_LoadWordN (ARMul_State * state, ARMword address)
{
- state->NumNcycles ++;
-
+ state->NumNcycles++;
+
return ARMul_ReadWord (state, address);
}
* Load Halfword, (Non Sequential Cycle) *
\***************************************************************************/
-ARMword
-ARMul_LoadHalfWord (ARMul_State * state, ARMword address)
+ARMword ARMul_LoadHalfWord (ARMul_State * state, ARMword address)
{
ARMword temp, offset;
- state->NumNcycles ++;
+ state->NumNcycles++;
- temp = ARMul_ReadWord (state, address);
- offset = (((ARMword)state->bigendSig * 2) ^ (address & 2)) << 3; /* bit offset into the word */
+ temp = ARMul_ReadWord (state, address);
+ offset = (((ARMword) state->bigendSig * 2) ^ (address & 2)) << 3; /* bit offset into the word */
return (temp >> offset) & 0xffff;
}
* Read Byte (but don't tell anyone!) *
\***************************************************************************/
-ARMword
-ARMul_ReadByte (ARMul_State * state, ARMword address)
+ARMword ARMul_ReadByte (ARMul_State * state, ARMword address)
{
ARMword temp, offset;
- temp = ARMul_ReadWord (state, address);
- offset = (((ARMword)state->bigendSig * 3) ^ (address & 3)) << 3; /* bit offset into the word */
+ temp = ARMul_ReadWord (state, address);
+ offset = (((ARMword) state->bigendSig * 3) ^ (address & 3)) << 3; /* bit offset into the word */
- return (temp >> offset & 0xffL);
+ return (temp >> offset & 0xffL);
}
/***************************************************************************\
* Load Byte, (Non Sequential Cycle) *
\***************************************************************************/
-ARMword
-ARMul_LoadByte (ARMul_State * state, ARMword address)
+ARMword ARMul_LoadByte (ARMul_State * state, ARMword address)
{
- state->NumNcycles ++;
+ state->NumNcycles++;
return ARMul_ReadByte (state, address);
}
void
ARMul_StoreWordS (ARMul_State * state, ARMword address, ARMword data)
{
- state->NumScycles ++;
+ state->NumScycles++;
ARMul_WriteWord (state, address, data);
}
void
ARMul_StoreWordN (ARMul_State * state, ARMword address, ARMword data)
{
- state->NumNcycles ++;
+ state->NumNcycles++;
ARMul_WriteWord (state, address, data);
}
{
ARMword temp, offset;
- state->NumNcycles ++;
-
+ state->NumNcycles++;
+
#ifdef VALIDATE
if (address == TUBE)
{
if (data == 4)
state->Emulate = FALSE;
else
- (void) putc ((char)data, stderr); /* Write Char */
+ (void) putc ((char) data, stderr); /* Write Char */
return;
}
#endif
- temp = ARMul_ReadWord (state, address);
- offset = (((ARMword)state->bigendSig * 2) ^ (address & 2)) << 3; /* bit offset into the word */
-
- PutWord (state, address, (temp & ~(0xffffL << offset)) | ((data & 0xffffL) << offset));
+ temp = ARMul_ReadWord (state, address);
+ offset = (((ARMword) state->bigendSig * 2) ^ (address & 2)) << 3; /* bit offset into the word */
+
+ PutWord (state, address,
+ (temp & ~(0xffffL << offset)) | ((data & 0xffffL) << offset));
}
/***************************************************************************\
{
ARMword temp, offset;
- temp = ARMul_ReadWord (state, address);
- offset = (((ARMword)state->bigendSig * 3) ^ (address & 3)) << 3; /* bit offset into the word */
-
- PutWord (state, address, (temp & ~(0xffL << offset)) | ((data & 0xffL) << offset));
+ temp = ARMul_ReadWord (state, address);
+ offset = (((ARMword) state->bigendSig * 3) ^ (address & 3)) << 3; /* bit offset into the word */
+
+ PutWord (state, address,
+ (temp & ~(0xffL << offset)) | ((data & 0xffL) << offset));
}
/***************************************************************************\
void
ARMul_StoreByte (ARMul_State * state, ARMword address, ARMword data)
{
- state->NumNcycles ++;
+ state->NumNcycles++;
#ifdef VALIDATE
if (address == TUBE)
if (data == 4)
state->Emulate = FALSE;
else
- (void) putc ((char)data,stderr); /* Write Char */
+ (void) putc ((char) data, stderr); /* Write Char */
return;
}
#endif
* Swap Word, (Two Non Sequential Cycles) *
\***************************************************************************/
-ARMword
-ARMul_SwapWord (ARMul_State * state, ARMword address, ARMword data)
+ARMword ARMul_SwapWord (ARMul_State * state, ARMword address, ARMword data)
{
ARMword temp;
- state->NumNcycles ++;
+ state->NumNcycles++;
temp = ARMul_ReadWord (state, address);
-
- state->NumNcycles ++;
-
+
+ state->NumNcycles++;
+
PutWord (state, address, data);
-
+
return temp;
}
* Swap Byte, (Two Non Sequential Cycles) *
\***************************************************************************/
-ARMword
-ARMul_SwapByte (ARMul_State * state, ARMword address, ARMword data)
+ARMword ARMul_SwapByte (ARMul_State * state, ARMword address, ARMword data)
{
ARMword temp;
temp = ARMul_LoadByte (state, address);
ARMul_StoreByte (state, address, data);
-
+
return temp;
}
\***************************************************************************/
void
-ARMul_Icycles (ARMul_State * state, unsigned number, ARMword address)
+ARMul_Icycles (ARMul_State * state, unsigned number, ARMword address ATTRIBUTE_UNUSED)
{
state->NumIcycles += number;
ARMul_CLEARABORT;
\***************************************************************************/
void
-ARMul_Ccycles (ARMul_State * state, unsigned number, ARMword address)
+ARMul_Ccycles (ARMul_State * state, unsigned number, ARMword address ATTRIBUTE_UNUSED)
{
state->NumCcycles += number;
ARMul_CLEARABORT;
}
-
-
-
/********************************************************************/
#include "bag.h"
+#include <stdlib.h>
#define HASH_TABLE_SIZE 256
#define hash(x) (((x)&0xff)^(((x)>>8)&0xff)^(((x)>>16)&0xff)^(((x)>>24)&0xff))
-typedef struct hashentry {
+typedef struct hashentry
+{
struct hashentry *next;
int first;
int second;
-} Hashentry;
+}
+Hashentry;
Hashentry *lookupbyfirst[HASH_TABLE_SIZE];
Hashentry *lookupbysecond[HASH_TABLE_SIZE];
-void addtolist(Hashentry **add, long first, long second) {
- while (*add) add = &((*add)->next);
+void
+addtolist (Hashentry ** add, long first, long second)
+{
+ while (*add)
+ add = &((*add)->next);
/* Malloc will never fail? :o( */
- (*add) = (Hashentry *) malloc(sizeof(Hashentry));
+ (*add) = (Hashentry *) malloc (sizeof (Hashentry));
(*add)->next = (Hashentry *) 0;
(*add)->first = first;
(*add)->second = second;
}
-void killwholelist(Hashentry *p) {
+void
+killwholelist (Hashentry * p)
+{
Hashentry *q;
- while (p) {
- q = p;
- p = p->next;
- free(q);
- }
+ while (p)
+ {
+ q = p;
+ p = p->next;
+ free (q);
+ }
}
-void removefromlist(Hashentry **p, long first, long second) {
+static void
+removefromlist (Hashentry ** p, long first)
+{
Hashentry *q;
- while (*p) {
- if ((*p)->first == first) {
- q = (*p)->next;
- free(*p);
- *p = q;
- return;
+ while (*p)
+ {
+ if ((*p)->first == first)
+ {
+ q = (*p)->next;
+ free (*p);
+ *p = q;
+ return;
+ }
+ p = &((*p)->next);
}
- p = &((*p)->next);
- }
}
-void BAG_putpair(long first, long second) {
+void
+BAG_putpair (long first, long second)
+{
long junk;
- if (BAG_getfirst(&junk, second) != NO_SUCH_PAIR)
- BAG_killpair_bysecond(second);
- addtolist(&lookupbyfirst[hash(first)], first, second);
- addtolist(&lookupbysecond[hash(second)], first, second);
+ if (BAG_getfirst (&junk, second) != NO_SUCH_PAIR)
+ BAG_killpair_bysecond (second);
+ addtolist (&lookupbyfirst[hash (first)], first, second);
+ addtolist (&lookupbysecond[hash (second)], first, second);
}
-Bag_error BAG_getfirst(long *first, long second) {
+Bag_error
+BAG_getfirst (long *first, long second)
+{
Hashentry *look;
- look = lookupbysecond[hash(second)];
- while(look) if (look->second == second) {
- *first = look->first;
- return NO_ERROR;
- }
+ look = lookupbysecond[hash (second)];
+ while (look)
+ if (look->second == second)
+ {
+ *first = look->first;
+ return NO_ERROR;
+ }
return NO_SUCH_PAIR;
}
-Bag_error BAG_getsecond(long first, long *second) {
+Bag_error
+BAG_getsecond (long first, long *second)
+{
Hashentry *look;
- look = lookupbyfirst[hash(first)];
- while(look) {
- if (look->first == first) {
- *second = look->second;
- return NO_ERROR;
+ look = lookupbyfirst[hash (first)];
+ while (look)
+ {
+ if (look->first == first)
+ {
+ *second = look->second;
+ return NO_ERROR;
+ }
+ look = look->next;
}
- look = look->next;
- }
return NO_SUCH_PAIR;
}
-Bag_error BAG_killpair_byfirst(long first) {
+Bag_error
+BAG_killpair_byfirst (long first)
+{
long second;
- if (BAG_getsecond(first, &second) == NO_SUCH_PAIR)
+ if (BAG_getsecond (first, &second) == NO_SUCH_PAIR)
return NO_SUCH_PAIR;
- removefromlist(&lookupbyfirst[hash(first)], first, second);
- removefromlist(&lookupbysecond[hash(second)], first, second);
+ removefromlist (&lookupbyfirst[hash (first)], first);
+ removefromlist (&lookupbysecond[hash (second)], first);
return NO_ERROR;
}
-Bag_error BAG_killpair_bysecond(long second) {
+Bag_error
+BAG_killpair_bysecond (long second)
+{
long first;
-
- if (BAG_getfirst(&first, second) == NO_SUCH_PAIR)
+
+ if (BAG_getfirst (&first, second) == NO_SUCH_PAIR)
return NO_SUCH_PAIR;
- removefromlist(&lookupbyfirst[hash(first)], first, second);
- removefromlist(&lookupbysecond[hash(second)], first, second);
+ removefromlist (&lookupbyfirst[hash (first)], first);
+ removefromlist (&lookupbysecond[hash (second)], first);
return NO_ERROR;
}
-void BAG_newbag() {
+void
+BAG_newbag ()
+{
int i;
- for (i = 0; i < 256; i++) {
- killwholelist(lookupbyfirst[i]);
- killwholelist(lookupbysecond[i]);
- lookupbyfirst[i] = lookupbysecond[i] = (Hashentry *) 0;
- }
+ for (i = 0; i < 256; i++)
+ {
+ killwholelist (lookupbyfirst[i]);
+ killwholelist (lookupbysecond[i]);
+ lookupbyfirst[i] = lookupbysecond[i] = (Hashentry *) 0;
+ }
}
-
-
-
-
-
#include <stdio.h>
#include <stdarg.h>
+#include <string.h>
#include <bfd.h>
#include <signal.h>
#include "callback.h"
#include "armdefs.h"
#include "armemu.h"
#include "dbg_rdi.h"
+#include "ansidecl.h"
host_callback *sim_callback;
/* Non-zero to set big endian mode. */
static int big_endian;
-static void
+int stop_simulator;
+
+static void
init ()
{
static int done;
if (!done)
{
- ARMul_EmulateInit();
+ ARMul_EmulateInit ();
state = ARMul_NewState ();
state->bigendSig = (big_endian ? HIGH : LOW);
- ARMul_MemoryInit(state, mem_size);
- ARMul_OSInit(state);
- ARMul_CoProInit(state);
+ ARMul_MemoryInit (state, mem_size);
+ ARMul_OSInit (state);
+ ARMul_CoProInit (state);
state->verbose = verbosity;
done = 1;
}
}
/* Set the memory size to SIZE bytes.
- Must be called before initializing simulator. */
+ Must be called before initializing simulator. */
/* FIXME: Rename to sim_set_mem_size. */
-void
+void
sim_size (size)
int size;
{
mem_size = size;
}
-void
-ARMul_ConsolePrint (ARMul_State * state, const char *format,...)
+void
+ARMul_ConsolePrint (ARMul_State * state, const char *format, ...)
{
va_list ap;
}
}
-ARMword
-ARMul_Debug (ARMul_State * state, ARMword pc, ARMword instr)
+ARMword
+ARMul_Debug (ARMul_State * state ATTRIBUTE_UNUSED, ARMword pc ATTRIBUTE_UNUSED, ARMword instr ATTRIBUTE_UNUSED)
{
-
+ return 0;
}
int
sim_write (sd, addr, buffer, size)
- SIM_DESC sd;
+ SIM_DESC sd ATTRIBUTE_UNUSED;
SIM_ADDR addr;
unsigned char *buffer;
int size;
init ();
for (i = 0; i < size; i++)
{
- ARMul_WriteByte (state, addr+i, buffer[i]);
+ ARMul_WriteByte (state, addr + i, buffer[i]);
}
return size;
}
int
sim_read (sd, addr, buffer, size)
- SIM_DESC sd;
+ SIM_DESC sd ATTRIBUTE_UNUSED;
SIM_ADDR addr;
unsigned char *buffer;
int size;
int
sim_trace (sd)
- SIM_DESC sd;
-{
- (*sim_callback->printf_filtered) (sim_callback, "This simulator does not support tracing\n");
+ SIM_DESC sd ATTRIBUTE_UNUSED;
+{
+ (*sim_callback->printf_filtered) (sim_callback,
+ "This simulator does not support tracing\n");
return 1;
}
int
sim_stop (sd)
- SIM_DESC sd;
+ SIM_DESC sd ATTRIBUTE_UNUSED;
{
- return 0;
+ state->Emulate = STOP;
+ stop_simulator = 1;
+ return 1;
}
void
sim_resume (sd, step, siggnal)
- SIM_DESC sd;
- int step, siggnal;
+ SIM_DESC sd ATTRIBUTE_UNUSED;
+ int step;
+ int siggnal ATTRIBUTE_UNUSED;
{
state->EndCondition = 0;
+ stop_simulator = 0;
if (step)
{
}
else
{
-#if 1 /* JGS */
- state->NextInstr = RESUME; /* treat as PC change */
+#if 1 /* JGS */
+ state->NextInstr = RESUME; /* treat as PC change */
#endif
state->Reg[15] = ARMul_DoProg (state);
}
SIM_RC
sim_create_inferior (sd, abfd, argv, env)
- SIM_DESC sd;
+ SIM_DESC sd ATTRIBUTE_UNUSED;
struct _bfd *abfd;
char **argv;
char **env;
{
- int argvlen=0;
+ int argvlen = 0;
char **arg;
if (abfd != NULL)
ARMul_SetPC (state, bfd_get_start_address (abfd));
else
- ARMul_SetPC (state, 0); /* ??? */
+ ARMul_SetPC (state, 0); /* ??? */
-#if 1 /* JGS */
+#if 1 /* JGS */
/* We explicitly select a processor capable of supporting the ARM
32bit mode, and then we force the simulated CPU into the 32bit
User mode: */
- ARMul_SelectProcessor(state, ARM600);
- ARMul_SetCPSR(state, USER32MODE);
+ ARMul_SelectProcessor (state, ARM600);
+ ARMul_SetCPSR (state, USER32MODE);
#endif
if (argv != NULL)
{
/*
- ** Set up the command line (by laboriously stringing together the
- ** environment carefully picked apart by our caller...)
- */
+ ** Set up the command line (by laboriously stringing together the
+ ** environment carefully picked apart by our caller...)
+ */
/* Free any old stuff */
if (state->CommandLine != NULL)
{
- free(state->CommandLine);
+ free (state->CommandLine);
state->CommandLine = NULL;
}
-
+
/* See how much we need */
for (arg = argv; *arg != NULL; arg++)
- argvlen += strlen(*arg)+1;
-
+ argvlen += strlen (*arg) + 1;
+
/* allocate it... */
- state->CommandLine = malloc(argvlen+1);
+ state->CommandLine = malloc (argvlen + 1);
if (state->CommandLine != NULL)
{
arg = argv;
- state->CommandLine[0]='\0';
+ state->CommandLine[0] = '\0';
for (arg = argv; *arg != NULL; arg++)
{
- strcat(state->CommandLine, *arg);
- strcat(state->CommandLine, " ");
+ strcat (state->CommandLine, *arg);
+ strcat (state->CommandLine, " ");
}
}
}
/* Now see if there's a MEMSIZE spec in the environment */
while (*env)
{
- if (strncmp(*env, "MEMSIZE=", sizeof("MEMSIZE=")-1)==0)
+ if (strncmp (*env, "MEMSIZE=", sizeof ("MEMSIZE=") - 1) == 0)
{
- unsigned long top_of_memory;
char *end_of_num;
-
+
/* Set up memory limit */
- state->MemSize = strtoul(*env + sizeof("MEMSIZE=")-1, &end_of_num, 0);
+ state->MemSize =
+ strtoul (*env + sizeof ("MEMSIZE=") - 1, &end_of_num, 0);
}
env++;
}
void
sim_info (sd, verbose)
- SIM_DESC sd;
- int verbose;
+ SIM_DESC sd ATTRIBUTE_UNUSED;
+ int verbose ATTRIBUTE_UNUSED;
{
}
-static int
+static int
frommem (state, memory)
struct ARMul_State *state;
unsigned char *memory;
if (state->bigendSig == HIGH)
{
return (memory[0] << 24)
- | (memory[1] << 16)
- | (memory[2] << 8)
- | (memory[3] << 0);
+ | (memory[1] << 16) | (memory[2] << 8) | (memory[3] << 0);
}
else
{
return (memory[3] << 24)
- | (memory[2] << 16)
- | (memory[1] << 8)
- | (memory[0] << 0);
+ | (memory[2] << 16) | (memory[1] << 8) | (memory[0] << 0);
}
}
static void
-tomem (state, memory, val)
+tomem (state, memory, val)
struct ARMul_State *state;
unsigned char *memory;
int val;
int
sim_store_register (sd, rn, memory, length)
- SIM_DESC sd;
+ SIM_DESC sd ATTRIBUTE_UNUSED;
int rn;
unsigned char *memory;
- int length;
+ int length ATTRIBUTE_UNUSED;
{
init ();
- ARMul_SetReg(state, state->Mode, rn, frommem (state, memory));
+ ARMul_SetReg (state, state->Mode, rn, frommem (state, memory));
return -1;
}
int
sim_fetch_register (sd, rn, memory, length)
- SIM_DESC sd;
+ SIM_DESC sd ATTRIBUTE_UNUSED;
int rn;
unsigned char *memory;
- int length;
+ int length ATTRIBUTE_UNUSED;
{
ARMword regval;
init ();
if (rn < 16)
- regval = ARMul_GetReg(state, state->Mode, rn);
- else if (rn == 25) /* FIXME: use PS_REGNUM from gdb/config/arm/tm-arm.h */
- regval = ARMul_GetCPSR(state);
+ regval = ARMul_GetReg (state, state->Mode, rn);
+ else if (rn == 25) /* FIXME: use PS_REGNUM from gdb/config/arm/tm-arm.h */
+ regval = ARMul_GetCPSR (state);
else
- regval = 0; /* FIXME: should report an error */
+ regval = 0; /* FIXME: should report an error */
tomem (state, memory, regval);
return -1;
}
sim_kind = kind;
myname = argv[0];
sim_callback = ptr;
-
+
/* Decide upon the endian-ness of the processor.
If we can, get the information from the bfd itself.
Otherwise look to see if we have been given a command
else if (argv[1] != NULL)
{
int i;
-
+
/* Scan for endian-ness switch. */
for (i = 0; (argv[i] != NULL) && (argv[i][0] != 0); i++)
- if (argv[i][0] == '-' && argv[i][1] == 'E')
- {
- char c;
-
- if ((c = argv[i][2]) == 0)
- {
- ++i;
- c = argv[i][0];
- }
-
- switch (c)
- {
- case 0:
- sim_callback->printf_filtered
- (sim_callback, "No argument to -E option provided\n");
- break;
-
- case 'b':
- case 'B':
- big_endian = 1;
- break;
-
- case 'l':
- case 'L':
- big_endian = 0;
- break;
-
- default:
- sim_callback->printf_filtered
- (sim_callback, "Unrecognised argument to -E option\n");
- break;
- }
- }
+ if (argv[i][0] == '-' && argv[i][1] == 'E')
+ {
+ char c;
+
+ if ((c = argv[i][2]) == 0)
+ {
+ ++i;
+ c = argv[i][0];
+ }
+
+ switch (c)
+ {
+ case 0:
+ sim_callback->printf_filtered
+ (sim_callback, "No argument to -E option provided\n");
+ break;
+
+ case 'b':
+ case 'B':
+ big_endian = 1;
+ break;
+
+ case 'l':
+ case 'L':
+ big_endian = 0;
+ break;
+
+ default:
+ sim_callback->printf_filtered
+ (sim_callback, "Unrecognised argument to -E option\n");
+ break;
+ }
+ }
}
return (SIM_DESC) 1;
void
sim_close (sd, quitting)
- SIM_DESC sd;
- int quitting;
+ SIM_DESC sd ATTRIBUTE_UNUSED;
+ int quitting ATTRIBUTE_UNUSED;
{
/* nothing to do */
}
SIM_DESC sd;
char *prog;
bfd *abfd;
- int from_tty;
+ int from_tty ATTRIBUTE_UNUSED;
{
- extern bfd *sim_load_file (); /* ??? Don't know where this should live. */
+ extern bfd *sim_load_file (); /* ??? Don't know where this should live. */
bfd *prog_bfd;
prog_bfd = sim_load_file (sd, myname, sim_callback, prog, abfd,
- sim_kind == SIM_OPEN_DEBUG,
- 0, sim_write);
+ sim_kind == SIM_OPEN_DEBUG, 0, sim_write);
if (prog_bfd == NULL)
return SIM_RC_FAIL;
ARMul_SetPC (state, bfd_get_start_address (prog_bfd));
void
sim_stop_reason (sd, reason, sigrc)
- SIM_DESC sd;
+ SIM_DESC sd ATTRIBUTE_UNUSED;
enum sim_stop *reason;
int *sigrc;
{
- if (state->EndCondition == 0)
+ if (stop_simulator)
+ {
+ *reason = sim_stopped;
+ *sigrc = SIGINT;
+ }
+ else if (state->EndCondition == 0)
{
*reason = sim_exited;
*sigrc = state->Reg[0] & 255;
void
sim_do_command (sd, cmd)
- SIM_DESC sd;
- char *cmd;
-{
- (*sim_callback->printf_filtered) (sim_callback, "This simulator does not accept any commands.\n");
+ SIM_DESC sd ATTRIBUTE_UNUSED;
+ char *cmd ATTRIBUTE_UNUSED;
+{
+ (*sim_callback->printf_filtered) (sim_callback,
+ "This simulator does not accept any commands.\n");
}
+2000-02-08 Nick Clifton <nickc@cygnus.com>
+
+ * callback.c: Fix compile time warning messages.
+ * run.c: Fix compile time warning messages.
+
+1999-12-17 Dave Brolley <brolley@cygnus.com>
+
+ * sim-profile.h: (set_profile_option_mask): Add prototype.
+ * sim-profile.c (set_profile_option_mask): No longer static.
+
+Wed Dec 8 21:47:13 1999 Andrew Cagney <cagney@b1.cygnus.com>
+
+ * sim-arange.c: Include <string.h>
+
+1999-12-07 Dave Brolley <brolley@cygnus.com>
+
+ * sim-options.c (print_help): '=' required before optional argument.
+ * cgen-par.h (CGEN_FN_MEM_QI_WRITE): New enumerator.
+ (CGEN_FN_MEM_HI_WRITE): New enumerator.
+ (CGEN_FN_MEM_SI_WRITE): New enumerator.
+ (CGEN_FN_MEM_DI_WRITE): New enumerator.
+ (CGEN_FN_MEM_DF_WRITE): New enumerator.
+ (CGEN_FN_MEM_XI_WRITE): New enumerator.
+ (fn_mem_qi_write): New union members.
+ (fn_mem_hi_write): New union members.
+ (fn_mem_si_write): New union members.
+ (fn_mem_di_write): New union members.
+ (fn_mem_df_write): New union members.
+ (fn_mem_xi_write): New union members.
+ (sim_queue_fn_mem_qi_write): New function.
+ (sim_queue_fn_mem_hi_write): New function.
+ (sim_queue_fn_mem_si_write): New function.
+ (sim_queue_fn_mem_di_write): New function.
+ (sim_queue_fn_mem_df_write): New function.
+ (sim_queue_fn_mem_xi_write): New function.
+ * cgen-par.c (sim_queue_fn_mem_qi_write): New function.
+ (sim_queue_fn_mem_hi_write): New function.
+ (sim_queue_fn_mem_si_write): New function.
+ (sim_queue_fn_mem_di_write): New function.
+ (sim_queue_fn_mem_df_write): New function.
+ (sim_queue_fn_mem_xi_write): New function.
+ (cgen_write_queue_element_execute): Handle CGEN_FN_MEM_QI_WRITE,
+ CGEN_FN_MEM_HI_WRITE, CGEN_FN_MEM_SI_WRITE, CGEN_FN_MEM_DI_WRITE,
+ CGEN_FN_MEM_DF_WRITE, CGEN_FN_MEM_XI_WRITE.
+
+1999-12-01 Dave Brolley <brolley@cygnus.com>
+
+ * cgen-accfp.c (subsf): Check status code.
+ (mulsf): Ditto.
+ (negsf): Ditto.
+ (abssf): Ditto.
+ (sqrtsf): Ditto.
+ (invsf): Ditto.
+ (minsf): Ditto.
+ (maxsf): Ditto.
+ (subdf): Ditto.
+ (muldf): Ditto.
+ (divdf): Ditto.
+ (negdf): Ditto.
+ (absdf): Ditto.
+ (sqrtdf): Ditto.
+ (invdf): Ditto.
+ (mindf): Ditto.
+ (maxdf): Ditto.
+
+1999-11-26 Dave Brolley <brolley@cygnus.com>
+
+ * cgen-par.h (fn_df_write): Mode of data is DF.
+ (sim_queue_fn_df_write): Mode of data is DF.
+ * cgen-par.c (sim_queue_fn_df_write): Mode of data is DF.
+
+1999-11-22 Dave Brolley <brolley@cygnus.com>
+
+ * cgen-trace.c (SIZE_TRACE_BUF): Inxrease size of trace buffer.
+ * cgen-par.h (CGEN_WRITE_QUEUE_SIZE): Increase size of queue.
+
+1999-11-04 Dave Brolley <brolley@cygnus.com>
+
+ * cgen-par.h (cgen_write_queue_kind): Add CGEN_FN_XI_WRITE and
+ CGEN_MEM_XI_WRITE members.
+ (CGEN_WRITE_QUEUE_ELEMENT): Add fn_xi_write and mem_xi_write members.
+ (sim_queue_fn_xi_write): New function.
+ (sim_queue_mem_xi_write): New function.
+
+ * cgen-par.c (sim_queue_fn_xi_write): New function.
+ (sim_queue_mem_xi_write): New function.
+ (cgen_write_queue_element_execute): Handle CGEN_FN_XI_WRITE and
+ CGEN_MEM_XI_WRITE.
+
+1999-10-22 Dave Brolley <brolley@cygnus.com>
+
+ * cgen-par.h (insn_address): New field in CGEN_WRITE_QUEUE_ELEMENT.
+ (CGEN_WRITE_QUEUE_ELEMENT_IADDR): New macro.
+ * cgen-par.c: Set insn_address for each queued write. Get pc from
+ cpu when executing queued writes.
+
+1999-10-19 Dave Brolley <brolley@cygnus.com>
+
+ * cgen-par.h (sim_queue_fn_pc_write): New function.
+ (CGEN_FN_PC_WRITE): New enumerator.
+ (fn_pc_write): New union member.
+ * cgen-par.c (sim_queue_fn_pc_write): New function.
+ (cgen_write_queue_element_execute): Handle CGEN_FN_PC_WRITE.
+
+1999-10-18 Dave Brolley <brolley@cygnus.com>
+
+ * cgen-par.h (CGEN_MEM_DI_WRITE): New enumerator.
+ (CGEN_MEM_DF_WRITE): New enumerator.
+ (mem_di_write): New union member.
+ (mem_df_write): New union member.
+ * cgen-par.c (sim_queue_mem_di_write): New function.
+ (sim_queue_mem_df_write): New function.
+ (cgen_write_queue_element_execute): Handle CGEN_MEM_DI_WRITE and
+ CGEN_MEM_DF_WRITE.
+ * cgen-accfp.c (divsf): Check for division errors.
+
+1999-10-14 Doug Evans <devans@casey.cygnus.com>
+
+ * cgen-engine.h (EXTRACT_INT,EXTRACT_UINT): Delete.
+
+1999-10-07 Dave Brolley <brolley@cygnus.com>
+
+ * cgen-par.h (CGEN_FN_HI_WRITE): New enumerator.
+ (fn_hi_write): New union member.
+ (sim_queue_fn_hi_write): New function.
+ * cgen-par.c (sim_queue_fn_hi_write): New function.
+ (cgen_write_queue_element_execute): Handle CGEN_FN_HI_WRITE.
+
+1999-09-29 Doug Evans <devans@casey.cygnus.com>
+
+ * cgen-defs.h (sim_engine_invalid_insn): New arg `vpc'.
+ Change type of result to SEM_PC.
+
+Wed Sep 29 14:43:57 1999 Dave Brolley <brolley@cygnus.com>
+
+ * cgen-defs.h (sim_engine_invalid_insn): Now returns PC.
+
+1999-09-25 Doug Evans <devans@casey.cygnus.com>
+
+ * cgen-ops.h (SUBWORD*): Delete cpu arg.
+ (JOIN*): Delete cpu arg.
+
+Tue Sep 21 17:14:16 1999 Dave Brolley <brolley@cygnus.com>
+
+ * genmloop.sh (@cpu@_scache_lookup): No longer takes last_insn_p
+ parameter.
+ (SET_LAST_INSN_P): Set last_insn_p flag in the scache element.
+
+Mon Sep 20 21:44:06 1999 Geoffrey Keating <geoffk@cygnus.com>
+
+ * sim-fpu.c (i2fpu): Keep the guard bits sticky when converting
+ large values.
+
+Wed Sep 15 14:12:37 1999 Andrew Cagney <cagney@b1.cygnus.com>
+
+ * hw-tree.c, hw-properties.c, hw-instances.c: Include "sim-io.h".
+
+Tue Sep 14 14:15:47 1999 Dave Brolley <brolley@cygnus.com>
+
+ * cgen-par.h (CGEN_BI_WRITE): New enumerator.
+ (bi_write): New union element.
+ (sim_queue_bi_write): New function.
+ * cgen-par.c (sim_queue_bi_write): New function.
+ (cgen_write_queue_element_execute): Handle CGEN_BI_WRITE.
+
+Thu Sep 2 18:15:53 1999 Andrew Cagney <cagney@b1.cygnus.com>
+
+ * configure: Regenerated to track ../common/aclocal.m4 changes.
+
+ * aclocal.m4 (WERROR_CFLAGS, WARN_CFLAGS): Merge from
+ ../gdb/configure.in.
+ * Make-common.in (WERROR_CFLAGS, WARN_CFLAGS): Define.
+ (SIM_WERROR_CFLAGS, SIM_WARN_CFLAGS): Define.
+ (SIM_WARNINGS): Delete
+ (CONFIG_CFLAGS): Update.
+
+Tue Aug 31 16:01:42 1999 Dave Brolley <brolley@cygnus.com>
+
+ * cgen-par.c: New file.
+ * cgen-par.h: New file.
+ * cgen-sim.h (cgen-par.h): #include it.
+ * cgen-cpu.h (write_queue): New field.
+ (CPU_WRITE_QUEUE): New access macro.
+ * Make-common.in (CGEN_MAIN_CPU_DEPS): Add cgen-par.h.
+ (cgen-par.o): New target.
+
+1999-08-28 Doug Evans <devans@casey.cygnus.com>
+
+ * cgen-types.h (mode_type,MODE_VOID): Renamed from MODE_VM.
+ * cgen-utils.c (mode_names): Update.
+
+1999-08-20 Doug Evans <devans@casey.cygnus.com>
+
+ * genmloop.sh: New args -parallel-generic-write, -parallel-only.
+ * cgen-engine.h (SEMANTIC_FN): Don't use version with PAREXEC
+ buffer arg if WITH_PARALLEL_GENWRITE.
+ (struct insn_sem): Handle WITH_PARALLEL_GENWRITE.
+ (struct idesc): Ditto.
+
+Wed Aug 18 18:17:28 1999 Doug Evans <devans@canuck.cygnus.com>
+
+ * sim-model.c (model_option_handler): Add \n to error message.
+
+1999-08-08 Doug Evans <devans@casey.cygnus.com>
+
+ * cgen-engine.h (SEM_FN_NAME,SEMF_FN_NAME): Delete.
+ (insn_sem): Rewrite.
+ (sem_fn_desc): New struct.
+ (idesc): Rewrite.
+ * genmloop.sh (scache case,@cpu@_scache_lookup): Profile scache hit,
+ misses if ! FAST_P.
+ (scache case): Split into non-parallel/parallel versions.
+ (@cpu@_engine_run_{full,fast}): Call @cpu@_{sem,semf}_init_idesc_table
+ if not use semantic switch version.
+
+1999-08-04 Doug Evans <devans@casey.cygnus.com>
+
+ * cgen-defs.h (SEM_BRANCH_TYPE): New enum.
+ * cgen-engine.h (SEM_BRANCH_UNTAKEN,SEM_BRANCH_UNCACHEABLE): Delete.
+ (SEM_BRANCH_INIT_EXTRACT): Delete.
+ (SEM_BRANCH_INIT): Replace npc_ptr with br_type.
+ (SEM_BRANCH_FINI): Ditto.
+ (SEM_BRANCH_VIA_ADDR): Ditto.
+ (SEM_BRANCH_VIA_CACHE): Ditto. Delete cachvarptr arg.
+ (SEM_BRANCH_ADDR_CACHE): Delete.
+ (SEM_SKIP_COMPILE,SEM_SKIP_INSN): New macros.
+ * cgen-scache.h (cpu_scache): Replace member pbb_pr_npc_ptr with
+ pbb_br_type.
+ * genmloop.sh (eng.hin): Update prototype of ${cpu}_pbb_cti_chain.
+ (@cpu@_pbb_begin): Initialize branch_target.
+ (@cpu@_pbb_cti_chain): Replace arg new_vpc_ptr with br_type.
+ (@cpu@_engine_run_full): Replace local pbb_br_npc_ptr with
+ pbb_br_type.
+ (@cpu@_engine_run_fast): Ditto.
+
+Fri Jul 16 14:47:53 1999 Dave Brolley <brolley@cygnus.com>
+
+ * cgen-utils.c (RORSI): New function.
+ (ROLSI): New function.
+
+1999-07-14 Doug Evans <devans@casey.cygnus.com>
+
+ * Makefile.in (TAGS): Tweak TAGS regex.
+ * cgen-mem.h (*): Add TAGS markers.
+
+Sun Jul 11 23:47:20 1999 Andrew Cagney <cagney@b1.cygnus.com>
+
+ * sim-resume.c (sim_resume): Ensure that the siggnal [sic] is only
+ passed in when sim_resume is first entered - don't re-pass it
+ after a restart.
+
+Sun Jul 11 23:34:44 1999 Andrew Cagney <cagney@b1.cygnus.com>
+
+ * sim-options.c (standard_option_handler): Add OPTION_LOAD_VMA and
+ OPTION_LOAD_LMA but only when is defined.
+ (standard_options): When SIM_HANDLES_LMA is defined include
+ options --load-lma and --load-vma.
+ (standard_install): Initialize STATE_LOAD_AT_LMA_P.
+
+ * sim-base.h (STATE_LOAD_AT_LMA_P): Define.
+ (struct sim_state_base): Add load_at_lma_p.
+ * sim-hload.c (sim_load): Replace SIM_HANDLES_LMA with
+ STATE_LOAD_AT_LMA_P.
+
+Sun Jul 11 12:03:36 1999 Andrew Cagney <cagney@b1.cygnus.com>
+
+ * nrun.c (main): Re-format loop gnu style.
+
+Wed Jul 7 19:56:03 1999 Andrew Cagney <cagney@b1.cygnus.com>
+
+ * dv-sockser.c (connected_p): Initialize addrlen.
+
+1999-07-06 Dave Brolley <brolley@cygnus.com>
+
+ * cgen-accfp.c (floatsidf): New function.
+ (fixdfsi): New function.
+
+1999-07-06 Doug Evans <devans@casey.cygnus.com>
+
+ * sim-model.c (sim_model_init): Issue error if machine is unsupported.
+
+1999-07-05 Doug Evans <devans@casey.cygnus.com>
+
+ * Make-common.in (CGEN_MAIN_CPU_DEPS): Add cgen-fpu.h.
+ (cgen-fpu.o,cgen-accfp.o): Add rules for.
+ * cgen-fpu.c: New file.
+ * cgen-fpu.h: New file.
+ * cgen-accfp.c: New file.
+ * cgen-cpu.h (CGEN_CPU): New member fpu.
+ * cgen-mem.h: Redo fp support.
+ * cgen-ops.h: Delete k&r support. Redo fp support.
+ * cgen-sim.h: Include cgen-fpu.h.
+ * cgen-types.h (SF,DF,XF,TF): Moved to cgen-fpu.h.
+
+1999-06-23 Doug Evans <devans@casey.cygnus.com>
+
+ * cgen-engine.h (TARGET_SEM_BRANCH_FINI): Remove cruft at end of
+ ifndef.
+ * genmloop.sh (@cpu@_scache_lookup): Delete unused local var.
+ (@cpu@_pbb_cti_chain): Minor clean up.
+
+1999-05-08 Felix Lee <flee@cygnus.com>
+
+ * aclocal.m4: Use AC_EXEEXT instead of AM_EXEEXT. Delete defn of
+ AM_CYGWIN32 and AM_EXEEXT.
+ * configure: Regenerate.
+
+Fri Apr 16 16:43:22 1999 Doug Evans <devans@charmed.cygnus.com>
+
+ * sim-core.c (device_error,device_io_read_buffer,
+ device_io_write_buffer): Delete decls.
+ * sim-core.h: Put them here.
+
+ * sim-core.c (sim_core_read_buffer): Pass sd to device_io_read_buffer.
+ (sim_core_write_buffer): Pass sd to device_io_write_buffer.
+ * sim-n-core.h (sim_core_read_aligned_N): Ditto.
+ (sim_core_write_aligned_N): Ditto.
+
+1999-04-14 Stephane Carrez <stcarrez@worldnet.fr>
+
+ * sim-memopt.c (sim_memory_uninstall): Don't look into
+ free()d memory.
+
+1999-04-14 Doug Evans <devans@casey.cygnus.com>
+
+ * cgen-utils.scm (virtual_insn_entries): Update attribute definition.
+
+1999-04-13 Doug Evans <devans@casey.cygnus.com>
+
+ * sim-core.c (sim_core_read_buffer): Handle NULL cpu when WITH_DEVICES.
+ (sim_core_write_buffer): Ditto.
+
+1999-04-02 Keith Seitz <keiths@cygnus.com>
+
+ * sim-io.c (sim_io_poll_quit): Only call the poll_quit callback
+ after the interval counter has expired.
+ (POLL_QUIT_INTERVAL): Define. Used to tweak the frequency of
+ poll_quit callbacks. May be overridden by Makefile.
+ (poll_quit_counter): New global.
+ * sim-events.c: Remove all mentions of ui_loop_hook. The
+ host callback "poll_quit" will serve the purpose.
+ * run.c: Add definition of ui_loop_hook when NEED_UI_LOOP_HOOK
+ is defined.
+ * nrun.c: Remove declaration of ui_loop_hook.
+
+Wed Mar 31 18:55:41 1999 Doug Evans <devans@canuck.cygnus.com>
+
+ * cgen-run.c (sim_resume): Don't tell main loop to run "forever"
+ if being used by gdb.
+
+1999-03-22 Doug Evans <devans@casey.cygnus.com>
+
+ * cgen-types.h (XF,TF): Tweak.
+ * cgen-ops.h: Redo inline support. Delete DI_FN_SUPPORT,
+ in cgen-types.h.
+ (SUBWORD*,JOIN*): Define.
+ * cgen-trace.c (sim_cgen_disassemble_insn): Update, base_insn_bitsize
+ moved into cpu descriptor.
+ * sim-model.h (MACH): New member `num'.
+
1999-02-09 Doug Evans <devans@casey.cygnus.com>
- * Make-common.in (CGEN_READ_SCM): Renamed from CGEN_MAIN_SCM.
- (CGEN_DESC_SCM): New variable.
- (cgen-desc): New rule.
* cgen-cpu.h (CGEN_DISASSEMBLER): New type.
(CGEN_CPU): Member opcode renamed to cpu_desc.
New members get_idata,disassembler.
1999-01-05 Doug Evans <devans@casey.cygnus.com>
* Make-common.in (CGEN_INCLUDE_DEPS): Add cgen-defs.h, cgen-engine.h.
- (CGEN_MAIN_SCM): Add rtx-funcs.scm.
- (cgen-arch): Pass $(mach) to cgen.sh.
* cgen-engine.h (SEM_BRANCH_FINI): New arg pcvar, all uses updated.
(SEM_BRANCH_INIT_EXTRACT): New macro.
(SEM_BRANCH_INIT): Add taken_p.
1998-11-18 Doug Evans <devans@casey.cygnus.com>
* Make-common.in (cgen-utils.o): Depend on cgen-engine.h.
- (CGEN_ARCH_SCM): New variable.
* cgen-engine.h (EXTRACT_[ML]SB0_{INT,UINT}): New macros.
(EXTRACT_INT,EXTRACT_UINT): New macros.
(SEM_SEM_ARG): New macro.
(sim_disassemble_insn): Update prototype.
* cgen-trace.c (current_insn,insn_fields): New static locals.
(trace_insn): Set them.
- * cgen-utils.scm: #include cgen-engine.h.
+ * cgen-utils.c: #include cgen-engine.h.
(sim_disassemble_insn): New arg insn_fields.
Handle variable length insns.
* genmloop.sh: Only emit pbb decls if -pbb.
Wed Jul 1 16:44:12 1998 Doug Evans <devans@seba.cygnus.com>
- * Make-common.in (SCHEME,SCHEMEFLAGS): Delete.
- (CGENDIR,CGEN): New variables.
- (CGEN_VERBOSE): Renamed to CGENFLAGS.
- (cgen-arch,cgen-cpu,cgen-decode): Update.
- (CGEN_CPU_WRITE): New variable.
- (CGEN_CPU_SEMSW): -W -> -X.
- (CGEN_FLAGS_TO_PASS): Delete SCHEME. Add CGEN,CGENFLAGS.
- * cgen.sh: Delete args scheme,schemeflags. New arg cgen.
-
* cgen-sim.h (RECORD_IADDR): Delete.
* cgen-types.h (HOSTINT,HOSTUINT,HOSTPTR): New types.
* genmloop.sh (engine_resume_{full,fast}): Delete icount.
(cgen_cpu_max_extra_bytes): Declare.
* cgen-utils.c (cgen_cpu_max_extra_bytes): New function.
- * cgen.sh: s/@arch@/${arch}/ for cpu files.
-
* sim-cpu.h: New file. sim_cpu_base moved here.
Move sim_cpu_lookup decl here.
* sim-base.h: #include "sim-cpu.h".
Tue Feb 17 17:27:30 1998 Doug Evans <devans@seba.cygnus.com>
- * Make-common.in (CGEN_MAIN_SCM): Update.
* aclocal.m4 (USE_MAINTAINER_MODE): New variable.
* cgen-sim.h (SEMANTIC_CACHE_FN): Delete.
(SEMANTIC_FN): Rewrite declaration.
(DECODE): Update type of semantic_fast member.
({EX,SEM}_FN_NAME): Have only one version.
- * cgen.sh: Support building cpu.c.
* sim-base.h (sim_state_base): Delete conditionals surrounding
member scache_size.
* cgen-sim.h (DECODE): Always use switch for `read' for now.
(PAREXEC): Renamed from PARALLEL_EXEC. All uses updated.
(SEMANTIC{,_CACHE}_FN): Fix return type.
- * cgen.sh (decode): Add s/@arch@/$arch/.
* genmloop.sh (@cpu@_engine_run): Delete `current_state'.
(engine_resume): Likewise. Make `engine' volatile. Save copy
of cpu pointer in volatile object. Initialize read switch if
MAX_NR_PROCESSORS.
(sim_engine_nr_cpus) sim-engine.c, sim-engine.h: New function
-Thu Jan 29 12:13:01 1998 Doug Evans <devans@canuck.cygnus.com>
-
- * cgen.sh: Portably read parms past $9.
-
Fri Jan 23 14:20:54 1998 Doug Evans <devans@seba.cygnus.com>
* Make-common.in (stamp-tvals): New rule.
* cgen-scache.h: Deleted.
* Make-common.in (cgen-run.o,cgen-scache.o): Delete cgen-scache.h dep.
- (CGEN_CPU_SCM): Add sim-model.scm.
* cgen-scache.c: Only compile contents if WITH_SCACHE.
(scache_init): Use runtime computed size of SCACHE.
(scache_flush): Likewise.
static int
os_write_stdout (p, buf, len)
- host_callback *p;
+ host_callback *p ATTRIBUTE_UNUSED;
const char *buf;
int len;
{
static void
os_flush_stdout (p)
- host_callback *p;
+ host_callback *p ATTRIBUTE_UNUSED;
{
fflush (stdout);
}
static int
os_write_stderr (p, buf, len)
- host_callback *p;
+ host_callback *p ATTRIBUTE_UNUSED;
const char *buf;
int len;
{
static void
os_flush_stderr (p)
- host_callback *p;
+ host_callback *p ATTRIBUTE_UNUSED;
{
fflush (stderr);
}
/* VARARGS */
static void
#ifdef ANSI_PROTOTYPES
-os_printf_filtered (host_callback *p, const char *format, ...)
+os_printf_filtered (host_callback *p ATTRIBUTE_UNUSED, const char *format, ...)
#else
os_printf_filtered (p, va_alist)
host_callback *p;
/* VARARGS */
static void
#ifdef ANSI_PROTOTYPES
-os_vprintf_filtered (host_callback *p, const char *format, va_list args)
+os_vprintf_filtered (host_callback *p ATTRIBUTE_UNUSED, const char *format, va_list args)
#else
os_vprintf_filtered (p, format, args)
host_callback *p;
/* VARARGS */
static void
#ifdef ANSI_PROTOTYPES
-os_evprintf_filtered (host_callback *p, const char *format, va_list args)
+os_evprintf_filtered (host_callback *p ATTRIBUTE_UNUSED, const char *format, va_list args)
#else
os_evprintf_filtered (p, format, args)
host_callback *p;
/* VARARGS */
static void
#ifdef ANSI_PROTOTYPES
-os_error (host_callback *p, const char *format, ...)
+os_error (host_callback *p ATTRIBUTE_UNUSED, const char *format, ...)
#else
os_error (p, va_alist)
host_callback *p;
#include "bfd.h"
#include "callback.h"
#include "remote-sim.h"
+#include "ansidecl.h"
#include "../libiberty/alloca-conf.h"
static char *myname;
-
/* NOTE: sim_size() and sim_trace() are going away */
extern int sim_trace PARAMS ((SIM_DESC sd));
extern int getopt ();
+#ifdef NEED_UI_LOOP_HOOK
+/* Gdb foolery. This is only needed for gdb using a gui. */
+int (*ui_loop_hook) PARAMS ((int signo));
+#endif
+
static SIM_DESC sd;
static RETSIGTYPE
-cntrl_c (int sig)
+cntrl_c (int sig ATTRIBUTE_UNUSED)
{
if (! sim_stop (sd))
{
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