i40e: Rework register diagnostic

Register range, being subject to register diagnostic, can vary among
different NVMs. We will try to identify the full range and use it for
a register test. This is needed to avoid false test results. If we fail
to define the proper register range we will test only the first register
from that group.

Change-ID: Ieee7173c719733b61d3733177a94dc557eb7b3fd
Signed-off-by: Kamil Krawczyk <kamil.krawczyk@intel.com>
Signed-off-by: Jeff Kirsher <jeffrey.t.kirsher@intel.com>

diff --git a/drivers/net/ethernet/intel/i40e/i40e_diag.c b/drivers/net/ethernet/intel/i40e/i40e_diag.c
index b2380da..56438bd 100644 (file)
--- a/drivers/net/ethernet/intel/i40e/i40e_diag.c
+++ b/drivers/net/ethernet/intel/i40e/i40e_diag.c
@@ -67,17 +67,25 @@ static i40e_status i40e_diag_reg_pattern_test(struct i40e_hw *hw,
 
 struct i40e_diag_reg_test_info i40e_reg_list[] = {
        /* offset               mask         elements   stride */
-       {I40E_QTX_CTL(0),       0x0000FFBF,   4, I40E_QTX_CTL(1) - I40E_QTX_CTL(0)},
-       {I40E_PFINT_ITR0(0),    0x00000FFF,   3, I40E_PFINT_ITR0(1) - I40E_PFINT_ITR0(0)},
-       {I40E_PFINT_ITRN(0, 0), 0x00000FFF,   8, I40E_PFINT_ITRN(0, 1) - I40E_PFINT_ITRN(0, 0)},
-       {I40E_PFINT_ITRN(1, 0), 0x00000FFF,   8, I40E_PFINT_ITRN(1, 1) - I40E_PFINT_ITRN(1, 0)},
-       {I40E_PFINT_ITRN(2, 0), 0x00000FFF,   8, I40E_PFINT_ITRN(2, 1) - I40E_PFINT_ITRN(2, 0)},
-       {I40E_PFINT_STAT_CTL0,  0x0000000C,   1, 0},
-       {I40E_PFINT_LNKLST0,    0x00001FFF,   1, 0},
-       {I40E_PFINT_LNKLSTN(0), 0x000007FF,  64, I40E_PFINT_LNKLSTN(1) - I40E_PFINT_LNKLSTN(0)},
-       {I40E_QINT_TQCTL(0),    0x000000FF,  64, I40E_QINT_TQCTL(1) - I40E_QINT_TQCTL(0)},
-       {I40E_QINT_RQCTL(0),    0x000000FF,  64, I40E_QINT_RQCTL(1) - I40E_QINT_RQCTL(0)},
-       {I40E_PFINT_ICR0_ENA,   0xF7F20000,   1, 0},
+       {I40E_QTX_CTL(0),       0x0000FFBF, 1,
+               I40E_QTX_CTL(1) - I40E_QTX_CTL(0)},
+       {I40E_PFINT_ITR0(0),    0x00000FFF, 3,
+               I40E_PFINT_ITR0(1) - I40E_PFINT_ITR0(0)},
+       {I40E_PFINT_ITRN(0, 0), 0x00000FFF, 1,
+               I40E_PFINT_ITRN(0, 1) - I40E_PFINT_ITRN(0, 0)},
+       {I40E_PFINT_ITRN(1, 0), 0x00000FFF, 1,
+               I40E_PFINT_ITRN(1, 1) - I40E_PFINT_ITRN(1, 0)},
+       {I40E_PFINT_ITRN(2, 0), 0x00000FFF, 1,
+               I40E_PFINT_ITRN(2, 1) - I40E_PFINT_ITRN(2, 0)},
+       {I40E_PFINT_STAT_CTL0,  0x0000000C, 1, 0},
+       {I40E_PFINT_LNKLST0,    0x00001FFF, 1, 0},
+       {I40E_PFINT_LNKLSTN(0), 0x000007FF, 1,
+               I40E_PFINT_LNKLSTN(1) - I40E_PFINT_LNKLSTN(0)},
+       {I40E_QINT_TQCTL(0),    0x000000FF, 1,
+               I40E_QINT_TQCTL(1) - I40E_QINT_TQCTL(0)},
+       {I40E_QINT_RQCTL(0),    0x000000FF, 1,
+               I40E_QINT_RQCTL(1) - I40E_QINT_RQCTL(0)},
+       {I40E_PFINT_ICR0_ENA,   0xF7F20000, 1, 0},
        { 0 }
 };
 
@@ -93,9 +101,25 @@ i40e_status i40e_diag_reg_test(struct i40e_hw *hw)
        u32 reg, mask;
        u32 i, j;
 
-       for (i = 0; (i40e_reg_list[i].offset != 0) && !ret_code; i++) {
+       for (i = 0; i40e_reg_list[i].offset != 0 &&
+                                            !ret_code; i++) {
+
+               /* set actual reg range for dynamically allocated resources */
+               if (i40e_reg_list[i].offset == I40E_QTX_CTL(0) &&
+                   hw->func_caps.num_tx_qp != 0)
+                       i40e_reg_list[i].elements = hw->func_caps.num_tx_qp;
+               if ((i40e_reg_list[i].offset == I40E_PFINT_ITRN(0, 0) ||
+                    i40e_reg_list[i].offset == I40E_PFINT_ITRN(1, 0) ||
+                    i40e_reg_list[i].offset == I40E_PFINT_ITRN(2, 0) ||
+                    i40e_reg_list[i].offset == I40E_QINT_TQCTL(0) ||
+                    i40e_reg_list[i].offset == I40E_QINT_RQCTL(0)) &&
+                   hw->func_caps.num_msix_vectors != 0)
+                       i40e_reg_list[i].elements =
+                               hw->func_caps.num_msix_vectors - 1;
+
+               /* test register access */
                mask = i40e_reg_list[i].mask;
-               for (j = 0; (j < i40e_reg_list[i].elements) && !ret_code; j++) {
+               for (j = 0; j < i40e_reg_list[i].elements && !ret_code; j++) {
                        reg = i40e_reg_list[i].offset +
                              (j * i40e_reg_list[i].stride);
                        ret_code = i40e_diag_reg_pattern_test(hw, reg, mask);