return dev;
}
-#define PL011_INT_TX 0x20
-#define PL011_INT_RX 0x10
-
/* Flag Register, UARTFR */
#define PL011_FLAG_TXFE 0x80
#define PL011_FLAG_RXFF 0x40
s->flags |= PL011_FLAG_RXFE;
}
if (s->read_count == s->read_trigger - 1)
- s->int_level &= ~ PL011_INT_RX;
+ s->int_level &= ~ INT_RX;
trace_pl011_read_fifo(s->read_count);
s->rsr = c >> 8;
pl011_update(s);
/* XXX this blocks entire thread. Rewrite to use
* qemu_chr_fe_write and background I/O callbacks */
qemu_chr_fe_write_all(&s->chr, &ch, 1);
- s->int_level |= PL011_INT_TX;
+ s->int_level |= INT_TX;
pl011_update(s);
break;
case 1: /* UARTRSR/UARTECR */
s->flags |= PL011_FLAG_RXFF;
}
if (s->read_count == s->read_trigger) {
- s->int_level |= PL011_INT_RX;
+ s->int_level |= INT_RX;
pl011_update(s);
}
}