----------------------------
----- 6502 ALU implementation
+---- 6502 address calrucator
----------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.conv_std_logic_vector;
use work.motonesfpga_common.all;
-entity alu is
+entity address_calcurator is
generic ( dsize : integer := 8
);
port (
set_clk : in std_logic;
trig_clk : in std_logic;
+
+ --instruction reg
+ instruction : in std_logic_vector (dsize - 1 downto 0);
+ exec_cycle : in std_logic_vector (5 downto 0);
+
+ --control line.
pcl_inc_n : in std_logic;
sp_oe_n : in std_logic;
sp_push_n : in std_logic;
indir_n : in std_logic;
indir_x_n : in std_logic;
indir_y_n : in std_logic;
- arith_en_n : in std_logic;
- instruction : in std_logic_vector (dsize - 1 downto 0);
- exec_cycle : in std_logic_vector (5 downto 0);
- int_d_bus : inout std_logic_vector (dsize - 1 downto 0);
- acc_out : in std_logic_vector (dsize - 1 downto 0);
+
+ --in/out buses.
index_bus : in std_logic_vector (dsize - 1 downto 0);
bal : in std_logic_vector (dsize - 1 downto 0);
bah : in std_logic_vector (dsize - 1 downto 0);
- addr_back : out std_logic_vector (dsize - 1 downto 0);
- acc_in : out std_logic_vector (dsize - 1 downto 0);
+ int_d_bus : inout std_logic_vector (dsize - 1 downto 0);
+ addr_back_l : out std_logic_vector (dsize - 1 downto 0);
+ addr_back_h : out std_logic_vector (dsize - 1 downto 0);
abl : out std_logic_vector (dsize - 1 downto 0);
abh : out std_logic_vector (dsize - 1 downto 0);
- ea_carry : out std_logic;
- carry_in : in std_logic;
- negative : out std_logic;
- zero : out std_logic;
- carry_out : out std_logic;
- overflow : out std_logic
- );
-end alu;
+ ea_carry : out std_logic
+ );
+end address_calcurator;
-architecture rtl of alu is
+architecture rtl of address_calcurator is
component d_flip_flop
generic (
);
end component;
-component address_calculator
+component addr_alu
generic ( dsize : integer := 8
);
port (
);
end component;
-component alu_core
- generic ( dsize : integer := 8
- );
- port (
- sel : in std_logic_vector (3 downto 0);
- d1 : in std_logic_vector (dsize - 1 downto 0);
- d2 : in std_logic_vector (dsize - 1 downto 0);
- d_out : out std_logic_vector (dsize - 1 downto 0);
- carry_in : in std_logic;
- negative : out std_logic;
- zero : out std_logic;
- carry_out : out std_logic;
- overflow : out std_logic
- );
-end component;
constant ADDR_ADC : std_logic_vector (1 downto 0) := "00";
constant ADDR_INC : std_logic_vector (1 downto 0) := "01";
constant ADDR_DEC : std_logic_vector (1 downto 0) := "10";
constant ADDR_SIGNED_ADD : std_logic_vector (1 downto 0) := "11";
-constant ALU_AND : std_logic_vector (3 downto 0) := "0000";
-constant ALU_EOR : std_logic_vector (3 downto 0) := "0001";
-constant ALU_OR : std_logic_vector (3 downto 0) := "0010";
-constant ALU_BIT : std_logic_vector (3 downto 0) := "0011";
-constant ALU_ADC : std_logic_vector (3 downto 0) := "0100";
-constant ALU_SBC : std_logic_vector (3 downto 0) := "0101";
-constant ALU_CMP : std_logic_vector (3 downto 0) := "0110";
-constant ALU_ASL : std_logic_vector (3 downto 0) := "0111";
-constant ALU_LSR : std_logic_vector (3 downto 0) := "1000";
-constant ALU_ROL : std_logic_vector (3 downto 0) := "1001";
-constant ALU_ROR : std_logic_vector (3 downto 0) := "1010";
-constant ALU_INC : std_logic_vector (3 downto 0) := "1011";
-constant ALU_DEC : std_logic_vector (3 downto 0) := "1100";
-
---for indirect addressing.
constant T0 : std_logic_vector (5 downto 0) := "000000";
constant T1 : std_logic_vector (5 downto 0) := "000001";
signal addr_c : std_logic;
signal addr_c_reg : std_logic;
------------ signals for arithmatic ----------
-signal sel : std_logic_vector (3 downto 0);
-signal d1 : std_logic_vector (dsize - 1 downto 0);
-signal d2 : std_logic_vector (dsize - 1 downto 0);
-signal d_out : std_logic_vector (dsize - 1 downto 0);
-signal alu_out : std_logic_vector (dsize - 1 downto 0);
-
-signal n : std_logic;
-signal z : std_logic;
-signal c : std_logic;
-signal v : std_logic;
-
-signal arith_buf_we_n : std_logic;
-signal arith_buf_oe_n : std_logic;
-signal arith_reg_in : std_logic_vector (dsize - 1 downto 0);
-signal arith_reg : std_logic_vector (dsize - 1 downto 0);
-signal arith_reg_out : std_logic_vector (dsize - 1 downto 0);
-signal d_oe_n : std_logic;
-
begin
----------------------------------------
-- address calucurator instances ----
tmp_dff : d_flip_flop generic map (dsize)
port map(trig_clk, '1', '1', tmp_buf_we_n, tmp_reg_in, tmp_reg);
- addr_calc_inst : address_calculator generic map (dsize)
+ addr_calc_inst : addr_alu generic map (dsize)
port map (a_sel, addr1, addr2, addr_out, addr_c_in, addr_c);
ea_carry_dff_bit : d_flip_flop_bit
port map(trig_clk, '1', '1',
'0', addr_c, addr_c_reg);
- ----------------------------------------
- -- arithmatic operation instances ----
- ----------------------------------------
- arith_dff : d_flip_flop generic map (dsize)
- port map(trig_clk, '1', '1', arith_buf_we_n, arith_reg_in, arith_reg);
- arith_buf : tri_state_buffer generic map (dsize)
- port map (arith_buf_oe_n, arith_reg, arith_reg_out);
-
- alu_inst : alu_core generic map (dsize)
- port map (sel, d1, d2, alu_out, carry_in, n, z, c, v);
- alu_buf : tri_state_buffer generic map (dsize)
- port map (d_oe_n, alu_out, d_out);
-
-------------------------------
----- address calcuration -----
-------------------------------
ea_carry <= '0';
a_sel <= ADDR_INC;
addr1 <= bal;
- addr_back <= addr_out;
+ addr_back_l <= addr_out;
abl <= bal;
abh <= bah + addr_c;
+ addr_back_h <= addr_out;
elsif (sp_oe_n = '0') then
--stack operation...
--case pop
a_sel <= ADDR_INC;
addr1 <= bal;
- addr_back <= addr_out;
+ addr_back_l <= addr_out;
abl <= bal;
else
---case push
a_sel <= ADDR_DEC;
addr1 <= bal;
- addr_back <= addr_out;
+ addr_back_l <= addr_out;
abl <= bal;
end if;
elsif (zp_n = '0') then
---addr1 is pch.`
addr1 <= bah;
---rel val is on the d_bus.
- addr_back <= addr_out;
+ addr_back_h <= addr_out;
ea_carry <= '0';
--keep the value in the cycle
addr1 <= bal;
---rel val is on the d_bus.
addr2 <= int_d_bus;
- addr_back <= addr_out;
+ addr_back_l <= addr_out;
addr_c_in <= '0';
ea_carry <= addr_c_reg;
----addr_back is always bal for jmp/jsr instruction....
-----TODO must check later if it's ok.
- addr_back <= bal;
+ addr_back_l <= bal;
+ addr_back_h <= bah;
end if; --if (pcl_inc_n = '0') then
end process;
+end rtl;
-------------------------------
- ---- arithmatic operations-----
+ ---- ALU -----
-------------------------------
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.std_logic_unsigned.all;
+use ieee.std_logic_arith.conv_std_logic_vector;
+use work.motonesfpga_common.all;
+
+entity alu is
+ generic ( dsize : integer := 8
+ );
+ port (
+ set_clk : in std_logic;
+ trig_clk : in std_logic;
+ instruction : in std_logic_vector (dsize - 1 downto 0);
+ exec_cycle : in std_logic_vector (5 downto 0);
+ arith_en_n : in std_logic;
+ int_d_bus : inout std_logic_vector (dsize - 1 downto 0);
+ acc_in : out std_logic_vector (dsize - 1 downto 0);
+ acc_out : in std_logic_vector (dsize - 1 downto 0);
+ index_bus : in std_logic_vector (dsize - 1 downto 0);
+ carry_in : in std_logic;
+ negative : out std_logic;
+ zero : out std_logic;
+ carry_out : out std_logic;
+ overflow : out std_logic
+ );
+end alu;
+
+architecture rtl of alu is
+
+component alu_core
+ generic ( dsize : integer := 8
+ );
+ port (
+ sel : in std_logic_vector (3 downto 0);
+ d1 : in std_logic_vector (dsize - 1 downto 0);
+ d2 : in std_logic_vector (dsize - 1 downto 0);
+ d_out : out std_logic_vector (dsize - 1 downto 0);
+ carry_in : in std_logic;
+ negative : out std_logic;
+ zero : out std_logic;
+ carry_out : out std_logic;
+ overflow : out std_logic
+ );
+end component;
+
+component d_flip_flop
+ generic (
+ dsize : integer := 8
+ );
+ port (
+ clk : in std_logic;
+ res_n : in std_logic;
+ set_n : in std_logic;
+ we_n : in std_logic;
+ d : in std_logic_vector (dsize - 1 downto 0);
+ q : out std_logic_vector (dsize - 1 downto 0)
+ );
+end component;
+
+component tri_state_buffer
+ generic (
+ dsize : integer := 8
+ );
+ port (
+ oe_n : in std_logic;
+ d : in std_logic_vector (dsize - 1 downto 0);
+ q : out std_logic_vector (dsize - 1 downto 0)
+ );
+end component;
+
+constant ALU_AND : std_logic_vector (3 downto 0) := "0000";
+constant ALU_EOR : std_logic_vector (3 downto 0) := "0001";
+constant ALU_OR : std_logic_vector (3 downto 0) := "0010";
+constant ALU_BIT : std_logic_vector (3 downto 0) := "0011";
+constant ALU_ADC : std_logic_vector (3 downto 0) := "0100";
+constant ALU_SBC : std_logic_vector (3 downto 0) := "0101";
+constant ALU_CMP : std_logic_vector (3 downto 0) := "0110";
+constant ALU_ASL : std_logic_vector (3 downto 0) := "0111";
+constant ALU_LSR : std_logic_vector (3 downto 0) := "1000";
+constant ALU_ROL : std_logic_vector (3 downto 0) := "1001";
+constant ALU_ROR : std_logic_vector (3 downto 0) := "1010";
+constant ALU_INC : std_logic_vector (3 downto 0) := "1011";
+constant ALU_DEC : std_logic_vector (3 downto 0) := "1100";
+
+constant T0 : std_logic_vector (5 downto 0) := "000000";
+constant T1 : std_logic_vector (5 downto 0) := "000001";
+constant T2 : std_logic_vector (5 downto 0) := "000010";
+constant T3 : std_logic_vector (5 downto 0) := "000011";
+constant T4 : std_logic_vector (5 downto 0) := "000100";
+constant T5 : std_logic_vector (5 downto 0) := "000101";
+
+----------- signals for arithmatic ----------
+signal sel : std_logic_vector (3 downto 0);
+signal d1 : std_logic_vector (dsize - 1 downto 0);
+signal d2 : std_logic_vector (dsize - 1 downto 0);
+signal d_out : std_logic_vector (dsize - 1 downto 0);
+signal alu_out : std_logic_vector (dsize - 1 downto 0);
+
+signal n : std_logic;
+signal z : std_logic;
+signal c : std_logic;
+signal v : std_logic;
+
+signal arith_buf_we_n : std_logic;
+signal arith_buf_oe_n : std_logic;
+signal arith_reg_in : std_logic_vector (dsize - 1 downto 0);
+signal arith_reg : std_logic_vector (dsize - 1 downto 0);
+signal arith_reg_out : std_logic_vector (dsize - 1 downto 0);
+signal d_oe_n : std_logic;
+
+begin
+ ----------------------------------------
+ -- arithmatic operation instances ----
+ ----------------------------------------
+ arith_dff : d_flip_flop generic map (dsize)
+ port map(trig_clk, '1', '1', arith_buf_we_n, arith_reg_in, arith_reg);
+ arith_buf : tri_state_buffer generic map (dsize)
+ port map (arith_buf_oe_n, arith_reg, arith_reg_out);
+
+ alu_inst : alu_core generic map (dsize)
+ port map (sel, d1, d2, alu_out, carry_in, n, z, c, v);
+ alu_buf : tri_state_buffer generic map (dsize)
+ port map (d_oe_n, alu_out, d_out);
+
alu_arith_p : process (
arith_en_n,
instruction, exec_cycle, int_d_bus, acc_out,
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
-entity address_calculator is
+entity addr_alu is
generic ( dsize : integer := 8
);
port (
carry_in : in std_logic;
carry_out : out std_logic
);
-end address_calculator;
+end addr_alu;
-architecture rtl of address_calculator is
+architecture rtl of addr_alu is
constant ADDR_ADC : std_logic_vector (1 downto 0) := "00";
constant ADDR_INC : std_logic_vector (1 downto 0) := "01";
port map(ext_oe_n, int_dbus, ext_dbus);
end rtl;
-------------------------------------------
------ input data latch register
-------------------------------------------
-
-library ieee;
-use ieee.std_logic_1164.all;
-
-entity input_data_latch is
- generic (
- dsize : integer := 8
- );
- port (
- signal dbg_idl_val : out std_logic_vector (7 downto 0);
-
- clk : in std_logic;
- oe_n : in std_logic;
- we_n : in std_logic;
- int_dbus : in std_logic_vector (dsize - 1 downto 0);
- alu_bus : out std_logic_vector (dsize - 1 downto 0)
- );
-end input_data_latch;
-
-architecture rtl of input_data_latch is
-
-component d_flip_flop
- generic (
- dsize : integer := 8
- );
- port (
- clk : in std_logic;
- res_n : in std_logic;
- set_n : in std_logic;
- we_n : in std_logic;
- d : in std_logic_vector (dsize - 1 downto 0);
- q : out std_logic_vector (dsize - 1 downto 0)
- );
-end component;
-
-component tri_state_buffer
- generic (
- dsize : integer := 8
- );
- port (
- oe_n : in std_logic;
- d : in std_logic_vector (dsize - 1 downto 0);
- q : out std_logic_vector (dsize - 1 downto 0)
- );
-end component;
-
-signal latch_buf : std_logic_vector (dsize - 1 downto 0);
-
-begin
- latch_inst : d_flip_flop generic map (dsize)
- port map(clk, '1', '1', we_n, int_dbus, latch_buf);
- iput_data_tsb : tri_state_buffer generic map (dsize)
- port map(oe_n, latch_buf, alu_bus);
-
-end rtl;
----------------------------------------
--- status register component
entity decoder is
generic (dsize : integer := 8);
port (
--- signal dbg_ea_carry : out std_logic;
-
-
+ --input lines.
set_clk : in std_logic;
trig_clk : in std_logic;
res_n : in std_logic;
instruction : in std_logic_vector (dsize - 1 downto 0);
exec_cycle : in std_logic_vector (5 downto 0);
next_cycle : out std_logic_vector (5 downto 0);
+ ea_carry : in std_logic;
status_reg : inout std_logic_vector (dsize - 1 downto 0);
+
+ --general control.
inst_we_n : out std_logic;
ad_oe_n : out std_logic;
dbuf_int_oe_n : out std_logic;
- dl_al_we_n : out std_logic;
- dl_ah_we_n : out std_logic;
- dl_al_oe_n : out std_logic;
- dl_ah_oe_n : out std_logic;
- dl_dh_oe_n : out std_logic;
- pcl_inc_n : out std_logic;
+ r_nw : out std_logic;
+
+ ----control line for dual port registers.
+ idl_l_cmd : out std_logic_vector(3 downto 0);
+ idl_h_cmd : out std_logic_vector(3 downto 0);
pcl_cmd : out std_logic_vector(3 downto 0);
pch_cmd : out std_logic_vector(3 downto 0);
sp_cmd : out std_logic_vector(3 downto 0);
+ x_cmd : out std_logic_vector(3 downto 0);
+ y_cmd : out std_logic_vector(3 downto 0);
+ acc_cmd : out std_logic_vector(3 downto 0);
+
+ --addr calc control
+ pcl_inc_n : out std_logic;
sp_oe_n : out std_logic;
sp_push_n : out std_logic;
sp_pop_n : out std_logic;
- acc_cmd : out std_logic_vector(3 downto 0);
- x_cmd : out std_logic_vector(3 downto 0);
- y_cmd : out std_logic_vector(3 downto 0);
abs_xy_n : out std_logic;
- ea_carry : in std_logic;
pg_next_n : out std_logic;
zp_n : out std_logic;
zp_xy_n : out std_logic;
indir_n : out std_logic;
indir_x_n : out std_logic;
indir_y_n : out std_logic;
- arith_en_n : out std_logic;
+
+ ---status register
stat_dec_oe_n : out std_logic;
stat_bus_oe_n : out std_logic;
stat_set_flg_n : out std_logic;
stat_bus_all_n : out std_logic;
stat_bus_nz_n : out std_logic;
stat_alu_we_n : out std_logic;
+
+ --ALU control
+ arith_en_n : out std_logic;
+
+ --reset vectors.
r_vec_oe_n : out std_logic;
n_vec_oe_n : out std_logic;
- i_vec_oe_n : out std_logic;
- r_nw : out std_logic
+ i_vec_oe_n : out std_logic
+
;---for parameter check purpose!!!
check_bit : out std_logic_vector(1 to 5)
);
---for nmi handling
signal nmi_handled_n : std_logic;
--- page boundary handling
-signal wk_next_cycle : std_logic_vector (5 downto 0);
-signal wk_acc_cmd : std_logic_vector(3 downto 0);
-signal wk_x_cmd : std_logic_vector(3 downto 0);
-signal wk_y_cmd : std_logic_vector(3 downto 0);
-signal wk_stat_alu_we_n : std_logic;
signal ea_carry_reg : std_logic;
begin
ea_carry_inst: d_flip_flop_bit
port map(trig_clk, '1', '1', '0', ea_carry, ea_carry_reg);
- --acc,x,y next cycle is changed when it goes page across.
- --The conditional branch instructions all have the form xxy10000
- next_cycle <= wk_next_cycle;
- acc_cmd <= wk_acc_cmd(3) & '1' & wk_acc_cmd(1) & '1'
- when ea_carry = '1' and
- wk_next_cycle = T0 and instruction(4 downto 0) = "10000" else
- wk_acc_cmd;
-
- x_cmd <= wk_x_cmd(3) & '1' & wk_x_cmd(1 downto 0)
- when ea_carry = '1' and
- wk_next_cycle = T0 and instruction(4 downto 0) = "10000" else
- wk_x_cmd;
- y_cmd <= wk_y_cmd(3) & '1' & wk_y_cmd(1 downto 0)
- when ea_carry = '1' and
- wk_next_cycle = T0 and instruction(4 downto 0) = "10000" else
- wk_y_cmd;
- stat_alu_we_n <= '1' when ea_carry = '1' and
- wk_next_cycle = T0 and instruction(4 downto 0) = "10000" else
- wk_stat_alu_we_n;
-
main_p : process (set_clk, res_n, nmi_n)
-------------------------------------------------------------
--disable the last opration pins.
dbuf_int_oe_n <= '1';
- dl_al_we_n <= '1';
- dl_ah_we_n <= '1';
- dl_ah_oe_n <= '1';
- dl_dh_oe_n <= '1';
+
+ idl_l_cmd <= "1111";
+ idl_h_cmd <= "1111";
+ pcl_cmd <= "1111";
+ pch_cmd <= "1111";
sp_cmd <= "1111";
+ acc_cmd <= "1111";
+ x_cmd <= "1111";
+ y_cmd <= "1111";
+
sp_oe_n <= '1';
sp_push_n <= '1';
sp_pop_n <= '1';
- wk_acc_cmd <= "1111";
- wk_x_cmd <= "1111";
- wk_y_cmd <= "1111";
-
abs_xy_n <= '1';
pg_next_n <= '1';
zp_n <= '1';
stat_flg <= '1';
stat_bus_all_n <= '1';
stat_bus_nz_n <= '1';
- wk_stat_alu_we_n <= '1';
+ stat_alu_we_n <= '1';
r_vec_oe_n <= '1';
n_vec_oe_n <= '1';
--fetch opcode from where the latch is pointing to.
--latch > al.
- dl_al_oe_n <= '0';
+ idl_l_cmd <= "1110";
pcl_cmd <= "1110";
else
--fetch opcode and pcl increment.
pcl_cmd <= "1100";
- dl_al_oe_n <= '1';
+ --dl_al_oe_n <= '1';
end if;
ad_oe_n <= '0';
if (nmi_n = '0' and nmi_handled_n = '1') then
--start nmi handling...
--fetch_inst('1');
- wk_next_cycle <= N1;
+ next_cycle <= N1;
else
fetch_inst;
- wk_next_cycle <= T1;
+ next_cycle <= T1;
end if;
end procedure;
procedure single_inst is
begin
fetch_stop;
- wk_next_cycle <= T0;
+ next_cycle <= T0;
end procedure;
procedure fetch_imm is
--send data from data bus buffer.
--receiver is instruction dependent.
dbuf_int_oe_n <= '0';
- wk_next_cycle <= T0;
+ next_cycle <= T0;
end procedure;
procedure set_nz_from_bus is
procedure set_zc_from_alu is
begin
--status register n/z bit update.
- wk_stat_alu_we_n <= '0';
+ stat_alu_we_n <= '0';
stat_dec_oe_n <= '1';
status_reg <= "00000011";
end procedure;
procedure set_nz_from_alu is
begin
--status register n/z/c bit update.
- wk_stat_alu_we_n <= '0';
+ stat_alu_we_n <= '0';
stat_dec_oe_n <= '1';
status_reg <= "10000010";
end procedure;
procedure set_nzc_from_alu is
begin
--status register n/z/c bit update.
- wk_stat_alu_we_n <= '0';
+ stat_alu_we_n <= '0';
stat_dec_oe_n <= '1';
status_reg <= "10000011";
end procedure;
procedure set_nvz_from_alu is
begin
--status register n/z/v bit update.
- wk_stat_alu_we_n <= '0';
+ stat_alu_we_n <= '0';
stat_dec_oe_n <= '1';
status_reg <= "11000010";
end procedure;
procedure set_nvzc_from_alu is
begin
- wk_stat_alu_we_n <= '0';
+ stat_alu_we_n <= '0';
stat_dec_oe_n <= '1';
status_reg <= "11000011";
end procedure;
fetch_next;
--latch abs low data.
dbuf_int_oe_n <= '0';
- dl_al_we_n <= '0';
- wk_next_cycle <= T2;
+ --dl_al_we_n <= '0';
+ next_cycle <= T2;
end procedure;
procedure abs_fetch_high is
begin
d_print("abs (xy) 3");
- dl_al_we_n <= '1';
+ --dl_al_we_n <= '1';
--latch abs hi data.
fetch_next;
dbuf_int_oe_n <= '0';
- dl_ah_we_n <= '0';
- wk_next_cycle <= T3;
+ --dl_ah_we_n <= '0';
+ next_cycle <= T3;
end procedure;
procedure abs_latch_out is
begin
--d_print("abs 4");
- dl_ah_we_n <= '1';
+ --dl_ah_we_n <= '1';
fetch_stop;
--latch > al/ah.
- dl_al_oe_n <= '0';
- dl_ah_oe_n <= '0';
+ --dl_al_oe_n <= '0';
+ --dl_ah_oe_n <= '0';
end procedure;
procedure ea_x_out is
begin
-----calucurate and output effective addr
- back_oe(wk_x_cmd, '0');
+ back_oe(x_cmd, '0');
abs_xy_n <= '0';
end procedure;
procedure ea_y_out is
begin
- back_oe(wk_y_cmd, '0');
+ back_oe(y_cmd, '0');
abs_xy_n <= '0';
end procedure;
elsif exec_cycle = T2 then
fetch_stop;
dbuf_int_oe_n <= '0';
- dl_al_we_n <= '1';
+ --dl_al_we_n <= '1';
--calc zp.
- dl_al_oe_n <= '0';
+ --dl_al_oe_n <= '0';
zp_n <= '0';
- wk_next_cycle <= T0;
+ next_cycle <= T0;
end if;
end procedure;
elsif exec_cycle = T3 then
abs_latch_out;
dbuf_int_oe_n <= '0';
- wk_next_cycle <= T0;
+ next_cycle <= T0;
end if;
end procedure;
procedure a2_page_next is
begin
--close open gate if page boundary crossed.
- back_we(wk_acc_cmd, '1');
- front_we(wk_acc_cmd, '1');
- front_we(wk_x_cmd, '1');
- front_we(wk_y_cmd, '1');
- wk_stat_alu_we_n <= '1';
+ back_we(acc_cmd, '1');
+ front_we(acc_cmd, '1');
+ front_we(x_cmd, '1');
+ front_we(y_cmd, '1');
+ stat_alu_we_n <= '1';
end procedure;
procedure a2_abs_xy (is_x : in boolean) is
end if;
dbuf_int_oe_n <= '0';
- wk_next_cycle <= T0;
+ next_cycle <= T0;
d_print("absx step 1");
elsif (exec_cycle = T0 and ea_carry_reg = '1') then
--case page boundary crossed.
d_print("absx 5 (page boudary crossed.)");
--next page.
pg_next_n <= '0';
- wk_next_cycle <= T0;
+ next_cycle <= T0;
end if;
end procedure;
fetch_stop;
--output BAL only
dbuf_int_oe_n <= '0';
- dl_al_we_n <= '1';
+ --dl_al_we_n <= '1';
--calc zp.
- dl_al_oe_n <= '0';
+ --dl_al_oe_n <= '0';
zp_n <= '0';
- wk_next_cycle <= T3;
+ next_cycle <= T3;
elsif exec_cycle = T3 then
--t3 zp, xy
zp_xy_n <= '0';
if (is_x = true) then
- back_oe(wk_x_cmd, '0');
+ back_oe(x_cmd, '0');
else
- back_oe(wk_y_cmd, '0');
+ back_oe(y_cmd, '0');
end if;
- wk_next_cycle <= T0;
+ next_cycle <= T0;
end if;
end procedure;
if exec_cycle = T1 then
fetch_low;
--get IAL
- dl_al_we_n <= '0';
+ --dl_al_we_n <= '0';
elsif exec_cycle = T2 then
fetch_stop;
- dl_al_we_n <= '1';
+ --dl_al_we_n <= '1';
---address is 00:IAL
--output BAL @IAL
indir_y_n <= '0';
- dl_al_oe_n <= '0';
+ --dl_al_oe_n <= '0';
dbuf_int_oe_n <= '0';
- wk_next_cycle <= T3;
+ next_cycle <= T3;
elsif exec_cycle = T3 then
indir_y_n <= '0';
- dl_al_oe_n <= '0';
+ --dl_al_oe_n <= '0';
--output BAH @IAL+1
dbuf_int_oe_n <= '0';
- wk_next_cycle <= T4;
+ next_cycle <= T4;
elsif exec_cycle = T4 then
- dl_al_oe_n <= '1';
+ --dl_al_oe_n <= '1';
dbuf_int_oe_n <= '1';
--add index y.
pg_next_n <= '1';
- back_oe(wk_y_cmd, '0');
+ back_oe(y_cmd, '0');
indir_y_n <= '0';
dbuf_int_oe_n <= '0';
if (ea_carry = '1') then
- wk_next_cycle <= T5;
+ next_cycle <= T5;
else
- wk_next_cycle <= T0;
+ next_cycle <= T0;
end if;
elsif (exec_cycle = T5) then
--case page boundary crossed.
d_print("(indir), y (page boudary crossed.)");
--next page.
pg_next_n <= '0';
- wk_next_cycle <= T0;
+ next_cycle <= T0;
end if;
end procedure;
if exec_cycle = T1 then
fetch_low;
--get IAL
- dl_al_we_n <= '0';
+ --dl_al_we_n <= '0';
elsif exec_cycle = T2 then
fetch_stop;
- dl_al_we_n <= '1';
+ --dl_al_we_n <= '1';
---address is 00:IAL
--output BAL @IAL, but cycle #2 is discarded
indir_x_n <= '0';
- dl_al_oe_n <= '0';
- wk_next_cycle <= T3;
+ --dl_al_oe_n <= '0';
+ next_cycle <= T3;
elsif exec_cycle = T3 then
indir_x_n <= '0';
- dl_al_oe_n <= '1';
+ --dl_al_oe_n <= '1';
--output BAH @IAL+x
dbuf_int_oe_n <= '0';
- back_oe(wk_x_cmd, '0');
- wk_next_cycle <= T4;
+ back_oe(x_cmd, '0');
+ next_cycle <= T4;
elsif exec_cycle = T4 then
indir_x_n <= '0';
--output BAH @IAL+x+1
dbuf_int_oe_n <= '0';
- back_oe(wk_x_cmd, '0');
+ back_oe(x_cmd, '0');
- wk_next_cycle <= T5;
+ next_cycle <= T5;
elsif (exec_cycle = T5) then
indir_x_n <= '0';
- wk_next_cycle <= T0;
+ next_cycle <= T0;
end if;
end procedure;
elsif exec_cycle = T2 then
fetch_stop;
dbuf_int_oe_n <= '1';
- dl_al_we_n <= '1';
+ --dl_al_we_n <= '1';
--calc zp.
- dl_al_oe_n <= '0';
+ --dl_al_oe_n <= '0';
zp_n <= '0';
r_nw <= '0';
- wk_next_cycle <= T0;
+ next_cycle <= T0;
end if;
end procedure;
elsif exec_cycle = T2 then
fetch_stop;
dbuf_int_oe_n <= '1';
- dl_al_we_n <= '1';
+ --dl_al_we_n <= '1';
--calc zp.
- dl_al_oe_n <= '0';
+ --dl_al_oe_n <= '0';
zp_n <= '0';
- wk_next_cycle <= T3;
+ next_cycle <= T3;
elsif exec_cycle = T3 then
--calc zp + index.
- dl_al_oe_n <= '0';
+ --dl_al_oe_n <= '0';
zp_n <= '0';
zp_xy_n <= '0';
if (is_x = true) then
- back_oe(wk_x_cmd, '0');
+ back_oe(x_cmd, '0');
else
- back_oe(wk_y_cmd, '0');
+ back_oe(y_cmd, '0');
end if;
--write data
r_nw <= '0';
- wk_next_cycle <= T0;
+ next_cycle <= T0;
end if;
end procedure;
abs_latch_out;
dbuf_int_oe_n <= '1';
r_nw <= '0';
- wk_next_cycle <= T0;
+ next_cycle <= T0;
end if;
end procedure;
else
ea_y_out;
end if;
- wk_next_cycle <= T4;
+ next_cycle <= T4;
elsif exec_cycle = T4 then
if (ea_carry_reg = '1') then
pg_next_n <= '0';
ea_y_out;
end if;
r_nw <= '0';
- wk_next_cycle <= T0;
+ next_cycle <= T0;
end if;
end procedure;
if exec_cycle = T1 then
fetch_low;
--get IAL
- dl_al_we_n <= '0';
+ --dl_al_we_n <= '0';
elsif exec_cycle = T2 then
fetch_stop;
- dl_al_we_n <= '1';
+ --dl_al_we_n <= '1';
---address is 00:IAL
--output BAL @IAL
indir_y_n <= '0';
- dl_al_oe_n <= '0';
+ --dl_al_oe_n <= '0';
dbuf_int_oe_n <= '0';
- wk_next_cycle <= T3;
+ next_cycle <= T3;
elsif exec_cycle = T3 then
indir_y_n <= '0';
- dl_al_oe_n <= '0';
+ --dl_al_oe_n <= '0';
--output BAH @IAL+1
dbuf_int_oe_n <= '0';
- wk_next_cycle <= T4;
+ next_cycle <= T4;
elsif exec_cycle = T4 then
- dl_al_oe_n <= '1';
+ --dl_al_oe_n <= '1';
dbuf_int_oe_n <= '1';
--add index y.
pg_next_n <= '1';
- back_oe(wk_y_cmd, '0');
+ back_oe(y_cmd, '0');
indir_y_n <= '0';
- wk_next_cycle <= T5;
+ next_cycle <= T5;
elsif exec_cycle = T5 then
--page handling.
- back_oe(wk_y_cmd, '1');
+ back_oe(y_cmd, '1');
indir_y_n <= '0';
--ea_carry reg is suspicious. timing is not garanteed...
pg_next_n <= '1';
end if;
r_nw <= '0';
- wk_next_cycle <= T0;
+ next_cycle <= T0;
end if;
end procedure;
if exec_cycle = T1 then
fetch_low;
--get IAL
- dl_al_we_n <= '0';
+ --dl_al_we_n <= '0';
elsif exec_cycle = T2 then
fetch_stop;
- dl_al_we_n <= '1';
+ --dl_al_we_n <= '1';
---address is 00:IAL
--output BAL @IAL, but cycle #2 is discarded
indir_x_n <= '0';
- dl_al_oe_n <= '0';
- wk_next_cycle <= T3;
+ --dl_al_oe_n <= '0';
+ next_cycle <= T3;
elsif exec_cycle = T3 then
indir_x_n <= '0';
- dl_al_oe_n <= '1';
+ --dl_al_oe_n <= '1';
--output BAH @IAL+x
dbuf_int_oe_n <= '0';
- back_oe(wk_x_cmd, '0');
- wk_next_cycle <= T4;
+ back_oe(x_cmd, '0');
+ next_cycle <= T4;
elsif exec_cycle = T4 then
indir_x_n <= '0';
--output BAH @IAL+x+1
dbuf_int_oe_n <= '0';
- back_oe(wk_x_cmd, '0');
+ back_oe(x_cmd, '0');
- wk_next_cycle <= T5;
+ next_cycle <= T5;
elsif (exec_cycle = T5) then
indir_x_n <= '0';
dbuf_int_oe_n <= '1';
r_nw <= '0';
- wk_next_cycle <= T0;
+ next_cycle <= T0;
end if;
end procedure;
fetch_low;
elsif exec_cycle = T2 then
fetch_stop;
- dl_al_we_n <= '1';
+ --dl_al_we_n <= '1';
--t2 cycle read and,
- dl_al_oe_n <= '0';
+ --dl_al_oe_n <= '0';
zp_n <= '0';
--keep data in the alu reg.
arith_en_n <= '0';
dbuf_int_oe_n <= '0';
- wk_next_cycle <= T3;
+ next_cycle <= T3;
elsif exec_cycle = T3 then
--t3 fix alu internal register.
- dl_al_oe_n <= '0';
+ --dl_al_oe_n <= '0';
zp_n <= '0';
arith_en_n <= '0';
dbuf_int_oe_n <= '1';
- wk_next_cycle <= T4;
+ next_cycle <= T4;
elsif exec_cycle = T4 then
--t5 cycle writes modified value.
- dl_al_oe_n <= '0';
+ --dl_al_oe_n <= '0';
zp_n <= '0';
r_nw <= '0';
arith_en_n <= '0';
- wk_next_cycle <= T0;
+ next_cycle <= T0;
end if;
end procedure;
elsif exec_cycle = T2 then
fetch_stop;
dbuf_int_oe_n <= '1';
- dl_al_we_n <= '1';
+ --dl_al_we_n <= '1';
--t2 cycle read bal only.
- dl_al_oe_n <= '0';
+ --dl_al_oe_n <= '0';
zp_n <= '0';
- wk_next_cycle <= T3;
+ next_cycle <= T3;
elsif exec_cycle = T3 then
--t3 cycle read bal + x
- dl_al_oe_n <= '0';
+ --dl_al_oe_n <= '0';
zp_n <= '0';
zp_xy_n <= '0';
- back_oe(wk_x_cmd, '0');
+ back_oe(x_cmd, '0');
--keep data in the alu reg.
arith_en_n <= '0';
dbuf_int_oe_n <= '0';
- wk_next_cycle <= T4;
+ next_cycle <= T4;
elsif exec_cycle = T4 then
- dl_al_oe_n <= '0';
+ --dl_al_oe_n <= '0';
zp_n <= '0';
zp_xy_n <= '0';
- back_oe(wk_x_cmd, '0');
+ back_oe(x_cmd, '0');
--fix alu internal register.
arith_en_n <= '0';
dbuf_int_oe_n <= '1';
- wk_next_cycle <= T5;
+ next_cycle <= T5;
elsif exec_cycle = T5 then
dbuf_int_oe_n <= '1';
--t5 cycle writes modified value.
- dl_al_oe_n <= '0';
+ --dl_al_oe_n <= '0';
zp_n <= '0';
zp_xy_n <= '0';
- back_oe(wk_x_cmd, '0');
+ back_oe(x_cmd, '0');
r_nw <= '0';
arith_en_n <= '0';
- wk_next_cycle <= T0;
+ next_cycle <= T0;
end if;
end procedure;
--keep data in the alu reg.
arith_en_n <= '0';
dbuf_int_oe_n <= '0';
- wk_next_cycle <= T4;
+ next_cycle <= T4;
elsif exec_cycle = T4 then
abs_latch_out;
--fix alu internal register.
arith_en_n <= '0';
dbuf_int_oe_n <= '1';
- wk_next_cycle <= T5;
+ next_cycle <= T5;
elsif exec_cycle = T5 then
dbuf_int_oe_n <= '1';
--t5 cycle writes modified value.
r_nw <= '0';
arith_en_n <= '0';
- wk_next_cycle <= T0;
+ next_cycle <= T0;
end if;
end procedure;
abs_latch_out;
ea_x_out;
dbuf_int_oe_n <= '0';
- wk_next_cycle <= T4;
+ next_cycle <= T4;
elsif exec_cycle = T4 then
abs_latch_out;
--keep data in the alu reg.
arith_en_n <= '0';
dbuf_int_oe_n <= '0';
- wk_next_cycle <= T5;
+ next_cycle <= T5;
elsif exec_cycle = T5 then
--fix alu internal register.
arith_en_n <= '0';
dbuf_int_oe_n <= '1';
- wk_next_cycle <= T6;
+ next_cycle <= T6;
elsif exec_cycle = T6 then
--t5 cycle writes modified value.
r_nw <= '0';
arith_en_n <= '0';
- wk_next_cycle <= T0;
+ next_cycle <= T0;
end if;
end procedure;
begin
if exec_cycle = T1 then
fetch_stop;
- wk_next_cycle <= T2;
+ next_cycle <= T2;
elsif exec_cycle = T2 then
back_oe(sp_cmd, '0');
back_we(sp_cmd, '0');
sp_push_n <= '0';
sp_oe_n <= '0';
r_nw <= '0';
- wk_next_cycle <= T0;
+ next_cycle <= T0;
end if;
end procedure;
begin
if exec_cycle = T1 then
fetch_stop;
- wk_next_cycle <= T2;
+ next_cycle <= T2;
elsif exec_cycle = T2 then
--stack decrement first.
back_we(sp_cmd, '0');
sp_pop_n <= '0';
sp_oe_n <= '0';
- wk_next_cycle <= T3;
+ next_cycle <= T3;
elsif exec_cycle = T3 then
sp_pop_n <= '1';
back_oe(sp_cmd, '0');
sp_oe_n <= '0';
dbuf_int_oe_n <= '0';
- wk_next_cycle <= T0;
+ next_cycle <= T0;
end if;
end procedure;
--latch rel value.
dbuf_int_oe_n <= '0';
- dl_ah_we_n <= '0';
- wk_next_cycle <= T2;
+ --dl_ah_we_n <= '0';
+ next_cycle <= T2;
else
d_print("no branch");
- wk_next_cycle <= T0;
+ next_cycle <= T0;
end if;
elsif exec_cycle = T2 then
d_print("rel ea");
fetch_stop;
dbuf_int_oe_n <= '1';
- dl_ah_we_n <= '1';
+ --dl_ah_we_n <= '1';
--calc relative addr.
rel_calc_n <= '0';
pg_next_n <= '1';
- dl_dh_oe_n <= '0';
+ --dl_dh_oe_n <= '0';
back_oe(pcl_cmd, '0');
back_oe(pch_cmd, '0');
back_we(pcl_cmd, '0');
- wk_next_cycle <= T0;
+ next_cycle <= T0;
elsif (exec_cycle = T0 and ea_carry = '1') then
d_print("page crossed.");
--page crossed. adh calc.
back_oe(pcl_cmd, '0');
back_oe(pch_cmd, '0');
back_we(pch_cmd, '0');
- dl_dh_oe_n <= '0';
+ --dl_dh_oe_n <= '0';
rel_calc_n <= '0';
pg_next_n <= '0';
- wk_next_cycle <= T0;
+ next_cycle <= T0;
end if;
end procedure;
stat_flg <= '1';
stat_bus_all_n <= '1';
stat_bus_nz_n <= '1';
- wk_stat_alu_we_n <= '1';
+ stat_alu_we_n <= '1';
--pc l/h is reset vector.
pcl_cmd <= "1110";
pch_cmd <= "1110";
- wk_next_cycle <= R0;
+ next_cycle <= R0;
elsif (rising_edge(set_clk)) then
d_print(string'("-"));
disable_pins;
inst_we_n <= '1';
ad_oe_n <= '1';
- dl_al_oe_n <= '1';
+ --dl_al_oe_n <= '1';
pcl_inc_n <= '1';
pcl_cmd <= "1111";
pch_cmd <= "1111";
d_print("decode and execute inst: "
& conv_hex8(conv_integer(instruction)));
--disable pin for jmp instruction
- dl_al_oe_n <= '1';
+ --dl_al_oe_n <= '1';
back_we(pcl_cmd, '1');
front_we(pch_cmd, '1');
--asl acc mode.
d_print("asl");
arith_en_n <= '0';
- back_oe(wk_acc_cmd, '0');
- front_we(wk_acc_cmd, '0');
+ back_oe(acc_cmd, '0');
+ front_we(acc_cmd, '0');
set_nzc_from_alu;
single_inst;
elsif instruction = conv_std_logic_vector(16#ca#, dsize) then
d_print("dex");
arith_en_n <= '0';
- back_oe(wk_x_cmd, '0');
- front_we(wk_x_cmd, '0');
+ back_oe(x_cmd, '0');
+ front_we(x_cmd, '0');
--set nz bit.
set_nz_from_bus;
single_inst;
elsif instruction = conv_std_logic_vector(16#88#, dsize) then
d_print("dey");
arith_en_n <= '0';
- back_oe(wk_y_cmd, '0');
- front_we(wk_y_cmd, '0');
+ back_oe(y_cmd, '0');
+ front_we(y_cmd, '0');
--set nz bit.
set_nz_from_bus;
single_inst;
elsif instruction = conv_std_logic_vector(16#e8#, dsize) then
d_print("inx");
arith_en_n <= '0';
- back_oe(wk_x_cmd, '0');
- front_we(wk_x_cmd, '0');
+ back_oe(x_cmd, '0');
+ front_we(x_cmd, '0');
--set nz bit.
set_nz_from_bus;
single_inst;
elsif instruction = conv_std_logic_vector(16#c8#, dsize) then
d_print("iny");
arith_en_n <= '0';
- back_oe(wk_y_cmd, '0');
- front_we(wk_y_cmd, '0');
+ back_oe(y_cmd, '0');
+ front_we(y_cmd, '0');
set_nz_from_bus;
single_inst;
--lsr acc mode
d_print("lsr");
arith_en_n <= '0';
- back_oe(wk_acc_cmd, '0');
- front_we(wk_acc_cmd, '0');
+ back_oe(acc_cmd, '0');
+ front_we(acc_cmd, '0');
set_zc_from_alu;
single_inst;
--rol acc
d_print("rol");
arith_en_n <= '0';
- back_oe(wk_acc_cmd, '0');
- front_we(wk_acc_cmd, '0');
+ back_oe(acc_cmd, '0');
+ front_we(acc_cmd, '0');
set_nzc_from_alu;
single_inst;
--ror acc
d_print("ror");
arith_en_n <= '0';
- back_oe(wk_acc_cmd, '0');
- front_we(wk_acc_cmd, '0');
+ back_oe(acc_cmd, '0');
+ front_we(acc_cmd, '0');
set_nzc_from_alu;
single_inst;
d_print("tax");
set_nz_from_bus;
single_inst;
- front_oe(wk_acc_cmd, '0');
- front_we(wk_x_cmd, '0');
+ front_oe(acc_cmd, '0');
+ front_we(x_cmd, '0');
elsif instruction = conv_std_logic_vector(16#a8#, dsize) then
d_print("tay");
set_nz_from_bus;
single_inst;
- front_oe(wk_acc_cmd, '0');
- front_we(wk_y_cmd, '0');
+ front_oe(acc_cmd, '0');
+ front_we(y_cmd, '0');
elsif instruction = conv_std_logic_vector(16#ba#, dsize) then
d_print("tsx");
set_nz_from_bus;
single_inst;
front_oe(sp_cmd, '0');
- front_we(wk_x_cmd, '0');
+ front_we(x_cmd, '0');
elsif instruction = conv_std_logic_vector(16#8a#, dsize) then
d_print("txa");
set_nz_from_bus;
single_inst;
- front_oe(wk_x_cmd, '0');
- front_we(wk_acc_cmd, '0');
+ front_oe(x_cmd, '0');
+ front_we(acc_cmd, '0');
elsif instruction = conv_std_logic_vector(16#9a#, dsize) then
d_print("txs");
set_nz_from_bus;
single_inst;
- front_oe(wk_x_cmd, '0');
+ front_oe(x_cmd, '0');
front_we(sp_cmd, '0');
elsif instruction = conv_std_logic_vector(16#98#, dsize) then
d_print("tya");
set_nz_from_bus;
single_inst;
- front_oe(wk_y_cmd, '0');
- front_we(wk_acc_cmd, '0');
+ front_oe(y_cmd, '0');
+ front_we(acc_cmd, '0');
d_print("adc");
fetch_imm;
arith_en_n <= '0';
- back_oe(wk_acc_cmd, '0');
- back_we(wk_acc_cmd, '0');
+ back_oe(acc_cmd, '0');
+ back_we(acc_cmd, '0');
set_nvzc_from_alu;
elsif instruction = conv_std_logic_vector(16#65#, dsize) then
a2_zp;
if exec_cycle = T2 then
arith_en_n <= '0';
- back_oe(wk_acc_cmd, '0');
- back_we(wk_acc_cmd, '0');
+ back_oe(acc_cmd, '0');
+ back_we(acc_cmd, '0');
set_nvzc_from_alu;
end if;
a2_zp_xy(true);
if exec_cycle = T3 then
arith_en_n <= '0';
- back_oe(wk_acc_cmd, '0');
- back_we(wk_acc_cmd, '0');
+ back_oe(acc_cmd, '0');
+ back_we(acc_cmd, '0');
set_nvzc_from_alu;
end if;
a2_abs;
if exec_cycle = T3 then
arith_en_n <= '0';
- back_oe(wk_acc_cmd, '0');
- back_we(wk_acc_cmd, '0');
+ back_oe(acc_cmd, '0');
+ back_we(acc_cmd, '0');
set_nvzc_from_alu;
end if;
a2_abs_xy(true);
if exec_cycle = T3 or exec_cycle = T0 then
arith_en_n <= '0';
- back_oe(wk_acc_cmd, '0');
- back_we(wk_acc_cmd, '0');
+ back_oe(acc_cmd, '0');
+ back_we(acc_cmd, '0');
set_nvzc_from_alu;
end if;
a2_abs_xy(false);
if exec_cycle = T3 or exec_cycle = T0 then
arith_en_n <= '0';
- back_oe(wk_acc_cmd, '0');
- back_we(wk_acc_cmd, '0');
+ back_oe(acc_cmd, '0');
+ back_we(acc_cmd, '0');
set_nvzc_from_alu;
end if;
a2_indir_x;
if exec_cycle = T5 then
arith_en_n <= '0';
- back_oe(wk_acc_cmd, '0');
- back_we(wk_acc_cmd, '0');
+ back_oe(acc_cmd, '0');
+ back_we(acc_cmd, '0');
set_nvzc_from_alu;
end if;
a2_indir_y;
if exec_cycle = T4 or exec_cycle = T0 then
arith_en_n <= '0';
- back_oe(wk_acc_cmd, '0');
- back_we(wk_acc_cmd, '0');
+ back_oe(acc_cmd, '0');
+ back_we(acc_cmd, '0');
set_nvzc_from_alu;
end if;
d_print("and");
fetch_imm;
arith_en_n <= '0';
- back_oe(wk_acc_cmd, '0');
- back_we(wk_acc_cmd, '0');
+ back_oe(acc_cmd, '0');
+ back_we(acc_cmd, '0');
set_nz_from_alu;
elsif instruction = conv_std_logic_vector(16#25#, dsize) then
a2_zp;
if exec_cycle = T2 then
arith_en_n <= '0';
- back_oe(wk_acc_cmd, '0');
- back_we(wk_acc_cmd, '0');
+ back_oe(acc_cmd, '0');
+ back_we(acc_cmd, '0');
set_nz_from_alu;
end if;
a2_zp_xy(true);
if exec_cycle = T3 then
arith_en_n <= '0';
- back_oe(wk_acc_cmd, '0');
- back_we(wk_acc_cmd, '0');
+ back_oe(acc_cmd, '0');
+ back_we(acc_cmd, '0');
set_nz_from_alu;
end if;
a2_abs;
if exec_cycle = T3 then
arith_en_n <= '0';
- back_oe(wk_acc_cmd, '0');
- back_we(wk_acc_cmd, '0');
+ back_oe(acc_cmd, '0');
+ back_we(acc_cmd, '0');
set_nz_from_alu;
end if;
a2_abs_xy(true);
if exec_cycle = T3 or exec_cycle = T0 then
arith_en_n <= '0';
- back_oe(wk_acc_cmd, '0');
- back_we(wk_acc_cmd, '0');
+ back_oe(acc_cmd, '0');
+ back_we(acc_cmd, '0');
set_nz_from_alu;
end if;
a2_abs_xy(false);
if exec_cycle = T3 or exec_cycle = T0 then
arith_en_n <= '0';
- back_oe(wk_acc_cmd, '0');
- back_we(wk_acc_cmd, '0');
+ back_oe(acc_cmd, '0');
+ back_we(acc_cmd, '0');
set_nz_from_alu;
end if;
a2_indir_x;
if exec_cycle = T5 then
arith_en_n <= '0';
- back_oe(wk_acc_cmd, '0');
- back_we(wk_acc_cmd, '0');
+ back_oe(acc_cmd, '0');
+ back_we(acc_cmd, '0');
set_nz_from_alu;
end if;
a2_indir_y;
if exec_cycle = T4 or exec_cycle = T0 then
arith_en_n <= '0';
- back_oe(wk_acc_cmd, '0');
- back_we(wk_acc_cmd, '0');
+ back_oe(acc_cmd, '0');
+ back_we(acc_cmd, '0');
set_nz_from_alu;
end if;
a2_zp;
if exec_cycle = T2 then
arith_en_n <= '0';
- back_oe(wk_acc_cmd, '0');
+ back_oe(acc_cmd, '0');
set_nvz_from_alu;
end if;
a2_abs;
if exec_cycle = T3 then
arith_en_n <= '0';
- back_oe(wk_acc_cmd, '0');
+ back_oe(acc_cmd, '0');
set_nvz_from_alu;
end if;
d_print("cmp");
fetch_imm;
arith_en_n <= '0';
- back_oe(wk_acc_cmd, '0');
+ back_oe(acc_cmd, '0');
set_nzc_from_alu;
elsif instruction = conv_std_logic_vector(16#c5#, dsize) then
a2_zp;
if exec_cycle = T2 then
arith_en_n <= '0';
- back_oe(wk_acc_cmd, '0');
+ back_oe(acc_cmd, '0');
set_nzc_from_alu;
end if;
a2_zp_xy(true);
if exec_cycle = T3 then
arith_en_n <= '0';
- back_oe(wk_acc_cmd, '0');
+ back_oe(acc_cmd, '0');
set_nzc_from_alu;
end if;
a2_abs;
if exec_cycle = T3 then
arith_en_n <= '0';
- back_oe(wk_acc_cmd, '0');
+ back_oe(acc_cmd, '0');
set_nzc_from_alu;
end if;
a2_abs_xy(true);
if exec_cycle = T3 or exec_cycle = T0 then
arith_en_n <= '0';
- back_oe(wk_acc_cmd, '0');
+ back_oe(acc_cmd, '0');
set_nzc_from_alu;
end if;
a2_abs_xy(false);
if exec_cycle = T3 or exec_cycle = T0 then
arith_en_n <= '0';
- back_oe(wk_acc_cmd, '0');
+ back_oe(acc_cmd, '0');
set_nzc_from_alu;
end if;
a2_indir_x;
if exec_cycle = T5 then
arith_en_n <= '0';
- back_oe(wk_acc_cmd, '0');
+ back_oe(acc_cmd, '0');
set_nzc_from_alu;
end if;
a2_indir_y;
if exec_cycle = T4 or exec_cycle = T0 then
arith_en_n <= '0';
- back_oe(wk_acc_cmd, '0');
+ back_oe(acc_cmd, '0');
set_nzc_from_alu;
end if;
d_print("cpx");
fetch_imm;
arith_en_n <= '0';
- back_oe(wk_x_cmd, '0');
+ back_oe(x_cmd, '0');
set_nzc_from_alu;
elsif instruction = conv_std_logic_vector(16#e4#, dsize) then
a2_zp;
if exec_cycle = T2 then
arith_en_n <= '0';
- back_oe(wk_x_cmd, '0');
+ back_oe(x_cmd, '0');
set_nzc_from_alu;
end if;
a2_abs;
if exec_cycle = T3 then
arith_en_n <= '0';
- back_oe(wk_x_cmd, '0');
+ back_oe(x_cmd, '0');
set_nzc_from_alu;
end if;
d_print("cpy");
fetch_imm;
arith_en_n <= '0';
- back_oe(wk_y_cmd, '0');
+ back_oe(y_cmd, '0');
set_nzc_from_alu;
elsif instruction = conv_std_logic_vector(16#c4#, dsize) then
a2_zp;
if exec_cycle = T2 then
arith_en_n <= '0';
- back_oe(wk_y_cmd, '0');
+ back_oe(y_cmd, '0');
set_nzc_from_alu;
end if;
a2_abs;
if exec_cycle = T3 then
arith_en_n <= '0';
- back_oe(wk_y_cmd, '0');
+ back_oe(y_cmd, '0');
set_nzc_from_alu;
end if;
d_print("eor");
fetch_imm;
arith_en_n <= '0';
- back_oe(wk_acc_cmd, '0');
- back_we(wk_acc_cmd, '0');
+ back_oe(acc_cmd, '0');
+ back_we(acc_cmd, '0');
set_nz_from_alu;
elsif instruction = conv_std_logic_vector(16#45#, dsize) then
a2_zp;
if exec_cycle = T2 then
arith_en_n <= '0';
- back_oe(wk_acc_cmd, '0');
- back_we(wk_acc_cmd, '0');
+ back_oe(acc_cmd, '0');
+ back_we(acc_cmd, '0');
set_nz_from_alu;
end if;
a2_zp_xy(true);
if exec_cycle = T3 then
arith_en_n <= '0';
- back_oe(wk_acc_cmd, '0');
- back_we(wk_acc_cmd, '0');
+ back_oe(acc_cmd, '0');
+ back_we(acc_cmd, '0');
set_nz_from_alu;
end if;
a2_abs;
if exec_cycle = T3 then
arith_en_n <= '0';
- back_oe(wk_acc_cmd, '0');
- back_we(wk_acc_cmd, '0');
+ back_oe(acc_cmd, '0');
+ back_we(acc_cmd, '0');
set_nz_from_alu;
end if;
a2_abs_xy(true);
if exec_cycle = T3 or exec_cycle = T0 then
arith_en_n <= '0';
- back_oe(wk_acc_cmd, '0');
- back_we(wk_acc_cmd, '0');
+ back_oe(acc_cmd, '0');
+ back_we(acc_cmd, '0');
set_nz_from_alu;
end if;
a2_abs_xy(false);
if exec_cycle = T3 or exec_cycle = T0 then
arith_en_n <= '0';
- back_oe(wk_acc_cmd, '0');
- back_we(wk_acc_cmd, '0');
+ back_oe(acc_cmd, '0');
+ back_we(acc_cmd, '0');
set_nz_from_alu;
end if;
a2_indir_x;
if exec_cycle = T5 then
arith_en_n <= '0';
- back_oe(wk_acc_cmd, '0');
- back_we(wk_acc_cmd, '0');
+ back_oe(acc_cmd, '0');
+ back_we(acc_cmd, '0');
set_nz_from_alu;
end if;
a2_indir_y;
if exec_cycle = T4 or exec_cycle = T0 then
arith_en_n <= '0';
- back_oe(wk_acc_cmd, '0');
- back_we(wk_acc_cmd, '0');
+ back_oe(acc_cmd, '0');
+ back_we(acc_cmd, '0');
set_nz_from_alu;
end if;
--imm
d_print("lda");
fetch_imm;
- front_we(wk_acc_cmd, '0');
+ front_we(acc_cmd, '0');
set_nz_from_bus;
elsif instruction = conv_std_logic_vector(16#a5#, dsize) then
d_print("lda");
a2_zp;
if exec_cycle = T2 then
- front_we(wk_acc_cmd, '0');
+ front_we(acc_cmd, '0');
set_nz_from_bus;
end if;
d_print("lda");
a2_zp_xy(true);
if exec_cycle = T3 then
- front_we(wk_acc_cmd, '0');
+ front_we(acc_cmd, '0');
set_nz_from_bus;
end if;
a2_abs;
if exec_cycle = T3 then
set_nz_from_bus;
- front_we(wk_acc_cmd, '0');
+ front_we(acc_cmd, '0');
end if;
elsif instruction = conv_std_logic_vector(16#bd#, dsize) then
a2_abs_xy(true);
if exec_cycle = T3 or exec_cycle = T0 then
--lda.
- front_we(wk_acc_cmd, '0');
+ front_we(acc_cmd, '0');
set_nz_from_bus;
end if;
a2_abs_xy(false);
if exec_cycle = T3 or exec_cycle = T0 then
--lda.
- front_we(wk_acc_cmd, '0');
+ front_we(acc_cmd, '0');
set_nz_from_bus;
end if;
d_print("lda");
a2_indir_x;
if exec_cycle = T5 then
- front_we(wk_acc_cmd, '0');
+ front_we(acc_cmd, '0');
set_nz_from_bus;
end if;
a2_indir_y;
if exec_cycle = T4 or exec_cycle = T0 then
--lda.
- front_we(wk_acc_cmd, '0');
+ front_we(acc_cmd, '0');
set_nz_from_bus;
end if;
d_print("ldx");
fetch_imm;
set_nz_from_bus;
- front_we(wk_x_cmd, '0');
+ front_we(x_cmd, '0');
elsif instruction = conv_std_logic_vector(16#a6#, dsize) then
--zp
d_print("ldx");
a2_zp;
if exec_cycle = T2 then
- front_we(wk_x_cmd, '0');
+ front_we(x_cmd, '0');
set_nz_from_bus;
end if;
d_print("ldx");
a2_zp_xy(false);
if exec_cycle = T3 then
- front_we(wk_x_cmd, '0');
+ front_we(x_cmd, '0');
set_nz_from_bus;
end if;
a2_abs;
if exec_cycle = T3 then
set_nz_from_bus;
- front_we(wk_x_cmd, '0');
+ front_we(x_cmd, '0');
end if;
elsif instruction = conv_std_logic_vector(16#be#, dsize) then
d_print("ldx");
a2_abs_xy(false);
if exec_cycle = T3 or exec_cycle = T0 then
- front_we(wk_x_cmd, '0');
+ front_we(x_cmd, '0');
set_nz_from_bus;
end if;
d_print("ldy");
fetch_imm;
set_nz_from_bus;
- front_we(wk_y_cmd, '0');
+ front_we(y_cmd, '0');
elsif instruction = conv_std_logic_vector(16#a4#, dsize) then
--zp
d_print("ldy");
a2_zp;
if exec_cycle = T2 then
- front_we(wk_y_cmd, '0');
+ front_we(y_cmd, '0');
set_nz_from_bus;
end if;
d_print("ldy");
a2_zp_xy(true);
if exec_cycle = T3 then
- front_we(wk_y_cmd, '0');
+ front_we(y_cmd, '0');
set_nz_from_bus;
end if;
a2_abs;
if exec_cycle = T3 then
set_nz_from_bus;
- front_we(wk_y_cmd, '0');
+ front_we(y_cmd, '0');
end if;
elsif instruction = conv_std_logic_vector(16#bc#, dsize) then
a2_abs_xy(true);
if exec_cycle = T3 or exec_cycle = T0 then
set_nz_from_bus;
- front_we(wk_y_cmd, '0');
+ front_we(y_cmd, '0');
end if;
elsif instruction = conv_std_logic_vector(16#09#, dsize) then
d_print("ora");
fetch_imm;
arith_en_n <= '0';
- back_oe(wk_acc_cmd, '0');
- back_we(wk_acc_cmd, '0');
+ back_oe(acc_cmd, '0');
+ back_we(acc_cmd, '0');
set_nz_from_alu;
elsif instruction = conv_std_logic_vector(16#05#, dsize) then
a2_zp;
if exec_cycle = T2 then
arith_en_n <= '0';
- back_oe(wk_acc_cmd, '0');
- back_we(wk_acc_cmd, '0');
+ back_oe(acc_cmd, '0');
+ back_we(acc_cmd, '0');
set_nz_from_alu;
end if;
a2_zp_xy(true);
if exec_cycle = T3 then
arith_en_n <= '0';
- back_oe(wk_acc_cmd, '0');
- back_we(wk_acc_cmd, '0');
+ back_oe(acc_cmd, '0');
+ back_we(acc_cmd, '0');
set_nz_from_alu;
end if;
a2_abs;
if exec_cycle = T3 then
arith_en_n <= '0';
- back_oe(wk_acc_cmd, '0');
- back_we(wk_acc_cmd, '0');
+ back_oe(acc_cmd, '0');
+ back_we(acc_cmd, '0');
set_nz_from_alu;
end if;
a2_abs_xy(true);
if exec_cycle = T3 or exec_cycle = T0 then
arith_en_n <= '0';
- back_oe(wk_acc_cmd, '0');
- back_we(wk_acc_cmd, '0');
+ back_oe(acc_cmd, '0');
+ back_we(acc_cmd, '0');
set_nz_from_alu;
end if;
a2_abs_xy(false);
if exec_cycle = T3 or exec_cycle = T0 then
arith_en_n <= '0';
- back_oe(wk_acc_cmd, '0');
- back_we(wk_acc_cmd, '0');
+ back_oe(acc_cmd, '0');
+ back_we(acc_cmd, '0');
set_nz_from_alu;
end if;
a2_indir_x;
if exec_cycle = T5 then
arith_en_n <= '0';
- back_oe(wk_acc_cmd, '0');
- back_we(wk_acc_cmd, '0');
+ back_oe(acc_cmd, '0');
+ back_we(acc_cmd, '0');
set_nz_from_alu;
end if;
a2_indir_y;
if exec_cycle = T4 or exec_cycle = T0 then
arith_en_n <= '0';
- back_oe(wk_acc_cmd, '0');
- back_we(wk_acc_cmd, '0');
+ back_oe(acc_cmd, '0');
+ back_we(acc_cmd, '0');
set_nz_from_alu;
end if;
d_print("sbc");
fetch_imm;
arith_en_n <= '0';
- back_oe(wk_acc_cmd, '0');
- back_we(wk_acc_cmd, '0');
+ back_oe(acc_cmd, '0');
+ back_we(acc_cmd, '0');
set_nvzc_from_alu;
elsif instruction = conv_std_logic_vector(16#e5#, dsize) then
a2_zp;
if exec_cycle = T2 then
arith_en_n <= '0';
- back_oe(wk_acc_cmd, '0');
- back_we(wk_acc_cmd, '0');
+ back_oe(acc_cmd, '0');
+ back_we(acc_cmd, '0');
set_nvzc_from_alu;
end if;
a2_zp_xy(true);
if exec_cycle = T3 then
arith_en_n <= '0';
- back_oe(wk_acc_cmd, '0');
- back_we(wk_acc_cmd, '0');
+ back_oe(acc_cmd, '0');
+ back_we(acc_cmd, '0');
set_nvzc_from_alu;
end if;
a2_abs;
if exec_cycle = T3 then
arith_en_n <= '0';
- back_oe(wk_acc_cmd, '0');
- back_we(wk_acc_cmd, '0');
+ back_oe(acc_cmd, '0');
+ back_we(acc_cmd, '0');
set_nvzc_from_alu;
end if;
a2_abs_xy(true);
if exec_cycle = T3 or exec_cycle = T0 then
arith_en_n <= '0';
- back_oe(wk_acc_cmd, '0');
- back_we(wk_acc_cmd, '0');
+ back_oe(acc_cmd, '0');
+ back_we(acc_cmd, '0');
set_nvzc_from_alu;
end if;
a2_abs_xy(false);
if exec_cycle = T3 or exec_cycle = T0 then
arith_en_n <= '0';
- back_oe(wk_acc_cmd, '0');
- back_we(wk_acc_cmd, '0');
+ back_oe(acc_cmd, '0');
+ back_we(acc_cmd, '0');
set_nvzc_from_alu;
end if;
a2_indir_x;
if exec_cycle = T5 then
arith_en_n <= '0';
- back_oe(wk_acc_cmd, '0');
- back_we(wk_acc_cmd, '0');
+ back_oe(acc_cmd, '0');
+ back_we(acc_cmd, '0');
set_nvzc_from_alu;
end if;
a2_indir_y;
if exec_cycle = T4 or exec_cycle = T0 then
arith_en_n <= '0';
- back_oe(wk_acc_cmd, '0');
- back_we(wk_acc_cmd, '0');
+ back_oe(acc_cmd, '0');
+ back_we(acc_cmd, '0');
set_nvzc_from_alu;
end if;
d_print("sta");
a3_zp;
if exec_cycle = T2 then
- front_oe(wk_acc_cmd, '0');
+ front_oe(acc_cmd, '0');
end if;
elsif instruction = conv_std_logic_vector(16#95#, dsize) then
d_print("sta");
a3_zp_xy(true);
if exec_cycle = T2 then
- front_oe(wk_acc_cmd, '0');
+ front_oe(acc_cmd, '0');
end if;
elsif instruction = conv_std_logic_vector(16#8d#, dsize) then
d_print("sta");
a3_abs;
if exec_cycle = T3 then
- front_oe(wk_acc_cmd, '0');
+ front_oe(acc_cmd, '0');
end if;
elsif instruction = conv_std_logic_vector(16#9d#, dsize) then
d_print("sta");
a3_abs_xy (true);
if exec_cycle = T4 then
- front_oe(wk_acc_cmd, '0');
+ front_oe(acc_cmd, '0');
end if;
elsif instruction = conv_std_logic_vector(16#99#, dsize) then
d_print("sta");
a3_abs_xy (false);
if exec_cycle = T4 then
- front_oe(wk_acc_cmd, '0');
+ front_oe(acc_cmd, '0');
end if;
elsif instruction = conv_std_logic_vector(16#81#, dsize) then
d_print("sta");
a3_indir_x;
if exec_cycle = T5 then
- front_oe(wk_acc_cmd, '0');
+ front_oe(acc_cmd, '0');
end if;
elsif instruction = conv_std_logic_vector(16#91#, dsize) then
d_print("sta");
a3_indir_y;
if exec_cycle = T5 then
- front_oe(wk_acc_cmd, '0');
+ front_oe(acc_cmd, '0');
end if;
elsif instruction = conv_std_logic_vector(16#86#, dsize) then
d_print("stx");
a3_zp;
if exec_cycle = T2 then
- front_oe(wk_x_cmd, '0');
+ front_oe(x_cmd, '0');
end if;
elsif instruction = conv_std_logic_vector(16#96#, dsize) then
d_print("stx");
a3_zp_xy(false);
if exec_cycle = T2 then
- front_oe(wk_x_cmd, '0');
+ front_oe(x_cmd, '0');
end if;
elsif instruction = conv_std_logic_vector(16#8e#, dsize) then
d_print("stx");
a3_abs;
if exec_cycle = T3 then
- front_oe(wk_x_cmd, '0');
+ front_oe(x_cmd, '0');
end if;
elsif instruction = conv_std_logic_vector(16#84#, dsize) then
d_print("sty");
a3_zp;
if exec_cycle = T2 then
- front_oe(wk_y_cmd, '0');
+ front_oe(y_cmd, '0');
end if;
elsif instruction = conv_std_logic_vector(16#94#, dsize) then
d_print("sty");
a3_zp_xy(true);
if exec_cycle = T2 then
- front_oe(wk_y_cmd, '0');
+ front_oe(y_cmd, '0');
end if;
elsif instruction = conv_std_logic_vector(16#8c#, dsize) then
d_print("sty");
a3_abs;
if exec_cycle = T3 then
- front_oe(wk_y_cmd, '0');
+ front_oe(y_cmd, '0');
end if;
d_print("pha");
a51_push;
if exec_cycle = T2 then
- front_oe(wk_acc_cmd, '0');
+ front_oe(acc_cmd, '0');
end if;
elsif instruction = conv_std_logic_vector(16#28#, dsize) then
d_print("pla");
a52_pull;
if exec_cycle = T3 then
- front_we(wk_acc_cmd, '0');
+ front_we(acc_cmd, '0');
set_nz_from_bus;
end if;
fetch_next;
dbuf_int_oe_n <= '0';
--latch adl
- dl_al_we_n <= '0';
- wk_next_cycle <= T2;
+ --dl_al_we_n <= '0';
+ next_cycle <= T2;
elsif exec_cycle = T2 then
d_print("jsr 3");
fetch_stop;
dbuf_int_oe_n <= '1';
- dl_al_we_n <= '1';
+ --dl_al_we_n <= '1';
--push return addr high into stack.
sp_push_n <= '0';
back_oe(sp_cmd, '0');
back_we(sp_cmd, '0');
r_nw <= '0';
- wk_next_cycle <= T3;
+ next_cycle <= T3;
elsif exec_cycle = T3 then
d_print("jsr 4");
front_oe(pch_cmd, '1');
back_we(sp_cmd, '0');
r_nw <= '0';
- wk_next_cycle <= T4;
+ next_cycle <= T4;
elsif exec_cycle = T4 then
d_print("jsr 5");
sp_push_n <= '1';
back_oe(pch_cmd, '0');
back_oe(pcl_cmd, '0');
dbuf_int_oe_n <= '0';
- dl_ah_we_n <= '0';
+ --dl_ah_we_n <= '0';
- wk_next_cycle <= T5;
+ next_cycle <= T5;
elsif exec_cycle = T5 then
d_print("jsr 6");
back_oe(pch_cmd, '1');
back_oe(pcl_cmd, '1');
dbuf_int_oe_n <= '1';
- dl_ah_we_n <= '1';
+ --dl_ah_we_n <= '1';
--load/output pch
ad_oe_n <= '1';
- dl_dh_oe_n <= '0';
+ --dl_dh_oe_n <= '0';
front_we(pch_cmd, '0');
--load pcl.
- dl_al_oe_n <= '0';
+ --dl_al_oe_n <= '0';
back_we(pcl_cmd, '0');
- wk_next_cycle <= T0;
+ next_cycle <= T0;
end if; --if exec_cycle = T1 then
-- A.5.4 break
sp_pop_n <= '0';
sp_oe_n <= '0';
- wk_next_cycle <= T2;
+ next_cycle <= T2;
elsif exec_cycle = T2 then
d_print("rti 3");
dbuf_int_oe_n <= '0';
stat_bus_all_n <= '0';
- wk_next_cycle <= T3;
+ next_cycle <= T3;
elsif exec_cycle = T3 then
d_print("rti 4");
stat_bus_all_n <= '1';
dbuf_int_oe_n <= '0';
front_we(pcl_cmd, '0');
- wk_next_cycle <= T4;
+ next_cycle <= T4;
elsif exec_cycle = T4 then
d_print("rti 5");
--stack decrement stop.
dbuf_int_oe_n <= '0';
front_we(pch_cmd, '0');
- wk_next_cycle <= T5;
+ next_cycle <= T5;
elsif exec_cycle = T5 then
d_print("rti 6");
back_oe(sp_cmd, '1');
front_we(pch_cmd, '1');
--increment pc.
- wk_next_cycle <= T0;
+ next_cycle <= T0;
end if; --if exec_cycle = T1 then
----------------------------------------
--latch abs low data.
dbuf_int_oe_n <= '0';
- dl_al_we_n <= '0';
- wk_next_cycle <= T2;
+ --dl_al_we_n <= '0';
+ next_cycle <= T2;
elsif exec_cycle = T2 then
d_print("jmp 3");
- dl_al_we_n <= '1';
+ --dl_al_we_n <= '1';
--fetch abs hi
fetch_next;
--latch in dlh
dbuf_int_oe_n <= '0';
- dl_ah_we_n <= '0';
+ --dl_ah_we_n <= '0';
---load pch.
front_we(pch_cmd, '0');
- wk_next_cycle <= T0;
+ next_cycle <= T0;
end if;
elsif instruction = conv_std_logic_vector(16#6c#, dsize) then
--latch abs low data.
dbuf_int_oe_n <= '0';
- dl_al_we_n <= '0';
- wk_next_cycle <= T2;
+ --dl_al_we_n <= '0';
+ next_cycle <= T2;
elsif exec_cycle = T2 then
d_print("jmp 3");
- dl_al_we_n <= '1';
+ --dl_al_we_n <= '1';
--fetch abs hi
fetch_next;
--latch in dlh
dbuf_int_oe_n <= '0';
- dl_ah_we_n <= '0';
- wk_next_cycle <= T3;
+ --dl_ah_we_n <= '0';
+ next_cycle <= T3;
elsif exec_cycle = T3 then
fetch_stop;
- dl_ah_we_n <= '1';
+ --dl_ah_we_n <= '1';
--IAH/IAL > ADL
- dl_ah_oe_n <= '0';
- dl_al_oe_n <= '0';
+ --dl_ah_oe_n <= '0';
+ --dl_al_oe_n <= '0';
front_we(pcl_cmd, '0');
- wk_next_cycle <= T4;
+ next_cycle <= T4;
elsif exec_cycle = T4 then
- dl_ah_oe_n <= '0';
- dl_al_oe_n <= '0';
+ --dl_ah_oe_n <= '0';
+ --dl_al_oe_n <= '0';
front_we(pcl_cmd, '1');
--IAH/IAL+1 > ADH
front_we(pch_cmd, '0');
indir_n <= '0';
- wk_next_cycle <= T0;
+ next_cycle <= T0;
end if;
sp_pop_n <= '0';
sp_oe_n <= '0';
- wk_next_cycle <= T2;
+ next_cycle <= T2;
elsif exec_cycle = T2 then
d_print("rts 3");
dbuf_int_oe_n <= '0';
front_we(pcl_cmd, '0');
- wk_next_cycle <= T3;
+ next_cycle <= T3;
elsif exec_cycle = T3 then
d_print("rts 4");
--stack decrement stop.
dbuf_int_oe_n <= '0';
front_we(pch_cmd, '0');
- wk_next_cycle <= T4;
+ next_cycle <= T4;
elsif exec_cycle = T4 then
d_print("rts 5");
back_oe(sp_cmd, '1');
front_we(pch_cmd, '1');
--empty cycle.
--complying h/w manual...
- wk_next_cycle <= T5;
+ next_cycle <= T5;
elsif exec_cycle = T5 then
d_print("rts 6");
--increment pc.
fetch_next;
- wk_next_cycle <= T0;
+ next_cycle <= T0;
end if; --if exec_cycle = T1 then
----------------------------------------
inst_we_n <= '1';
ad_oe_n <= '1';
dbuf_int_oe_n <= '1';
- dl_al_we_n <= '1';
- dl_ah_we_n <= '1';
- dl_al_oe_n <= '1';
- dl_ah_oe_n <= '1';
- dl_dh_oe_n <= '1';
+ --dl_al_we_n <= '1';
+ --dl_ah_we_n <= '1';
+ --dl_al_oe_n <= '1';
+ --dl_ah_oe_n <= '1';
+ --dl_dh_oe_n <= '1';
pcl_inc_n <= '1';
pcl_cmd <= "1111";
pch_cmd <= "1111";
sp_oe_n <= '1';
sp_push_n <= '1';
sp_pop_n <= '1';
- wk_acc_cmd <= "1111";
- wk_x_cmd <= "1111";
- wk_y_cmd <= "1111";
+ acc_cmd <= "1111";
+ x_cmd <= "1111";
+ y_cmd <= "1111";
abs_xy_n <= '1';
pg_next_n <= '1';
stat_flg <= '1';
stat_bus_all_n <= '1';
stat_bus_nz_n <= '1';
- wk_stat_alu_we_n <= '1';
+ stat_alu_we_n <= '1';
r_vec_oe_n <= '1';
n_vec_oe_n <= '1';
nmi_handled_n <= '1';
r_nw <= '1';
- wk_next_cycle <= R1;
+ next_cycle <= R1;
elsif exec_cycle = R1 or exec_cycle = N1 then
pcl_cmd <= "1111";
pcl_inc_n <= '1';
inst_we_n <= '1';
- dl_al_oe_n <= '1';
+ --dl_al_oe_n <= '1';
--push pch.
d_print("R1");
r_nw <= '0';
if exec_cycle = R1 then
- wk_next_cycle <= R2;
+ next_cycle <= R2;
elsif exec_cycle = N1 then
- wk_next_cycle <= N2;
+ next_cycle <= N2;
end if;
elsif exec_cycle = R2 or exec_cycle = N2 then
r_nw <= '0';
if exec_cycle = R2 then
- wk_next_cycle <= R3;
+ next_cycle <= R3;
elsif exec_cycle = N2 then
- wk_next_cycle <= N3;
+ next_cycle <= N3;
end if;
elsif exec_cycle = R3 or exec_cycle = N3 then
r_nw <= '0';
if exec_cycle = R3 then
- wk_next_cycle <= R4;
+ next_cycle <= R4;
elsif exec_cycle = N3 then
- wk_next_cycle <= N4;
+ next_cycle <= N4;
end if;
elsif exec_cycle = R4 or exec_cycle = N4 then
r_nw <= '1';
dbuf_int_oe_n <= '0';
front_we(pcl_cmd, '0');
- dl_al_oe_n <= '1';
- dl_ah_oe_n <= '1';
+ --dl_al_oe_n <= '1';
+ --dl_ah_oe_n <= '1';
if exec_cycle = R4 then
r_vec_oe_n <= '0';
n_vec_oe_n <= '1';
- wk_next_cycle <= R5;
+ next_cycle <= R5;
elsif exec_cycle = N4 then
r_vec_oe_n <= '1';
n_vec_oe_n <= '0';
- wk_next_cycle <= N5;
+ next_cycle <= N5;
end if;
elsif exec_cycle = R5 or exec_cycle = N5 then
nmi_handled_n <= '0';
end if;
--start execute cycle.
- wk_next_cycle <= T0;
+ next_cycle <= T0;
end if; --if rdy = '0' then
----------------------------------------------
component decoder
generic (dsize : integer := 8);
- port ( \r
- --signal dbg_ea_carry : out std_logic;\r
-\r
+ port (\r
+ --input lines.\r
set_clk : in std_logic;
trig_clk : in std_logic;
res_n : in std_logic;
instruction : in std_logic_vector (dsize - 1 downto 0);
exec_cycle : in std_logic_vector (5 downto 0);
next_cycle : out std_logic_vector (5 downto 0);
+ ea_carry : in std_logic;\r
status_reg : inout std_logic_vector (dsize - 1 downto 0);
+\r
+ --general control.\r
inst_we_n : out std_logic;
ad_oe_n : out std_logic;
dbuf_int_oe_n : out std_logic;
- dl_al_we_n : out std_logic;
- dl_ah_we_n : out std_logic;
- dl_al_oe_n : out std_logic;
- dl_ah_oe_n : out std_logic;
- dl_dh_oe_n : out std_logic;
+ r_nw : out std_logic;\r
+\r
+ ----control line for dual port registers.\r
+ idl_l_cmd : out std_logic_vector(3 downto 0);\r
+ idl_h_cmd : out std_logic_vector(3 downto 0);\r
+ pcl_cmd : out std_logic_vector(3 downto 0);\r
+ pch_cmd : out std_logic_vector(3 downto 0);\r
+ sp_cmd : out std_logic_vector(3 downto 0);\r
+ x_cmd : out std_logic_vector(3 downto 0);\r
+ y_cmd : out std_logic_vector(3 downto 0);\r
+ acc_cmd : out std_logic_vector(3 downto 0);\r
+ \r
+ --addr calc control\r
pcl_inc_n : out std_logic;
- pcl_cmd : out std_logic_vector(3 downto 0);
- pch_cmd : out std_logic_vector(3 downto 0);
- sp_cmd : out std_logic_vector(3 downto 0);
sp_oe_n : out std_logic;
sp_push_n : out std_logic;
sp_pop_n : out std_logic;
- acc_cmd : out std_logic_vector(3 downto 0);
- x_cmd : out std_logic_vector(3 downto 0);
- y_cmd : out std_logic_vector(3 downto 0);
abs_xy_n : out std_logic;
- ea_carry : in std_logic;
pg_next_n : out std_logic;
zp_n : out std_logic;
zp_xy_n : out std_logic;
indir_n : out std_logic;
indir_x_n : out std_logic;
indir_y_n : out std_logic;
- arith_en_n : out std_logic;
+\r
+ ---status register\r
stat_dec_oe_n : out std_logic;
stat_bus_oe_n : out std_logic;
stat_set_flg_n : out std_logic;
stat_flg : out std_logic;
stat_bus_all_n : out std_logic;
stat_bus_nz_n : out std_logic;
- stat_alu_we_n : out std_logic;
+ stat_alu_we_n : out std_logic;\r
+ \r
+ --ALU control\r
+ arith_en_n : out std_logic;\r
+ \r
+ --reset vectors.
r_vec_oe_n : out std_logic;
n_vec_oe_n : out std_logic;
- i_vec_oe_n : out std_logic;
- r_nw : out std_logic
+ i_vec_oe_n : out std_logic\r
+\r
;---for parameter check purpose!!!
check_bit : out std_logic_vector(1 to 5)
);
end component;
+\r
+component address_calcurator\r
+ generic ( dsize : integer := 8\r
+ );\r
+ port ( \r
+ set_clk : in std_logic;\r
+ trig_clk : in std_logic;\r
+\r
+ --instruction reg\r
+ instruction : in std_logic_vector (dsize - 1 downto 0);\r
+ exec_cycle : in std_logic_vector (5 downto 0);\r
+\r
+ --control line.\r
+ pcl_inc_n : in std_logic;\r
+ sp_oe_n : in std_logic;\r
+ sp_push_n : in std_logic;\r
+ sp_pop_n : in std_logic;\r
+ abs_xy_n : in std_logic;\r
+ pg_next_n : in std_logic;\r
+ zp_n : in std_logic;\r
+ zp_xy_n : in std_logic;\r
+ rel_calc_n : in std_logic;\r
+ indir_n : in std_logic;\r
+ indir_x_n : in std_logic;\r
+ indir_y_n : in std_logic;\r
+\r
+ --in/out buses.\r
+ index_bus : in std_logic_vector (dsize - 1 downto 0);\r
+ bal : in std_logic_vector (dsize - 1 downto 0);\r
+ bah : in std_logic_vector (dsize - 1 downto 0);\r
+ int_d_bus : inout std_logic_vector (dsize - 1 downto 0);\r
+ addr_back_l : out std_logic_vector (dsize - 1 downto 0);\r
+ addr_back_h : out std_logic_vector (dsize - 1 downto 0);\r
+ abl : out std_logic_vector (dsize - 1 downto 0);\r
+ abh : out std_logic_vector (dsize - 1 downto 0);\r
+ ea_carry : out std_logic\r
+ );\r
+end component;\r
component alu
generic ( dsize : integer := 8
port ( \r
set_clk : in std_logic;\r
trig_clk : in std_logic;\r
- pcl_inc_n : in std_logic;
- sp_oe_n : in std_logic;
- sp_push_n : in std_logic;
- sp_pop_n : in std_logic;
- abs_xy_n : in std_logic;
- pg_next_n : in std_logic;
- zp_n : in std_logic;
- zp_xy_n : in std_logic;
- rel_calc_n : in std_logic;
- indir_n : in std_logic;
- indir_x_n : in std_logic;
- indir_y_n : in std_logic;
+ instruction : in std_logic_vector (dsize - 1 downto 0);\r
+ exec_cycle : in std_logic_vector (5 downto 0);\r
arith_en_n : in std_logic;
- instruction : in std_logic_vector (dsize - 1 downto 0);
- exec_cycle : in std_logic_vector (5 downto 0);
- int_d_bus : inout std_logic_vector (dsize - 1 downto 0);
+ int_d_bus : inout std_logic_vector (dsize - 1 downto 0);\r
+ acc_in : out std_logic_vector (dsize - 1 downto 0);\r
acc_out : in std_logic_vector (dsize - 1 downto 0);
- index_bus : in std_logic_vector (dsize - 1 downto 0);
- bal : in std_logic_vector (dsize - 1 downto 0);
- bah : in std_logic_vector (dsize - 1 downto 0);
- addr_back : out std_logic_vector (dsize - 1 downto 0);
- acc_in : out std_logic_vector (dsize - 1 downto 0);
- abl : out std_logic_vector (dsize - 1 downto 0);
- abh : out std_logic_vector (dsize - 1 downto 0);
- ea_carry : out std_logic;
+ index_bus : in std_logic_vector (dsize - 1 downto 0);\r
carry_in : in std_logic;
negative : out std_logic;
zero : out std_logic;
);
end component;
-component input_data_latch
- generic (
- dsize : integer := 8
- );
- port ( \r
- signal dbg_idl_val : out std_logic_vector (7 downto 0);\r
- \r
-
- clk : in std_logic;
- oe_n : in std_logic;
- we_n : in std_logic;
- int_dbus : in std_logic_vector (dsize - 1 downto 0);
- alu_bus : out std_logic_vector (dsize - 1 downto 0)
- );
-end component;
-
component tri_state_buffer
generic (
dsize : integer := 8
----------------------------------------------
------------ signal declareration ------------
----------------------------------------------
- signal set_clk : std_logic;
- signal trigger_clk : std_logic;
+ signal set_clk : std_logic;
+ signal trig_clk : std_logic;
signal exec_cycle : std_logic_vector(5 downto 0);
signal next_cycle : std_logic_vector(5 downto 0);
-------------------------------
-------- control lines --------
-------------------------------
- signal inst_we_n : std_logic;
- signal inst_rst_n : std_logic;
- signal ad_oe_n : std_logic;
-
- signal dbuf_r_nw : std_logic;
- signal dbuf_int_oe_n : std_logic;
-
- signal dl_al_we_n : std_logic;
- signal dl_ah_we_n : std_logic;
- signal dl_al_oe_n : std_logic;
- signal dl_ah_oe_n : std_logic;
- signal dl_dh_oe_n : std_logic;
-
- signal pcl_inc_n : std_logic;
- signal abs_xy_n : std_logic;
- signal ea_carry : std_logic;
- signal pg_next_n : std_logic;
- signal zp_n : std_logic;
- signal zp_xy_n : std_logic;
- signal rel_calc_n : std_logic;
- signal indir_n : std_logic;
- signal indir_x_n : std_logic;
- signal indir_y_n : std_logic;
- signal arith_en_n : std_logic;
-
- signal alu_n : std_logic;
- signal alu_z : std_logic;
- signal alu_c : std_logic;
- signal alu_v : std_logic;
- signal stat_c : std_logic;
+ signal inst_we_n : std_logic;
+ signal inst_rst_n : std_logic;
+ signal ad_oe_n : std_logic;
+
+ signal dbuf_r_nw : std_logic;
+ signal dbuf_int_oe_n : std_logic;
+
+ signal pcl_inc_n : std_logic;
+ signal abs_xy_n : std_logic;
+ signal ea_carry : std_logic;
+ signal pg_next_n : std_logic;
+ signal zp_n : std_logic;
+ signal zp_xy_n : std_logic;
+ signal rel_calc_n : std_logic;
+ signal indir_n : std_logic;
+ signal indir_x_n : std_logic;
+ signal indir_y_n : std_logic;
+ signal sp_oe_n : std_logic;\r
+ signal sp_push_n : std_logic;\r
+ signal sp_pop_n : std_logic;\r
+\r
+ signal arith_en_n : std_logic;
+ signal stat_c : std_logic;
+\r
+ signal negative : std_logic;\r
+ signal zero : std_logic;\r
+ signal carry_out : std_logic;\r
+ signal overflow : std_logic;\r
----control line for dual port registers.
- signal pcl_cmd : std_logic_vector(3 downto 0);
- signal pch_cmd : std_logic_vector(3 downto 0);
- signal sp_cmd : std_logic_vector(3 downto 0);
- signal acc_cmd : std_logic_vector(3 downto 0);
- signal x_cmd : std_logic_vector(3 downto 0);
- signal y_cmd : std_logic_vector(3 downto 0);
- signal sp_oe_n : std_logic;
- signal sp_push_n : std_logic;
- signal sp_pop_n : std_logic;
+ signal idl_l_cmd : std_logic_vector(3 downto 0);\r
+ signal idl_h_cmd : std_logic_vector(3 downto 0);\r
+ signal pcl_cmd : std_logic_vector(3 downto 0);
+ signal pch_cmd : std_logic_vector(3 downto 0);
+ signal sp_cmd : std_logic_vector(3 downto 0);
+ signal acc_cmd : std_logic_vector(3 downto 0);
+ signal x_cmd : std_logic_vector(3 downto 0);
+ signal y_cmd : std_logic_vector(3 downto 0);
---status register
- signal stat_dec_oe_n : std_logic;
- signal stat_bus_oe_n : std_logic;
- signal stat_set_flg_n : std_logic;
- signal stat_flg : std_logic;
- signal stat_bus_all_n : std_logic;
- signal stat_bus_nz_n : std_logic;
- signal stat_alu_we_n : std_logic;
+ signal stat_dec_oe_n : std_logic;
+ signal stat_bus_oe_n : std_logic;
+ signal stat_set_flg_n : std_logic;
+ signal stat_flg : std_logic;
+ signal stat_bus_all_n : std_logic;
+ signal stat_bus_nz_n : std_logic;
+ signal stat_alu_we_n : std_logic;
-------------------------------
------------ buses ------------
-------------------------------
- signal instruction : std_logic_vector(dsize - 1 downto 0);
+ signal instruction : std_logic_vector(dsize - 1 downto 0);
- signal bah : std_logic_vector(dsize - 1 downto 0);
- signal bal : std_logic_vector(dsize - 1 downto 0);
- signal index_bus : std_logic_vector(dsize - 1 downto 0);
- signal idl_h_out : std_logic_vector(dsize - 1 downto 0);
+ signal bah : std_logic_vector(dsize - 1 downto 0);
+ signal bal : std_logic_vector(dsize - 1 downto 0);
+ signal index_bus : std_logic_vector(dsize - 1 downto 0);
- signal acc_out : std_logic_vector(dsize - 1 downto 0);
- signal acc_in : std_logic_vector(dsize - 1 downto 0);
- signal addr_back : std_logic_vector(dsize - 1 downto 0);
+ signal acc_out : std_logic_vector(dsize - 1 downto 0);
+ signal acc_in : std_logic_vector(dsize - 1 downto 0);
+ signal addr_back_l : std_logic_vector(dsize - 1 downto 0);\r
+ signal addr_back_h : std_logic_vector(dsize - 1 downto 0);\r
--not used bus.
- signal null_bus : std_logic_vector(dsize - 1 downto 0);
+ signal null_bus : std_logic_vector(dsize - 1 downto 0);
--address bus
- signal abh : std_logic_vector(dsize - 1 downto 0);
- signal abl : std_logic_vector(dsize - 1 downto 0);
+ signal abh : std_logic_vector(dsize - 1 downto 0);
+ signal abl : std_logic_vector(dsize - 1 downto 0);
---internal data bus
- signal int_d_bus : std_logic_vector(dsize - 1 downto 0);
+ signal int_d_bus : std_logic_vector(dsize - 1 downto 0);
---reset vectors---
- signal r_vec_oe_n : std_logic;
- signal n_vec_oe_n : std_logic;
- signal i_vec_oe_n : std_logic;
- signal reset_l : std_logic_vector(dsize - 1 downto 0);
- signal reset_h : std_logic_vector(dsize - 1 downto 0);
- signal nmi_l : std_logic_vector(dsize - 1 downto 0);
- signal nmi_h : std_logic_vector(dsize - 1 downto 0);
- signal irq_l : std_logic_vector(dsize - 1 downto 0);
- signal irq_h : std_logic_vector(dsize - 1 downto 0);
-
- signal check_bit : std_logic_vector(1 to 5);
+ signal r_vec_oe_n : std_logic;
+ signal n_vec_oe_n : std_logic;
+ signal i_vec_oe_n : std_logic;
+ signal reset_l : std_logic_vector(dsize - 1 downto 0);
+ signal reset_h : std_logic_vector(dsize - 1 downto 0);
+ signal nmi_l : std_logic_vector(dsize - 1 downto 0);
+ signal nmi_h : std_logic_vector(dsize - 1 downto 0);
+ signal irq_l : std_logic_vector(dsize - 1 downto 0);
+ signal irq_h : std_logic_vector(dsize - 1 downto 0);
+
+ signal check_bit : std_logic_vector(1 to 5);
\r
begin
\r
phi1 <= input_clk;
phi2 <= not input_clk;
set_clk <= input_clk;
- trigger_clk <= not input_clk;
+ trig_clk <= not input_clk;
r_nw <= dbuf_r_nw;
reset_l <= "11111100";
dec_inst : decoder generic map (dsize)
port map(\r
- --dbg_ea_carry ,\r
- \r
- set_clk,
- trigger_clk,
- rst_n,
- irq_n,
- nmi_n,
- rdy,
- instruction,
- exec_cycle,
- next_cycle,
- status_reg,
- inst_we_n,
- ad_oe_n,
- dbuf_int_oe_n,
- dl_al_we_n,
- dl_ah_we_n,
- dl_al_oe_n,
- dl_ah_oe_n,
- dl_dh_oe_n,
- pcl_inc_n,
- pcl_cmd,
- pch_cmd,
- sp_cmd,
- sp_oe_n,
- sp_push_n,
- sp_pop_n,
- acc_cmd,
- x_cmd,
- y_cmd,
- abs_xy_n,
- ea_carry,
- pg_next_n,
- zp_n,
- zp_xy_n,
- rel_calc_n,
- indir_n,
- indir_x_n,
- indir_y_n,
- arith_en_n,
- stat_dec_oe_n,
- stat_bus_oe_n,
- stat_set_flg_n,
- stat_flg,
- stat_bus_all_n,
- stat_bus_nz_n,
- stat_alu_we_n,
- r_vec_oe_n,
- n_vec_oe_n,
- i_vec_oe_n,
- dbuf_r_nw
+ --input lines.\r
+ set_clk ,\r
+ trig_clk ,\r
+ rst_n ,\r
+ irq_n ,\r
+ nmi_n ,\r
+ rdy ,\r
+ instruction ,\r
+ exec_cycle ,\r
+ next_cycle ,\r
+ ea_carry ,\r
+ status_reg ,\r
+\r
+ inst_we_n ,\r
+ ad_oe_n ,\r
+ dbuf_int_oe_n ,\r
+ dbuf_r_nw ,\r
+\r
+ idl_l_cmd ,\r
+ idl_h_cmd ,\r
+ pcl_cmd ,\r
+ pch_cmd ,\r
+ sp_cmd ,\r
+ x_cmd ,\r
+ y_cmd ,\r
+ acc_cmd ,\r
+\r
+ pcl_inc_n ,\r
+ sp_oe_n ,\r
+ sp_push_n ,\r
+ sp_pop_n ,\r
+ abs_xy_n ,\r
+ pg_next_n ,\r
+ zp_n ,\r
+ zp_xy_n ,\r
+ rel_calc_n ,\r
+ indir_n ,\r
+ indir_x_n ,\r
+ indir_y_n ,\r
+\r
+ stat_dec_oe_n ,\r
+ stat_bus_oe_n ,\r
+ stat_set_flg_n ,\r
+ stat_flg ,\r
+ stat_bus_all_n ,\r
+ stat_bus_nz_n ,\r
+ stat_alu_we_n ,\r
+\r
+ arith_en_n ,\r
+\r
+ r_vec_oe_n ,\r
+ n_vec_oe_n ,\r
+ i_vec_oe_n\r
+\r
, check_bit --check bit.
);
-
+\r
+ ad_calc_inst : address_calcurator generic map (dsize) \r
+ port map (\r
+ set_clk ,\r
+ trig_clk ,\r
+\r
+ instruction ,\r
+ exec_cycle ,\r
+\r
+ pcl_inc_n ,\r
+ sp_oe_n ,\r
+ sp_push_n ,\r
+ sp_pop_n ,\r
+ abs_xy_n ,\r
+ pg_next_n ,\r
+ zp_n ,\r
+ zp_xy_n ,\r
+ rel_calc_n ,\r
+ indir_n ,\r
+ indir_x_n ,\r
+ indir_y_n ,\r
+\r
+ index_bus ,\r
+ bal ,\r
+ bah ,\r
+ int_d_bus ,\r
+ addr_back_l ,\r
+ addr_back_h ,\r
+ abl ,\r
+ abh ,\r
+ ea_carry\r
+ );\r
+
alu_inst : alu generic map (dsize)
port map (\r
- set_clk, \r
- trigger_clk, \r
- pcl_inc_n,
- sp_oe_n,
- sp_push_n,
- sp_pop_n,
- abs_xy_n,
- pg_next_n,
- zp_n,
- zp_xy_n,
- rel_calc_n,
- indir_n,
- indir_x_n,
- indir_y_n,\r
- arith_en_n,
- instruction,
- exec_cycle,
- int_d_bus,
- acc_out,
- index_bus,
- bal,
- bah,
- addr_back,
- acc_in,
- abl,
- abh,
- ea_carry,
- stat_c,
- alu_n,
- alu_z,
- alu_c,
- alu_v
+ set_clk ,\r
+ trig_clk ,\r
+ instruction ,\r
+ exec_cycle ,\r
+ arith_en_n ,\r
+ int_d_bus ,\r
+ acc_in ,\r
+ acc_out ,\r
+ index_bus ,\r
+ stat_c ,\r
+ negative ,\r
+ zero ,\r
+ carry_out ,\r
+ overflow
);
--cpu execution cycle number
exec_cycle_inst : d_flip_flop generic map (5)
- port map(trigger_clk, '1', '1', '0',
+ port map(trig_clk, '1', '1', '0',
next_cycle(4 downto 0), exec_cycle(4 downto 0));
- --io data buffer
+ --io data gateway
dbus_buf : data_bus_buffer generic map (dsize)
port map(dbuf_int_oe_n, dbuf_r_nw, int_d_bus, d_io);
+\r
+ -------- instruction register --------\r
+ ir : d_flip_flop generic map (dsize) \r
+ port map(trig_clk, inst_rst_n, '1', inst_we_n, d_io, instruction);\r
- --address operand data buffer.
- idl_l : input_data_latch generic map (dsize)
- port map(dbg_idl_l, trigger_clk, dl_al_oe_n, dl_al_we_n, int_d_bus, bal);
- idl_h : input_data_latch generic map (dsize)
- port map(dbg_idl_h, trigger_clk, '0', dl_ah_we_n, int_d_bus, idl_h_out);
- ---only DLH has b-bus side output.
- idl_h_a_buf : tri_state_buffer generic map (dsize)
- port map (dl_ah_oe_n, idl_h_out, bah);
- idl_h_d_buf : tri_state_buffer generic map (dsize)
- port map (dl_dh_oe_n, idl_h_out, int_d_bus);
-
- -------- registers --------
- ir : d_flip_flop generic map (dsize)
- port map(trigger_clk, inst_rst_n, '1', inst_we_n, d_io, instruction);
+ --input data buffer.
+ idl_l : dual_dff generic map (dsize)
+ port map(dbg_idl_l, trig_clk, rst_n, '1', idl_l_cmd, int_d_bus, null_bus, bal);
+ idl_h : dual_dff generic map (dsize)
+ port map(dbg_idl_h, trig_clk, rst_n, '1', idl_h_cmd, int_d_bus, null_bus, bah);
+ -------- program counter --------\r
pcl_inst : dual_dff generic map (dsize)
- port map(dbg_pcl, set_clk, rst_n, '1', pcl_cmd, int_d_bus, addr_back, bal);
+ port map(dbg_pcl, set_clk, rst_n, '1', pcl_cmd, int_d_bus, addr_back_l, bal);
pch_inst : dual_dff generic map (dsize)
- port map(dbg_pch, set_clk, rst_n, '1', pch_cmd, int_d_bus, addr_back, bah);
+ port map(dbg_pch, set_clk, rst_n, '1', pch_cmd, int_d_bus, addr_back_h, bah);
+\r
+ --addressing register\r
+ sp : dual_dff generic map (dsize) \r
+ port map(dbg_sp, set_clk, rst_n, '1', sp_cmd, int_d_bus, addr_back_l, bal);\r
+\r
+ x : dual_dff generic map (dsize) \r
+ port map(dbg_x, trig_clk, rst_n, '1', x_cmd, int_d_bus, null_bus, index_bus);\r
+ y : dual_dff generic map (dsize) \r
+ port map(dbg_y, trig_clk, rst_n, '1', y_cmd, int_d_bus, null_bus, index_bus);\r
+\r
+ --accumurator\r
+ acc : dual_dff generic map (dsize) \r
+ port map(dbg_acc, trig_clk, rst_n, '1', acc_cmd, int_d_bus, acc_in, acc_out);\r
+\r
+\r
--status register
status_register : processor_status generic map (dsize)
port map (\r
dbg_int_dbus,\r
-- dbg_status_val,\r
dbg_stat_we_n ,\r
- trigger_clk, rst_n,
+ trig_clk, rst_n,
stat_dec_oe_n, stat_bus_oe_n,
stat_set_flg_n, stat_flg, stat_bus_all_n, stat_bus_nz_n,
- stat_alu_we_n, alu_n, alu_v, alu_z, alu_c, stat_c,
+ stat_alu_we_n, negative, overflow, zero, carry_out, stat_c,
status_reg, int_d_bus);
-
- sp : dual_dff generic map (dsize)
- port map(dbg_sp, set_clk, rst_n, '1', sp_cmd, int_d_bus, addr_back, bal);
-
- x : dual_dff generic map (dsize)
- port map(dbg_x, trigger_clk, rst_n, '1', x_cmd, int_d_bus, null_bus, index_bus);
- y : dual_dff generic map (dsize)
- port map(dbg_y, trigger_clk, rst_n, '1', y_cmd, int_d_bus, null_bus, index_bus);
-
- acc : dual_dff generic map (dsize)
- port map(dbg_acc, trigger_clk, rst_n, '1', acc_cmd, int_d_bus, acc_in, acc_out);
-
--adh output is controlled by decoder.
adh_buf : tri_state_buffer generic map (dsize)
port map (ad_oe_n, abh, addr(asize - 1 downto dsize));
irq_h_buf : tri_state_buffer generic map (dsize)
port map (i_vec_oe_n, irq_h, bah);\r
\r
- reset_p : process (rst_n)
- begin
- if (rst_n = '0') then
-
- end if;
- end process;
-
-
------------------------------------------------------------
------------------------ for debug... ----------------------
------------------------------------------------------------
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