ARM64: fix a couple of signed/unsigned comparison warnings.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205174 91177308-0d34-0410-b5e6-96231b3b80d8

diff --git a/lib/Target/ARM64/ARM64FrameLowering.cpp b/lib/Target/ARM64/ARM64FrameLowering.cpp
index 7910085..0664bb3 100644 (file)
--- a/lib/Target/ARM64/ARM64FrameLowering.cpp
+++ b/lib/Target/ARM64/ARM64FrameLowering.cpp
@@ -422,7 +422,7 @@ void ARM64FrameLowering::emitEpilogue(MachineFunction &MF,
       static_cast<const ARM64RegisterInfo *>(MF.getTarget().getRegisterInfo());
   DebugLoc DL = MBBI->getDebugLoc();
 
-  unsigned NumBytes = MFI->getStackSize();
+  int NumBytes = MFI->getStackSize();
   unsigned NumRestores = 0;
   // Move past the restores of the callee-saved registers.
   MachineBasicBlock::iterator LastPopI = MBBI;

diff --git a/lib/Target/ARM64/ARM64ISelDAGToDAG.cpp b/lib/Target/ARM64/ARM64ISelDAGToDAG.cpp
index 4169043..a3a83e1 100644 (file)
--- a/lib/Target/ARM64/ARM64ISelDAGToDAG.cpp
+++ b/lib/Target/ARM64/ARM64ISelDAGToDAG.cpp
@@ -1308,8 +1308,7 @@ static bool isBitfieldExtractOpFromShr(SDNode *N, unsigned &Opc, SDValue &Opd0,
   } else
     return false;
 
-  assert(Shl_imm >= 0 && Shl_imm < VT.getSizeInBits() &&
-         "bad amount in shift node!");
+  assert(Shl_imm < VT.getSizeInBits() && "bad amount in shift node!");
   uint64_t Srl_imm = 0;
   if (!isIntImmediate(N->getOperand(1), Srl_imm))
     return false;