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RDMA/hns: Delete redundant abnormal interrupt status
authorWenpeng Liang <liangwenpeng@huawei.com>
Fri, 2 Apr 2021 09:07:29 +0000 (17:07 +0800)
committerJason Gunthorpe <jgg@nvidia.com>
Thu, 8 Apr 2021 19:08:21 +0000 (16:08 -0300)
The hardware supports only two types of abnormal interrupts.

Fixes: a5073d6054f7 ("RDMA/hns: Add eq support of hip08")
Link: https://lore.kernel.org/r/1617354454-47840-5-git-send-email-liweihang@huawei.com
Signed-off-by: Wenpeng Liang <liangwenpeng@huawei.com>
Signed-off-by: Weihang Li <liweihang@huawei.com>
Signed-off-by: Jason Gunthorpe <jgg@nvidia.com>
drivers/infiniband/hw/hns/hns_roce_hw_v2.c
drivers/infiniband/hw/hns/hns_roce_hw_v2.h

index e222bf3..4649ed0 100644 (file)
@@ -6036,28 +6036,19 @@ static irqreturn_t hns_roce_v2_msix_interrupt_abn(int irq, void *dev_id)
                roce_write(hr_dev, ROCEE_VF_ABN_INT_EN_REG, int_en);
 
                int_work = 1;
-       } else if (int_st & BIT(HNS_ROCE_V2_VF_INT_ST_BUS_ERR_S)) {
-               dev_err(dev, "BUS ERR!\n");
+       } else if (int_st & BIT(HNS_ROCE_V2_VF_INT_ST_RAS_INT_S)) {
+               dev_err(dev, "RAS interrupt!\n");
 
-               int_st |= 1 << HNS_ROCE_V2_VF_INT_ST_BUS_ERR_S;
+               int_st |= 1 << HNS_ROCE_V2_VF_INT_ST_RAS_INT_S;
                roce_write(hr_dev, ROCEE_VF_ABN_INT_ST_REG, int_st);
 
                int_en |= 1 << HNS_ROCE_V2_VF_ABN_INT_EN_S;
                roce_write(hr_dev, ROCEE_VF_ABN_INT_EN_REG, int_en);
 
                int_work = 1;
-       } else if (int_st & BIT(HNS_ROCE_V2_VF_INT_ST_OTHER_ERR_S)) {
-               dev_err(dev, "OTHER ERR!\n");
-
-               int_st |= 1 << HNS_ROCE_V2_VF_INT_ST_OTHER_ERR_S;
-               roce_write(hr_dev, ROCEE_VF_ABN_INT_ST_REG, int_st);
-
-               int_en |= 1 << HNS_ROCE_V2_VF_ABN_INT_EN_S;
-               roce_write(hr_dev, ROCEE_VF_ABN_INT_EN_REG, int_en);
-
-               int_work = 1;
-       } else
+       } else {
                dev_err(dev, "There is no abnormal irq found!\n");
+       }
 
        return IRQ_RETVAL(int_work);
 }
index 3ad3f51..826f3d3 100644 (file)
@@ -1966,8 +1966,7 @@ struct hns_roce_dip {
 #define HNS_ROCE_V2_ASYNC_EQE_NUM              0x1000
 
 #define HNS_ROCE_V2_VF_INT_ST_AEQ_OVERFLOW_S   0
-#define HNS_ROCE_V2_VF_INT_ST_BUS_ERR_S                1
-#define HNS_ROCE_V2_VF_INT_ST_OTHER_ERR_S      2
+#define HNS_ROCE_V2_VF_INT_ST_RAS_INT_S                1
 
 #define HNS_ROCE_EQ_DB_CMD_AEQ                 0x0
 #define HNS_ROCE_EQ_DB_CMD_AEQ_ARMED           0x1