drm/i915/display: Implement new combo phy initialization step

This is new step that was recently added to the combo phy
initialization.

v2:
- using intel_de_rmw()

v3:
- going back to read() modify and write() as group register can't be
read

BSpec: 49291
Cc: Clinton A Taylor <clinton.a.taylor@intel.com>
Cc: Lucas De Marchi <lucas.demarchi@intel.com>
Reviewed-by: Matt Roper <matthew.d.roper@intel.com>
Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20200625195252.39312-1-jose.souza@intel.com

diff --git a/drivers/gpu/drm/i915/display/intel_combo_phy.c b/drivers/gpu/drm/i915/display/intel_combo_phy.c
index 77b04bb..eccaa79 100644 (file)
--- a/drivers/gpu/drm/i915/display/intel_combo_phy.c
+++ b/drivers/gpu/drm/i915/display/intel_combo_phy.c
@@ -264,6 +264,18 @@ static bool icl_combo_phy_verify_state(struct drm_i915_private *dev_priv,
        if (!icl_combo_phy_enabled(dev_priv, phy))
                return false;
 
+       if (INTEL_GEN(dev_priv) >= 12) {
+               ret &= check_phy_reg(dev_priv, phy, ICL_PORT_TX_DW8_LN0(phy),
+                                    ICL_PORT_TX_DW8_ODCC_CLK_SEL |
+                                    ICL_PORT_TX_DW8_ODCC_CLK_DIV_SEL_MASK,
+                                    ICL_PORT_TX_DW8_ODCC_CLK_SEL |
+                                    ICL_PORT_TX_DW8_ODCC_CLK_DIV_SEL_DIV2);
+
+               ret &= check_phy_reg(dev_priv, phy, ICL_PORT_PCS_DW1_LN0(phy),
+                                    DCC_MODE_SELECT_MASK,
+                                    DCC_MODE_SELECT_CONTINUOSLY);
+       }
+
        ret = cnl_verify_procmon_ref_values(dev_priv, phy);
 
        if (phy_is_master(dev_priv, phy)) {
@@ -375,6 +387,19 @@ static void icl_combo_phys_init(struct drm_i915_private *dev_priv)
                intel_de_write(dev_priv, ICL_PHY_MISC(phy), val);
 
 skip_phy_misc:
+               if (INTEL_GEN(dev_priv) >= 12) {
+                       val = intel_de_read(dev_priv, ICL_PORT_TX_DW8_LN0(phy));
+                       val &= ~ICL_PORT_TX_DW8_ODCC_CLK_DIV_SEL_MASK;
+                       val |= ICL_PORT_TX_DW8_ODCC_CLK_SEL;
+                       val |= ICL_PORT_TX_DW8_ODCC_CLK_DIV_SEL_DIV2;
+                       intel_de_write(dev_priv, ICL_PORT_TX_DW8_GRP(phy), val);
+
+                       val = intel_de_read(dev_priv, ICL_PORT_PCS_DW1_LN0(phy));
+                       val &= ~DCC_MODE_SELECT_MASK;
+                       val |= DCC_MODE_SELECT_CONTINUOSLY;
+                       intel_de_write(dev_priv, ICL_PORT_PCS_DW1_GRP(phy), val);
+               }
+
                cnl_set_procmon_ref_values(dev_priv, phy);
 
                if (phy_is_master(dev_priv, phy)) {

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 5bee4e2..86a23ce 100644 (file)
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -1974,6 +1974,8 @@ static inline bool i915_mmio_reg_valid(i915_reg_t reg)
 #define ICL_PORT_PCS_DW1_AUX(phy)      _MMIO(_ICL_PORT_PCS_DW_AUX(1, phy))
 #define ICL_PORT_PCS_DW1_GRP(phy)      _MMIO(_ICL_PORT_PCS_DW_GRP(1, phy))
 #define ICL_PORT_PCS_DW1_LN0(phy)      _MMIO(_ICL_PORT_PCS_DW_LN(1, 0, phy))
+#define   DCC_MODE_SELECT_MASK         (0x3 << 20)
+#define   DCC_MODE_SELECT_CONTINUOSLY  (0x3 << 20)
 #define   COMMON_KEEPER_EN             (1 << 26)
 #define   LATENCY_OPTIM_MASK           (0x3 << 2)
 #define   LATENCY_OPTIM_VAL(x)         ((x) << 2)
@@ -2072,6 +2074,13 @@ static inline bool i915_mmio_reg_valid(i915_reg_t reg)
 #define   N_SCALAR(x)                  ((x) << 24)
 #define   N_SCALAR_MASK                        (0x7F << 24)
 
+#define ICL_PORT_TX_DW8_AUX(phy)               _MMIO(_ICL_PORT_TX_DW_AUX(8, phy))
+#define ICL_PORT_TX_DW8_GRP(phy)               _MMIO(_ICL_PORT_TX_DW_GRP(8, phy))
+#define ICL_PORT_TX_DW8_LN0(phy)               _MMIO(_ICL_PORT_TX_DW_LN(8, 0, phy))
+#define   ICL_PORT_TX_DW8_ODCC_CLK_SEL         REG_BIT(31)
+#define   ICL_PORT_TX_DW8_ODCC_CLK_DIV_SEL_MASK        REG_GENMASK(30, 29)
+#define   ICL_PORT_TX_DW8_ODCC_CLK_DIV_SEL_DIV2        REG_FIELD_PREP(ICL_PORT_TX_DW8_ODCC_CLK_DIV_SEL_MASK, 0x1)
+
 #define _ICL_DPHY_CHKN_REG                     0x194
 #define ICL_DPHY_CHKN(port)                    _MMIO(_ICL_COMBOPHY(port) + _ICL_DPHY_CHKN_REG)
 #define   ICL_DPHY_CHKN_AFE_OVER_PPI_STRAP     REG_BIT(7)