The PowerNV machine emulates an OpenPOWER system and the PowerNV chip
devices are models of the internal logic of the POWER processor. They
can not be instantiated by the user on the QEMU command line.
The PHB3/PHB4 devices could be an exception in the future after some
rework on how the device tree is built. For the moment, exclude them
also.
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Message-Id: <
20200129113720.7404-1-clg@kaod.org>
Tested-by: Thomas Huth <thuth@redhat.com>
Reviewed-by: Greg Kurz <groug@kaod.org>
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
dc->realize = pnv_phb3_realize;
device_class_set_props(dc, pnv_phb3_properties);
set_bit(DEVICE_CATEGORY_BRIDGE, dc->categories);
+ dc->user_creatable = false;
}
static const TypeInfo pnv_phb3_type_info = {
device_class_set_parent_realize(dc, pnv_phb3_root_port_realize,
&rpc->parent_realize);
+ dc->user_creatable = false;
k->vendor_id = PCI_VENDOR_ID_IBM;
k->device_id = 0x03dc;
xdc->dt_xscom = pnv_pbcq_dt_xscom;
dc->realize = pnv_pbcq_realize;
+ dc->user_creatable = false;
}
static const TypeInfo pnv_pbcq_type_info = {
dc->realize = pnv_phb4_realize;
device_class_set_props(dc, pnv_phb4_properties);
set_bit(DEVICE_CATEGORY_BRIDGE, dc->categories);
- dc->user_creatable = true;
+ dc->user_creatable = false;
dc->reset = pnv_phb4_reset;
xfc->notify = pnv_phb4_xive_notify;
PCIERootPortClass *rpc = PCIE_ROOT_PORT_CLASS(klass);
dc->desc = "IBM PHB4 PCIE Root Port";
+ dc->user_creatable = false;
device_class_set_parent_realize(dc, pnv_phb4_root_port_realize,
&rpc->parent_realize);
dc->realize = pnv_pec_realize;
device_class_set_props(dc, pnv_pec_properties);
+ dc->user_creatable = false;
pecc->xscom_nest_base = pnv_pec_xscom_nest_base;
pecc->xscom_pci_base = pnv_pec_xscom_pci_base;
device_class_set_props(dc, pnv_pec_stk_properties);
dc->realize = pnv_pec_stk_realize;
+ dc->user_creatable = false;
/* TODO: reset regs ? */
}
dc->realize = pnv_core_realize;
dc->unrealize = pnv_core_unrealize;
device_class_set_props(dc, pnv_core_properties);
+ dc->user_creatable = false;
}
#define DEFINE_PNV_CORE_TYPE(family, cpu_model) \
dc->realize = pnv_quad_realize;
device_class_set_props(dc, pnv_quad_properties);
+ dc->user_creatable = false;
}
static const TypeInfo pnv_quad_info = {
dc->realize = pnv_homer_realize;
dc->desc = "PowerNV HOMER Memory";
device_class_set_props(dc, pnv_homer_properties);
+ dc->user_creatable = false;
}
static const TypeInfo pnv_homer_type_info = {
dc->realize = pnv_lpc_realize;
dc->desc = "PowerNV LPC Controller";
device_class_set_props(dc, pnv_lpc_properties);
+ dc->user_creatable = false;
}
static const TypeInfo pnv_lpc_info = {
dc->realize = pnv_occ_realize;
dc->desc = "PowerNV OCC Controller";
device_class_set_props(dc, pnv_occ_properties);
+ dc->user_creatable = false;
}
static const TypeInfo pnv_occ_type_info = {