MIPS: CI20: Reduce clocksource to 750 kHz.

The original clock (3 MHz) is too fast for the clocksource,
there will be a chance that the system may get stuck.

Reported-by: Nikolaus Schaller <hns@goldelico.com>
Tested-by: Nikolaus Schaller <hns@goldelico.com> # on CI20
Signed-off-by: 周琰杰 (Zhou Yanjie) <zhouyanjie@wanyeetech.com>
Acked-by: Paul Cercueil <paul@crapouillou.net>
Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>

diff --git a/arch/mips/boot/dts/ingenic/ci20.dts b/arch/mips/boot/dts/ingenic/ci20.dts
index 8877c62..3a4eaf1 100644 (file)
--- a/arch/mips/boot/dts/ingenic/ci20.dts
+++ b/arch/mips/boot/dts/ingenic/ci20.dts
@@ -525,10 +525,10 @@
 
 &tcu {
        /*
-        * 750 kHz for the system timer and 3 MHz for the clocksource,
+        * 750 kHz for the system timer and clocksource,
         * use channel #0 for the system timer, #1 for the clocksource.
         */
        assigned-clocks = <&tcu TCU_CLK_TIMER0>, <&tcu TCU_CLK_TIMER1>,
                                          <&tcu TCU_CLK_OST>;
-       assigned-clock-rates = <750000>, <3000000>, <3000000>;
+       assigned-clock-rates = <750000>, <750000>, <3000000>;
 };