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drm/amd/powerplay: error out when force clock level under auto dpm mode V2
authorEvan Quan <evan.quan@amd.com>
Wed, 17 Oct 2018 08:36:02 +0000 (16:36 +0800)
committerAlex Deucher <alexander.deucher@amd.com>
Mon, 22 Oct 2018 19:40:30 +0000 (14:40 -0500)
Forcing clock level is supported under manual dpm mode only. Error out
when trying to set under manual mode. Instead of doing nothing and
reporting success.

V2: update for mclk/pcie clock level settings also

Signed-off-by: Evan Quan <evan.quan@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c
drivers/gpu/drm/amd/powerplay/amd_powerplay.c

index 94055a4..59cc678 100644 (file)
@@ -704,7 +704,10 @@ static ssize_t amdgpu_set_pp_dpm_sclk(struct device *dev,
                return ret;
 
        if (adev->powerplay.pp_funcs->force_clock_level)
-               amdgpu_dpm_force_clock_level(adev, PP_SCLK, mask);
+               ret = amdgpu_dpm_force_clock_level(adev, PP_SCLK, mask);
+
+       if (ret)
+               return -EINVAL;
 
        return count;
 }
@@ -737,7 +740,10 @@ static ssize_t amdgpu_set_pp_dpm_mclk(struct device *dev,
                return ret;
 
        if (adev->powerplay.pp_funcs->force_clock_level)
-               amdgpu_dpm_force_clock_level(adev, PP_MCLK, mask);
+               ret = amdgpu_dpm_force_clock_level(adev, PP_MCLK, mask);
+
+       if (ret)
+               return -EINVAL;
 
        return count;
 }
@@ -770,7 +776,10 @@ static ssize_t amdgpu_set_pp_dpm_pcie(struct device *dev,
                return ret;
 
        if (adev->powerplay.pp_funcs->force_clock_level)
-               amdgpu_dpm_force_clock_level(adev, PP_PCIE, mask);
+               ret = amdgpu_dpm_force_clock_level(adev, PP_PCIE, mask);
+
+       if (ret)
+               return -EINVAL;
 
        return count;
 }
index e8964ca..da9ff2c 100644 (file)
@@ -723,11 +723,14 @@ static int pp_dpm_force_clock_level(void *handle,
                pr_info("%s was not implemented.\n", __func__);
                return 0;
        }
+
+       if (hwmgr->dpm_level != AMD_DPM_FORCED_LEVEL_MANUAL) {
+               pr_info("force clock level is for dpm manual mode only.\n");
+               return -EINVAL;
+       }
+
        mutex_lock(&hwmgr->smu_lock);
-       if (hwmgr->dpm_level == AMD_DPM_FORCED_LEVEL_MANUAL)
-               ret = hwmgr->hwmgr_func->force_clock_level(hwmgr, type, mask);
-       else
-               ret = -EINVAL;
+       ret = hwmgr->hwmgr_func->force_clock_level(hwmgr, type, mask);
        mutex_unlock(&hwmgr->smu_lock);
        return ret;
 }