trace_drm_sched_job(sched_job, entity);
+ atomic_inc(&entity->rq->sched->num_jobs);
WRITE_ONCE(entity->last_user, current->group_leader);
first = spsc_queue_push(&entity->job_queue, &sched_job->queue_node);
dma_fence_get(&s_fence->finished);
atomic_dec(&sched->hw_rq_count);
+ atomic_dec(&sched->num_jobs);
drm_sched_fence_finished(s_fence);
trace_drm_sched_process_job(s_fence);
INIT_LIST_HEAD(&sched->ring_mirror_list);
spin_lock_init(&sched->job_list_lock);
atomic_set(&sched->hw_rq_count, 0);
+ atomic_set(&sched->num_jobs, 0);
atomic64_set(&sched->job_id_count, 0);
/* Each scheduler will run on a seperate kernel thread */
* @job_list_lock: lock to protect the ring_mirror_list.
* @hang_limit: once the hangs by a job crosses this limit then it is marked
* guilty and it will be considered for scheduling further.
+ * @num_jobs: the number of jobs in queue in the scheduler
*
* One scheduler is implemented for each hardware ring.
*/
struct list_head ring_mirror_list;
spinlock_t job_list_lock;
int hang_limit;
+ atomic_t num_jobs;
};
int drm_sched_init(struct drm_gpu_scheduler *sched,