drm/i915/dsi: Enable dithering for 6 bpc panels

The display engine has 2 dithering enable bits which both need to be set
for dithering to happen, 1 in the PIPECONF register which is taken care of
by i9xx_set_pipeconf() and a second bit at the encoder level.

The dsi code was not setting the encoder level dithering enable bit causing
dithering to be disabled, this commit fixes this.

Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20181201113148.23184-2-hdegoede@redhat.com

diff --git a/drivers/gpu/drm/i915/vlv_dsi.c b/drivers/gpu/drm/i915/vlv_dsi.c
index 54cbd8e..4d47910 100644 (file)
--- a/drivers/gpu/drm/i915/vlv_dsi.c
+++ b/drivers/gpu/drm/i915/vlv_dsi.c
@@ -678,6 +678,10 @@ static void intel_dsi_port_enable(struct intel_encoder *encoder,
                                        LANE_CONFIGURATION_DUAL_LINK_B :
                                        LANE_CONFIGURATION_DUAL_LINK_A;
                }
+
+               if (intel_dsi->pixel_format != MIPI_DSI_FMT_RGB888)
+                       temp |= DITHERING_ENABLE;
+
                /* assert ip_tg_enable signal */
                I915_WRITE(port_ctrl, temp | DPI_ENABLE);
                POSTING_READ(port_ctrl);