# CONFIG_ICACHE_ALGOLRU is not set
# CONFIG_ICACHE_LOCK is not set
CONFIG_DCACHE_ENABLE=y
-# CONFIG_DCACHE_ASSO1 is not set
-CONFIG_DCACHE_ASSO2=y
+CONFIG_DCACHE_ASSO1=y
+# CONFIG_DCACHE_ASSO2 is not set
# CONFIG_DCACHE_ASSO3 is not set
# CONFIG_DCACHE_ASSO4 is not set
# CONFIG_DCACHE_SZ1 is not set
# CONFIG_DCACHE_SZ256 is not set
CONFIG_DCACHE_LZ16=y
# CONFIG_DCACHE_LZ32 is not set
-# CONFIG_DCACHE_ALGORND is not set
-CONFIG_DCACHE_ALGOLRR=y
-# CONFIG_DCACHE_ALGOLRU is not set
-# CONFIG_DCACHE_LOCK is not set
CONFIG_DCACHE_SNOOP=y
# CONFIG_DCACHE_SNOOP_FAST is not set
# CONFIG_DCACHE_SNOOP_SEPTAG is not set
constant CFG_ILRAMADDR: integer := 16#8E#;
constant CFG_ILRAMSZ : integer := 1;
constant CFG_DCEN : integer := 1;
- constant CFG_DSETS : integer := 2;
+ constant CFG_DSETS : integer := 1;
constant CFG_DSETSZ : integer := 4;
constant CFG_DLINE : integer := 4;
- constant CFG_DREPL : integer := 1;
+ constant CFG_DREPL : integer := 0;
constant CFG_DLOCK : integer := 0;
constant CFG_DSNOOP : integer := 1 + 0 + 4*0;
constant CFG_DFIXED : integer := 16#0#;
--- YCC-RGB translation module ------------------------------------
-----------------------------------------------------------------------
- jpgycc : yccrgbs
- generic map(shindex => 5, haddr => 16#B00#, hirq => 13, pindex => 14,
+ jpgycc : upycc
+ generic map(memtech => memtech, shindex => 5, haddr => 16#B00#, hirq => 13, pindex => 14,
paddr => 7, mhindex => 3 )
port map(rst => rstn, clk => clkm, ahbmi => ahbmi,
ahbmo => ahbmo(3), ahbsi => ahbsi, ahbso => ahbso(5),
//#define NORMALTEST
-#define IP_CONNECT
-//#define BOARD_TEST
+//#define IP_CONNECT
+#define BOARD_TEST
main()
{
#endif
#ifdef IP_CONNECT
- yccrgbs_connect_neek();
+ upycc_connect_neek();
#endif
#ifdef BOARD_TEST
- yccrgbs_pic_neek();
+ upycc_pic_neek();
#endif
}
-------------------------------------------------------------------------------
--- YCC-RGB translation module ---------------------------------------
+-- Upsample YCC-RGB translation module ---------------------------------------
-------------------------------------------------------------------------------
- jpgycc : yccrgbs
+ jpgycc : upycc
generic map(shindex => 4, haddr => 16#A00#, hirq => 10, pindex => 12,
paddr => 12, mhindex => CFG_NCPU+CFG_AHB_UART+CFG_GRETH+CFG_AHB_JTAG+
CFG_SVGA_ENABLE+CFG_SPW_NUM*CFG_SPW_EN+CFG_GRUSB_DCL+
GRLIB=../..
-TOP=bus_yccrgbs
+TOP=bus_upycc
BOARD=altera-ep3c25-eek
include $(GRLIB)/boards/$(BOARD)/Makefile.inc
DEVICE=$(PART)-$(PACKAGE)$(SPEED)
EFFORT=std
XSTOPT=
SYNPOPT="set_option -pipe 1; set_option -retiming 1"
-VHDLSYNFILES=config.vhd bus_yccrgbs.vhd
-VHDLSIMFILES=sim_yccrgbs.vhd
-SIMTOP=sim_yccrgbs
+VHDLSYNFILES=config.vhd bus_upycc.vhd
+VHDLSIMFILES=sim_upycc.vhd
+SIMTOP=sim_upycc
SDCFILE=$(GRLIB)/boards/$(BOARD)/default.sdc
BITGEN=$(GRLIB)/boards/$(BOARD)/default.ut
CLEAN=soft-clean
--- /dev/null
+------------------------------------------------------------------------------
+-- Copyright (C) 2010, Kenichi Kurimoto
+--
+-- This program is free software; you can redistribute it and/or modify
+-- it under the terms of the GNU General Public License as published by
+-- the Free Software Foundation; either version 2 of the License, or
+-- (at your option) any later version.
+--
+-- This program is distributed in the hope that it will be useful,
+-- but WITHOUT ANY WARRANTY; without even the implied warranty of
+-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+-- GNU General Public License for more details.
+--
+-- You should have received a copy of the GNU General Public License
+-- along with this program; if not, write to the Free Software
+-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+-----------------------------------------------------------------------------
+
+
+
+
+
+library ieee;
+use ieee.std_logic_1164.all;
+
+library grlib,techmap;
+use grlib.amba.all;
+use grlib.stdlib.all;
+use techmap.gencomp.all;
+library gaisler;
+use gaisler.misc.all;
+--use gaisler.ambatest.all;
+use gaisler.ahbtbp.all;
+library kuri;
+use kuri.mjpeg.all;
+
+use work.config.all;
+
+entity bus_upycc is
+ port (
+ rstn : in std_ulogic;
+ clk : in std_ulogic;
+ ctrl_in1 : in ahbtbm_ctrl_in_type;
+ ctrl_out1 : out ahbtbm_ctrl_out_type);
+end;
+
+architecture rtl of bus_upycc is
+
+
+ signal apbi : apb_slv_in_type;
+ signal apbo : apb_slv_out_vector := (others => apb_none);
+ signal ahbsi : ahb_slv_in_type;
+ signal ahbso : ahb_slv_out_vector := (others => ahbs_none);
+ signal ahbmi : ahb_mst_in_type;
+ signal ahbmo : ahb_mst_out_vector := (others => ahbm_none);
+
+-- signal rst : std_ulogic;
+
+
+
+begin -- rtl
+
+
+-- rst <= not rstn;
+
+ upyccinst : upycc
+ generic map(shindex => 2, haddr => 16#900#, pindex => 2, paddr => 2, mhindex => 3, hirq => 2)
+ port map (rstn, clk, ahbmi, ahbmo(3), ahbsi, ahbso(2), apbi, apbo(2));
+
+ apb0 : apbctrl
+ generic map (hindex => 4, haddr => 16#800#)
+ port map(rstn, clk, ahbsi, ahbso(4), apbi, apbo);
+
+ ahbcontroller : ahbctrl -- AHB arbiter/multiplexer
+ generic map (defmast => CFG_DEFMST, split => CFG_SPLIT,
+ enbusmon => 0,rrobin => CFG_RROBIN, ioaddr => CFG_AHBIO)
+ port map (rstn, clk, ahbmi, ahbmo, ahbsi, ahbso);
+
+ ram0 : ahbram
+ generic map (hindex => 7, haddr => 16#a00#, tech => CFG_MEMTECH, kbytes => 24)
+ port map (rstn, clk, ahbsi, ahbso(7));
+
+ mast_em : ahbtbm
+ generic map(hindex => 0)
+ port map (rstn, clk, ctrl_in1, ctrl_out1, ahbmi, ahbmo(0));
+
+
+
+-- mast_em2 : ahbtbm
+-- generic map(hindex => 1)
+-- port map (rstn, clk, ctrl_in2, ctrl_out2, ahbmi, ahbmo(1));
+
+end rtl;
+
--- /dev/null
+../../../snapgear-2.6-p42/user/jpeg-6b-host/in_upycc.txt
\ No newline at end of file
--- /dev/null
+../../../snapgear-2.6-p42/user/jpeg-6b-host/out_upycc.txt
\ No newline at end of file
--- /dev/null
+------------------------------------------------------------------------------
+-- Copyright (C) 2010, Kenichi Kurimoto
+--
+-- This program is free software; you can redistribute it and/or modify
+-- it under the terms of the GNU General Public License as published by
+-- the Free Software Foundation; either version 2 of the License, or
+-- (at your option) any later version.
+--
+-- This program is distributed in the hope that it will be useful,
+-- but WITHOUT ANY WARRANTY; without even the implied warranty of
+-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+-- GNU General Public License for more details.
+--
+-- You should have received a copy of the GNU General Public License
+-- along with this program; if not, write to the Free Software
+-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+-----------------------------------------------------------------------------
+
+
+
+library ieee;
+use ieee.std_logic_1164.all;
+use std.textio.all;
+use ieee.std_logic_textio.all;
+--use ieee.numeric_std.all;
+
+
+library gaisler;
+use gaisler.sim.all;
+use gaisler.ambatest.all;
+use gaisler.ahbtbp.all;
+library techmap;
+use techmap.gencomp.all;
+library grlib;
+use grlib.stdlib.all;
+library kuri;
+use kuri.mjpeg.all;
+
+use work.debug.all;
+use work.config.all;
+
+
+
+entity sim_upycc is
+
+ generic (
+ clkperiod : integer := 20);
+
+end ;
+
+architecture behav of sim_upycc is
+
+
+
+ component bus_upycc
+ port(
+ rstn : in std_ulogic;
+ clk : in std_ulogic;
+ ctrl_in1 : in ahbtbm_ctrl_in_type;
+ ctrl_out1 : out ahbtbm_ctrl_out_type
+ );
+
+ end component;
+
+signal clk : std_ulogic := '0';
+signal rst : std_ulogic := '0';
+signal ctrl1 : ahbtb_ctrl_type;
+-- signal data_in : std_logic_vector(31 downto 0);
+
+file in_file : text open read_mode is "in_upycc.txt";
+file compare_file : text open read_mode is "out_upycc.txt";
+
+begin -- behav
+
+ b0 : bus_upycc
+ port map (rst,clk,ctrl1.i,ctrl1.o);
+
+ tictak : process
+ begin
+ clk <= '0';
+ wait for 10 ns;
+ clk <= '1';
+ wait for 10 ns;
+ end process;
+
+ stim: process
+ variable li : line;
+ variable lc : line;
+ variable i,j : integer;
+ -- variable ycc : std_logic_vector(23 downto 0);
+ variable eightbdata : std_logic_vector(7 downto 0);
+ variable indata : std_logic_vector(31 downto 0);
+ variable radd : std_logic_vector(31 downto 0);
+ -- variable cdata1, cdata2 : std_logic_vector(15 downto 0);
+ variable cdata32 : std_logic_vector(31 downto 0);
+
+ begin
+
+ report " stimulus process start ";
+
+ rst <= '0';
+ wait for 100 ns;
+ rst <= '1';
+
+ -- initialize
+ ahbtbminit(ctrl1);
+
+-- Write Control registers through APB bus
+
+ahbwrite(x"80000200", x"a0000000", "10", "10", '1', 2, false , ctrl1);
+ahbwrite(x"80000204", x"00082464", "10", "10", '1', 2, false , ctrl1);
+ahbwrite(x"80000208", x"04E4B504", "10", "10", '1', 2, false , ctrl1);
+ahbwrite(x"8000020C", x"00000000", "10", "10", '1', 2, false , ctrl1);
+ahbwrite(x"8000020C", x"ffffffff", "10", "10", '1', 2, false , ctrl1);
+
+-- Write YCC data for IP core
+-- for i in 0 to 33821 loop
+ for i in 0 to 3999 loop
+ readline(in_file,li);
+ hread(li, eightbdata);
+ indata := x"000000" & eightbdata;
+ ahbwrite(x"90000000", indata, "10", "10", '1', 2, false , ctrl1);
+ ahbtbmidle(true, ctrl1);
+ wait for 20 ns;
+ end loop;
+
+ radd := x"a0000000";
+-- for i in 0 to 79 loop
+ for i in 0 to 17 loop
+ for j in 0 to 39 loop
+ readline(compare_file, lc);
+ hread(lc, cdata32);
+ ahbread(radd, cdata32, "10", 2, false, ctrl1);
+ radd := radd + x"004";
+ end loop;
+ radd := radd + x"460";
+ end loop;
+
+ ahbtbmidle(true,ctrl1);
+ wait for 100 ns;
+
+
+ ahbtbmdone(0, ctrl1);
+ wait for 300 ns;
+
+ report "stimulus process end" severity failure;
+ wait;
+ end process;
+
+end behav;
--- /dev/null
+------------------------------------------------------------------------------
+-- Copyright (C) 2010, Kenichi Kurimoto
+--
+-- This program is free software; you can redistribute it and/or modify
+-- it under the terms of the GNU General Public License as published by
+-- the Free Software Foundation; either version 2 of the License, or
+-- (at your option) any later version.
+--
+-- This program is distributed in the hope that it will be useful,
+-- but WITHOUT ANY WARRANTY; without even the implied warranty of
+-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+-- GNU General Public License for more details.
+--
+-- You should have received a copy of the GNU General Public License
+-- along with this program; if not, write to the Free Software
+-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+-----------------------------------------------------------------------------
+
+
+
+library ieee;
+use ieee.std_logic_1164.all;
+use std.textio.all;
+use ieee.std_logic_textio.all;
+--use ieee.numeric_std.all;
+
+
+library gaisler;
+use gaisler.sim.all;
+use gaisler.ambatest.all;
+use gaisler.ahbtbp.all;
+library techmap;
+use techmap.gencomp.all;
+library grlib;
+use grlib.stdlib.all;
+library kuri;
+use kuri.mjpeg.all;
+
+use work.debug.all;
+use work.config.all;
+
+
+
+entity sim_upycc is
+
+ generic (
+ clkperiod : integer := 20);
+
+end ;
+
+architecture behav of sim_upycc is
+
+
+
+ component bus_upycc
+ port(
+ rstn : in std_ulogic;
+ clk : in std_ulogic;
+ ctrl_in1 : in ahbtbm_ctrl_in_type;
+ ctrl_out1 : out ahbtbm_ctrl_out_type
+ );
+
+ end component;
+
+signal clk : std_ulogic := '0';
+signal rst : std_ulogic := '0';
+signal ctrl1 : ahbtb_ctrl_type;
+-- signal data_in : std_logic_vector(31 downto 0);
+
+file in_file : text open read_mode is "in_upycc.txt";
+file compare_file : text open read_mode is "out_upycc.txt";
+
+begin -- behav
+
+ b0 : bus_upycc
+ port map (rst,clk,ctrl1.i,ctrl1.o);
+
+ tictak : process
+ begin
+ clk <= '0';
+ wait for 10 ns;
+ clk <= '1';
+ wait for 10 ns;
+ end process;
+
+ stim: process
+ variable li : line;
+ variable lc : line;
+ variable i,j : integer;
+ -- variable ycc : std_logic_vector(23 downto 0);
+ variable eightbdata : std_logic_vector(7 downto 0);
+ variable indata : std_logic_vector(31 downto 0);
+ variable radd : std_logic_vector(31 downto 0);
+ -- variable cdata1, cdata2 : std_logic_vector(15 downto 0);
+ variable cdata32 : std_logic_vector(31 downto 0);
+
+ begin
+
+ report " stimulus process start ";
+
+ rst <= '0';
+ wait for 100 ns;
+ rst <= '1';
+
+ -- initialize
+ ahbtbminit(ctrl1);
+
+-- Write Control registers through APB bus
+
+ahbwrite(x"80000200", x"a0000000", "10", "10", '1', 2, false , ctrl1);
+ahbwrite(x"80000204", x"00082464", "10", "10", '1', 2, false , ctrl1);
+--ahbwrite(x"80000204", x"000A2C44", "10", "10", '1', 2, false , ctrl1);
+ahbwrite(x"80000208", x"00000000", "10", "10", '1', 2, false , ctrl1);
+ahbwrite(x"80000208", x"ffffffff", "10", "10", '1', 2, false , ctrl1);
+
+-- Write YCC data for IP core
+-- for i in 0 to 33821 loop
+ for i in 0 to 3999 loop
+ readline(in_file,li);
+ hread(li, eightbdata);
+ indata := x"000000" & eightbdata;
+ ahbwrite(x"90000000", indata, "10", "10", '1', 2, false , ctrl1);
+ ahbtbmidle(true, ctrl1);
+ wait for 20 ns;
+ end loop;
+
+ radd := x"a0000000";
+-- for i in 0 to 79 loop
+ for i in 0 to 17 loop
+ for j in 0 to 39 loop
+ readline(compare_file, lc);
+ hread(lc, cdata32);
+ ahbread(radd, cdata32, "10", 2, false, ctrl1);
+ radd := radd + x"004";
+ end loop;
+ radd := radd + x"460";
+ end loop;
+
+ ahbtbmidle(true,ctrl1);
+ wait for 100 ns;
+
+
+ ahbtbmdone(0, ctrl1);
+ wait for 300 ns;
+
+ report "stimulus process end" severity failure;
+ wait;
+ end process;
+
+end behav;
package mjpeg is
+component upycc
+ generic (
+ memtech : integer := DEFMEMTECH;
+-- fifo_depth : integer := 32;
+ shindex : integer := 0;
+ haddr : integer := 0;
+ hmask : integer := 16#fff#;
+ hirq : integer := 0;
+ pindex : integer := 0;
+ paddr : integer := 0;
+ pmask : integer := 16#fff#;
+ mhindex : integer := 0;
+ chprot : integer := 3);
+ port (
+ rst : in std_ulogic;
+ clk : in std_ulogic;
+ ahbmi : in ahb_mst_in_type;
+ ahbmo : out ahb_mst_out_type;
+ ahbsi : in ahb_slv_in_type;
+ ahbso : out ahb_slv_out_type;
+ apbi : in apb_slv_in_type;
+ apbo : out apb_slv_out_type
+ );
+end component;
+
+component yccambaif
+ generic (
+ memtech : integer := DEFMEMTECH;
+ shindex : integer := 0;
+ haddr : integer := 0;
+ hmask : integer := 16#fff#;
+ hirq : integer := 0;
+ pindex : integer := 0;
+ paddr : integer := 0;
+ pmask : integer := 16#fff#);
+ port (
+ rst : in std_ulogic;
+ clk : in std_ulogic;
+ ahbsi : in ahb_slv_in_type;
+ ahbso : out ahb_slv_out_type;
+ apbi : in apb_slv_in_type;
+ apbo : out apb_slv_out_type;
+ kready : in std_logic;
+ kstrobe : out std_logic;
+ kdata : out std_logic_vector(7 downto 0);
+ samp_fact : out std_logic;
+ error : in std_logic;
+ xmcumax : out std_logic_vector(5 downto 0);
+ ymcumax : out std_logic_vector(4 downto 0);
+ incaddy : out std_logic_vector(15 downto 0);
+ incaddmcux : out std_logic_vector(15 downto 0);
+ incaddmcuy : out std_logic_vector(10 downto 0);
+ fbstartadd : out std_logic_vector(31 downto 0);
+ startgen : out std_logic
+ );
+end component;
+
+component yccmemcont
+ generic (
+ memtech : integer := DEFMEMTECH);
+ port (
+ rst : in std_ulogic;
+ clk : in std_ulogic;
+ kready1 : out std_logic;
+ kstrobe1 : in std_logic;
+ kdata1 : in std_logic_vector(7 downto 0);
+ kready2 : in std_logic;
+ kstrobe2 : out std_logic;
+ kdata2 : out std_logic_vector(23 downto 0);
+ samp_fact : in std_logic;
+ error : out std_logic
+ );
+end component;
+
+component yccrgb
+ generic (
+ memtech : integer := DEFMEMTECH;
+ hirq : integer := 0;
+ mhindex : integer := 0;
+ chprot : integer := 3);
+ port (
+ rst : in std_ulogic;
+ clk : in std_ulogic;
+ ahbmi : in ahb_mst_in_type;
+ ahbmo : out ahb_mst_out_type;
+ kready : out std_logic;
+ kstrobe : in std_logic;
+ kdata : in std_logic_vector(23 downto 0);
+ xmcumax : in std_logic_vector(5 downto 0);
+ ymcumax : in std_logic_vector(4 downto 0);
+ incaddy : in std_logic_vector(15 downto 0);
+ incaddmcux : in std_logic_vector(15 downto 0);
+ incaddmcuy : in std_logic_vector(10 downto 0);
+ fbstartadd : in std_logic_vector(31 downto 0);
+ startgen : in std_logic
+ );
+end component;
+
component yccrgbs
generic (
memtech : integer := DEFMEMTECH;
--- /dev/null
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+library grlib;
+use grlib.stdlib.all;
+use grlib.amba.all;
+use grlib.devices.all;
+
+library techmap;
+use techmap.gencomp.all;
+
+package mjpeg is
+
+component upycc
+ generic (
+ memtech : integer := DEFMEMTECH;
+-- fifo_depth : integer := 32;
+ shindex : integer := 0;
+ haddr : integer := 0;
+ hmask : integer := 16#fff#;
+ hirq : integer := 0;
+ pindex : integer := 0;
+ paddr : integer := 0;
+ pmask : integer := 16#fff#;
+ mhindex : integer := 0;
+ chprot : integer := 3);
+ port (
+ rst : in std_ulogic;
+ clk : in std_ulogic;
+ ahbmi : in ahb_mst_in_type;
+ ahbmo : out ahb_mst_out_type;
+ ahbsi : in ahb_slv_in_type;
+ ahbso : out ahb_slv_out_type;
+ apbi : in apb_slv_in_type;
+ apbo : out apb_slv_out_type
+ );
+end component;
+
+component yccambaif
+ generic (
+ memtech : integer := DEFMEMTECH;
+ shindex : integer := 0;
+ haddr : integer := 0;
+ hmask : integer := 16#fff#;
+ hirq : integer := 0;
+ pindex : integer := 0;
+ paddr : integer := 0;
+ pmask : integer := 16#fff#);
+ port (
+ rst : in std_ulogic;
+ clk : in std_ulogic;
+ ahbsi : in ahb_slv_in_type;
+ ahbso : out ahb_slv_out_type;
+ apbi : in apb_slv_in_type;
+ apbo : out apb_slv_out_type;
+ kready : in std_logic;
+ kstrobe : out std_logic;
+ kdata : out std_logic_vector(7 downto 0);
+ samp_fact : out std_logic;
+ error : in std_logic;
+ xmcumax : out std_logic_vector(5 downto 0);
+ ymcumax : out std_logic_vector(4 downto 0);
+ incaddy : in std_logic_vector(15 downto 0);
+ incaddmcux : in std_logic_vector(15 downto 0);
+ incaddmcuy : out std_logic_vector(10 downto 0);
+ fbstartadd : out std_logic_vector(31 downto 0);
+ startgen : out std_logic
+ );
+end component;
+
+component yccmemcont
+ generic (
+ memtech : integer := DEFMEMTECH);
+ port (
+ rst : in std_ulogic;
+ clk : in std_ulogic;
+ kready1 : out std_logic;
+ kstrobe1 : in std_logic;
+ kdata1 : in std_logic_vector(7 downto 0);
+ kready2 : in std_logic;
+ kstrobe2 : out std_logic;
+ kdata2 : out std_logic_vector(23 downto 0);
+ samp_fact : in std_logic;
+ error : out std_logic
+ );
+end component;
+
+component yccrgb
+ generic (
+ memtech : integer := DEFMEMTECH;
+ hirq : integer := 0;
+ mhindex : integer := 0;
+ chprot : integer := 3);
+ port (
+ rst : in std_ulogic;
+ clk : in std_ulogic;
+ ahbmi : in ahb_mst_in_type;
+ ahbmo : out ahb_mst_out_type;
+ kready : out std_logic;
+ kstrobe : in std_logic;
+ kdata : in std_logic_vector(23 downto 0);
+ xmcumax : in std_logic_vector(5 downto 0);
+ ymcumax : in std_logic_vector(4 downto 0);
+ incaddy : in std_logic_vector(15 downto 0);
+ incaddmcux : in std_logic_vector(15 downto 0);
+ incaddmcuy : in std_logic_vector(10 downto 0);
+ fbstartadd : in std_logic_vector(31 downto 0);
+ startgen : in std_logic
+ );
+end component;
+
+component yccrgbs
+ generic (
+ memtech : integer := DEFMEMTECH;
+ fifo_depth : integer := 32;
+ shindex : integer := 0;
+ chprot : integer := 3;
+ haddr : integer := 0;
+ hmask : integer := 16#fff#;
+ pindex : integer := 0;
+ paddr : integer := 0;
+ pmask : integer := 16#fff#;
+ mhindex : integer := 0;
+ hirq : integer := 0;
+ burst_num : integer := 16);
+ port (
+ rst : in std_ulogic;
+ clk : in std_ulogic;
+ ahbmi : in ahb_mst_in_type;
+ ahbmo : out ahb_mst_out_type;
+ ahbsi : in ahb_slv_in_type;
+ ahbso : out ahb_slv_out_type;
+ apbi : in apb_slv_in_type;
+ apbo : out apb_slv_out_type
+ );
+end component;
+
+end;
--- /dev/null
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+library grlib;
+use grlib.amba.all;
+use grlib.stdlib.all;
+use grlib.devices.all;
+
+library techmap;
+use techmap.gencomp.all;
+
+library kuri;
+use kuri.mjpeg.all;
+
+entity upycc is
+ generic (
+ memtech : integer := DEFMEMTECH;
+-- fifo_depth : integer := 32;
+ shindex : integer := 0;
+ haddr : integer := 0;
+ hmask : integer := 16#fff#;
+ hirq : integer := 0;
+ pindex : integer := 0;
+ paddr : integer := 0;
+ pmask : integer := 16#fff#;
+ mhindex : integer := 0;
+ chprot : integer := 3);
+
+ port (
+ rst : in std_ulogic;
+ clk : in std_ulogic;
+ ahbmi : in ahb_mst_in_type;
+ ahbmo : out ahb_mst_out_type;
+ ahbsi : in ahb_slv_in_type;
+ ahbso : out ahb_slv_out_type;
+ apbi : in apb_slv_in_type;
+ apbo : out apb_slv_out_type
+ );
+end;
+
+architecture rtl of upycc is
+
+signal kready1, kready2, kstrobe1, kstrobe2 : std_logic;
+signal kdata1 : std_logic_vector(7 downto 0);
+signal kdata2 : std_logic_vector(23 downto 0);
+signal samp_fact, error : std_logic;
+signal xmcumax : std_logic_vector(5 downto 0);
+signal ymcumax : std_logic_vector(4 downto 0);
+signal incaddy : std_logic_vector(15 downto 0);
+signal incaddmcux : std_logic_vector(15 downto 0);
+signal incaddmcuy : std_logic_vector(10 downto 0);
+signal fbstartadd : std_logic_vector(31 downto 0);
+signal startgen : std_logic;
+
+begin
+ amif : yccambaif
+ generic map(memtech => memtech,shindex => shindex , haddr => haddr, hmask => hmask,
+ hirq => hirq, pindex => pindex, paddr => paddr, pmask => pmask)
+ port map(rst => rst, clk => clk, ahbsi => ahbsi, ahbso => ahbso, apbi => apbi, apbo => apbo,
+ kready => kready1, kstrobe => kstrobe1, kdata => kdata1, samp_fact => samp_fact,
+ error => error, xmcumax => xmcumax, ymcumax => ymcumax, incaddy => incaddy,
+ incaddmcux => incaddmcux, incaddmcuy => incaddmcuy, fbstartadd => fbstartadd,
+ startgen => startgen);
+
+ yccmem : yccmemcont
+ generic map(memtech => memtech)
+ port map(rst => rst, clk => clk, kready1 => kready1, kstrobe1 => kstrobe1, kdata1 => kdata1,
+ kready2 => kready2, kstrobe2 => kstrobe2, kdata2 => kdata2, samp_fact => samp_fact,
+ error => error);
+
+ ycb : yccrgb
+ generic map(memtech => memtech, hirq => hirq, mhindex => mhindex,
+ chprot => chprot)
+ port map(rst => rst, clk => clk, ahbmi => ahbmi, ahbmo => ahbmo, kready => kready2,
+ kstrobe => kstrobe2, kdata => kdata2, xmcumax => xmcumax, ymcumax => ymcumax,
+ incaddy => incaddy, incaddmcux => incaddmcux, incaddmcuy => incaddmcuy,
+ fbstartadd => fbstartadd, startgen => startgen);
+
+end;
+
--- /dev/null
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+library grlib;
+use grlib.amba.all;
+use grlib.stdlib.all;
+use grlib.devices.all;
+
+library techmap;
+use techmap.gencomp.all;
+
+library kuri;
+use kuri.mjpeg.all;
+
+entity upycc is
+ generic (
+ memtech : integer := DEFMEMTECH;
+-- fifo_depth : integer := 32;
+ shindex : integer := 0;
+ haddr : integer := 0;
+ hmask : integer := 16#fff#;
+ hirq : integer := 0;
+ pindex : integer := 0;
+ paddr : integer := 0;
+ pmask : integer := 16#fff#;
+ mhindex : integer := 0;
+ chprot : integer := 3);
+
+ port (
+ rst : in std_ulogic;
+ clk : in std_ulogic;
+ ahbmi : in ahb_mst_in_type;
+ ahbmo : out ahb_mst_out_type;
+ ahbsi : in ahb_slv_in_type;
+ ahbso : out ahb_slv_out_type;
+ apbi : in apb_slv_in_type;
+ apbo : out apb_slv_out_type
+ );
+end;
+
+architecture rtl of upycc is
+
+signal kready1, kready2, kstrobe1, kstrobe2 : std_logic;
+signal kdata1 : std_logic_vector(7 downto 0);
+signal kdata2 : std_logic_vector(23 downto 0);
+signal samp_fact, error : std_logic;
+signal xmcumax : std_logic_vector(5 downto 0);
+signal ymcumax : std_logic_vector(4 downto 0);
+signal incaddy : std_logic_vector(15 downto 0);
+signal incaddmcux : std_logic_vector(15 downto 0);
+signal incaddmcuy : std_logic_vector(10 downto 0);
+signal fbstartadd : std_logic_vector(31 downto 0);
+signal startgen : std_logic;
+
+begin
+ amif : yccambaif
+ generic map(memtech => memtech,shindex => shindex , haddr => haddr, hmask => hmask,
+ hirq => hirq, pindex => pindex, paddr => paddr, pmask => pmask)
+ port map(rst => rst, clk => clk, ahbsi => ahbsi, ahbso => ahbso, apbi => apbi, apbo => apbo,
+ kready => kready1, kstrobe => kstrobe1, kdata => kdata1, samp_fact => samp_fact,
+ error => error, xmcumax => xmcumax, ymcumax => ymcumax, incaddy => incaddy,
+ incaddmcux => incaddmcux,
+ incaddmcuy => incaddmcuy,
+ fbstartadd => fbstartadd,
+ startgen => startgen);
+
+ yccmem : yccmemcont
+ generic map(memtech => memtech)
+ port map(rst => rst, clk => clk, kready1 => kready1, kstrobe1 => kstrobe1, kdata1 => kdata1,
+ kready2 => kready2, kstrobe2 => kstrobe2, kdata2 => kdata2, samp_fact => samp_fact,
+ error => error);
+
+ ycb : yccrgb
+ generic map(memtech => memtech, hirq => hirq, mhindex => mhindex,
+ chprot => chprot)
+ port map(rst => rst, clk => clk, ahbmi => ahbmi, ahbmo => ahbmo, kready => kready2,
+ kstrobe => kstrobe2, kdata => kdata2, xmcumax => xmcumax, ymcumax => ymcumax,
+ incaddy => incaddy, incaddmcux => incaddmcux, incaddmcuy => incaddmcuy,
+ fbstartadd => fbstartadd, startgen => startgen);
+
+end;
+
mjpeg.vhd
+upycc.vhd
+yccambaif.vhd
+yccmemcont.vhd
+yccrgb.vhd
yccrgbs.vhd
+
--- /dev/null
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+library grlib;
+use grlib.amba.all;
+use grlib.stdlib.all;
+use grlib.devices.all;
+
+library techmap;
+use techmap.gencomp.all;
+
+entity yccambaif is
+ generic (
+ memtech : integer := DEFMEMTECH;
+ shindex : integer := 0;
+ haddr : integer := 0;
+ hmask : integer := 16#fff#;
+ hirq : integer := 0;
+ pindex : integer := 0;
+ paddr : integer := 0;
+ pmask : integer := 16#fff#);
+ port (
+ rst : in std_ulogic;
+ clk : in std_ulogic;
+ ahbsi : in ahb_slv_in_type;
+ ahbso : out ahb_slv_out_type;
+ apbi : in apb_slv_in_type;
+ apbo : out apb_slv_out_type;
+ kready : in std_logic;
+ kstrobe : out std_logic;
+ kdata : out std_logic_vector(7 downto 0);
+ samp_fact : out std_logic;
+ error : in std_logic;
+ xmcumax : out std_logic_vector(5 downto 0);
+ ymcumax : out std_logic_vector(4 downto 0);
+ incaddy : out std_logic_vector(15 downto 0);
+ incaddmcux : out std_logic_vector(15 downto 0);
+ incaddmcuy : out std_logic_vector(10 downto 0);
+ fbstartadd : out std_logic_vector(31 downto 0);
+ startgen : out std_logic
+ );
+end;
+
+architecture rtl of yccambaif is
+
+constant shconfig : ahb_config_type := (
+ 0 => ahb_device_reg( VENDOR_CONTRIB, CONTRIB_CORE1, 0, 0, hirq),
+ 4 => ahb_membar(haddr, '0', '0', hmask),
+ others => zero32);
+
+constant pconfig : apb_config_type := (
+ 0 => ahb_device_reg( VENDOR_CONTRIB, CONTRIB_CORE1, 0, 0, 0),
+ 1 => apb_iobar(paddr, pmask));
+
+type ahbs_reg is record
+ get : std_logic;
+ hdata : std_logic_vector(7 downto 0);
+ written : std_ulogic;
+end record;
+
+type apbs_reg is record
+ sampf : std_logic;
+ xmcumax : std_logic_vector(5 downto 0);
+ ymcumax : std_logic_vector(4 downto 0);
+ incaddy : std_logic_vector(15 downto 0);
+ incaddmcux : std_logic_vector(15 downto 0);
+ incaddmcuy : std_logic_vector(10 downto 0);
+ fbstartadd : std_logic_vector(31 downto 0);
+ error_reg : std_logic_vector(2 downto 0);
+end record;
+
+type all_reg is record
+ hreg : ahbs_reg;
+ preg : apbs_reg;
+end record;
+
+signal r, rin : all_reg;
+
+begin
+comb : process (r, rst, ahbsi, apbi, kready, error)
+ variable v : all_reg;
+ variable apbwrite : std_logic;
+ variable vprdata : std_logic_vector(31 downto 0);
+ variable virq : std_logic_vector(NAHBIRQ-1 downto 0);
+ variable vstartgen : std_logic;
+ begin
+
+ v := r;
+ vprdata := (others => '0');
+ virq := (others => '0');
+ v.hreg.written := '0';
+ vstartgen := '0';
+
+-- apb controle part
+ apbwrite := apbi.psel(pindex) and apbi.pwrite and apbi.penable;
+ vprdata := (others => '0');
+ case apbi.paddr(5 downto 2) is
+ when "0000" =>
+ if apbwrite = '1' then
+ v.preg.fbstartadd := apbi.pwdata(31 downto 0);
+ end if;
+ vprdata := r.preg.fbstartadd(31 downto 0);
+ when "0001" =>
+ if apbwrite = '1' then
+ v.preg.sampf := apbi.pwdata(22);
+ v.preg.ymcumax := apbi.pwdata(21 downto 17);
+ v.preg.xmcumax := apbi.pwdata(16 downto 11);
+ v.preg.incaddmcuy := apbi.pwdata(10 downto 0);
+ end if;
+ vprdata := "0000000000" & r.preg.ymcumax & r.preg.xmcumax & r.preg.incaddmcuy;
+ when "0010" =>
+ if apbwrite = '1' then
+ v.preg.incaddy := apbi.pwdata(31 downto 16);
+ v.preg.incaddmcux := apbi.pwdata(15 downto 0);
+ end if;
+ vprdata := r.preg.incaddy & r.preg.incaddmcux;
+ when "0011" =>
+ if apbwrite = '1' then
+ if apbi.pwdata(31) = '1' then
+ vstartgen := '1';
+ end if;
+ v.preg.error_reg(2) := apbi.pwdata(31);
+ end if;
+ vprdata := r.preg.error_reg(2) & "00000000000000000000000000000" & r.preg.error_reg(1 downto 0);
+ when others =>
+ end case;
+
+ v.hreg.get := '0';
+-- ahb slave input part
+ if (ahbsi.hready = '1') and (ahbsi.hsel(shindex) = '1') then
+ if (ahbsi.haddr(15 downto 0) = "0000000000000000") and (ahbsi.hwrite = '1') and (ahbsi.htrans = HTRANS_NONSEQ) then
+ v.hreg.get := '1';
+ end if;
+ end if;
+ if r.hreg.get = '1' then
+ v.hreg.hdata(7 downto 0) := ahbsi.hwdata(7 downto 0);
+ v.hreg.written := '1';
+ end if;
+
+-- reset part
+ if rst = '0' then
+ v.hreg.hdata := (others => '0');
+ v.hreg.written := '0';
+ v.hreg.get := '0';
+ v.preg.xmcumax := (others => '0');
+ v.preg.ymcumax := (others => '0');
+ v.preg.incaddmcuy := (others => '0');
+ v.preg.error_reg := (others => '0');
+ end if;
+
+-- signal
+ rin <= v;
+ apbo.prdata <= vprdata;
+ ahbso.hirq <= virq;
+ ahbso.hrdata <= kready & "00000000000000000000000" & r.hreg.hdata;
+ startgen <= vstartgen;
+ kstrobe <= r.hreg.written;
+ kdata <= r.hreg.hdata;
+ xmcumax <= r.preg.xmcumax;
+ ymcumax <= r.preg.ymcumax;
+ incaddy <= r.preg.incaddy;
+ incaddmcux <= r.preg.incaddmcux;
+ incaddmcuy <= r.preg.incaddmcuy;
+ fbstartadd <= r.preg.fbstartadd;
+ samp_fact <= r.preg.sampf;
+end process;
+
+ apbo.pirq <= (others => '0');
+ apbo.pindex <= pindex;
+ apbo.pconfig <= pconfig;
+ ahbso.hconfig <= shconfig;
+ ahbso.hresp <= "00";
+ ahbso.hsplit <= (others => '0');
+ ahbso.hcache <= '0';
+ ahbso.hready <= '1';
+ ahbso.hindex <= shindex;
+
+-- registers
+reg : process(clk)
+begin
+ if rising_edge(clk) then
+ r <= rin;
+ end if;
+end process;
+
+
+end;
+
--- /dev/null
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+library grlib;
+use grlib.amba.all;
+use grlib.stdlib.all;
+use grlib.devices.all;
+
+library techmap;
+use techmap.gencomp.all;
+
+entity yccambaif is
+ generic (
+ memtech : integer := DEFMEMTECH;
+ shindex : integer := 0;
+ haddr : integer := 0;
+ hmask : integer := 16#fff#;
+ hirq : integer := 0;
+ pindex : integer := 0;
+ paddr : integer := 0;
+ pmask : integer := 16#fff#);
+ port (
+ rst : in std_ulogic;
+ clk : in std_ulogic;
+ ahbsi : in ahb_slv_in_type;
+ ahbso : out ahb_slv_out_type;
+ apbi : in apb_slv_in_type;
+ apbo : out apb_slv_out_type;
+ kready : in std_logic;
+ kstrobe : out std_logic;
+ kdata : out std_logic_vector(7 downto 0);
+ samp_fact : out std_logic;
+ error : in std_logic;
+ xmcumax : out std_logic_vector(5 downto 0);
+ ymcumax : out std_logic_vector(4 downto 0);
+ incaddy : out std_logic_vector(15 downto 0);
+ incaddmcux : out std_logic_vector(15 downto 0);
+ incaddmcuy : out std_logic_vector(10 downto 0);
+ fbstartadd : out std_logic_vector(31 downto 0);
+ startgen : out std_logic
+ );
+end;
+
+architecture rtl of yccambaif is
+
+constant shconfig : ahb_config_type := (
+ 0 => ahb_device_reg( VENDOR_CONTRIB, CONTRIB_CORE1, 0, 0, hirq),
+ 4 => ahb_membar(haddr, '0', '0', hmask),
+ others => zero32);
+
+constant pconfig : apb_config_type := (
+ 0 => ahb_device_reg( VENDOR_CONTRIB, CONTRIB_CORE1, 0, 0, 0),
+ 1 => apb_iobar(paddr, pmask));
+
+type ahbs_reg is record
+ get : std_logic;
+ hdata : std_logic_vector(7 downto 0);
+ written : std_ulogic;
+end record;
+
+type apbs_reg is record
+ sampf : std_logic;
+ xmcumax : std_logic_vector(5 downto 0);
+ ymcumax : std_logic_vector(4 downto 0);
+ incaddy : std_logic_vector(15 downto 0);
+ incaddmcux : std_logic_vector(15 downto 0);
+ incaddmcuy : std_logic_vector(10 downto 0);
+ fbstartadd : std_logic_vector(31 downto 0);
+ error_reg : std_logic_vector(2 downto 0);
+end record;
+
+type all_reg is record
+ hreg : ahbs_reg;
+ preg : apbs_reg;
+end record;
+
+
+
+signal r, rin : all_reg;
+
+begin
+comb : process (r, rst, ahbsi, apbi, kready, error)
+ variable v : all_reg;
+ variable apbwrite : std_logic;
+ variable vprdata : std_logic_vector(31 downto 0);
+ variable virq : std_logic_vector(NAHBIRQ-1 downto 0);
+ variable vstartgen : std_logic;
+ begin
+
+ v := r;
+ vprdata := (others => '0');
+ virq := (others => '0');
+ v.hreg.written := '0';
+ vstartgen := '0';
+
+-- apb controle part
+ apbwrite := apbi.psel(pindex) and apbi.pwrite and apbi.penable;
+ vprdata := (others => '0');
+ case apbi.paddr(5 downto 2) is
+ when "0000" =>
+ if apbwrite = '1' then
+ v.preg.fbstartadd := apbi.pwdata(31 downto 0);
+ end if;
+ vprdata := r.preg.fbstartadd(31 downto 0);
+ when "0001" =>
+ if apbwrite = '1' then
+ v.preg.sampf := apbi.pwdata(22);
+ v.preg.ymcumax := apbi.pwdata(21 downto 17);
+ v.preg.xmcumax := apbi.pwdata(16 downto 11);
+ v.preg.incaddmcuy := apbi.pwdata(10 downto 0);
+ end if;
+ vprdata := "0000000000" & r.preg.ymcumax & r.preg.xmcumax & r.preg.incaddmcuy;
+ when "0010" =>
+ if apbwrite = '1' then
+ v.preg.incaddy := apbi.pwdata(31 downto 16);
+ v.preg.incaddmcux := apbi.pwdata(15 downto 0);
+ end if;
+ vprdata := r.preg.incaddy & r.preg.incaddmcux;
+ when "0011" =>
+ if apbwrite = '1' then
+ if apbi.pwdata(31) = '1' then
+ vstartgen := '1';
+ end if;
+ v.preg.error_reg(2) := apbi.pwdata(31);
+ end if;
+ vprdata := r.preg.error_reg(2) & "00000000000000000000000000000" & r.preg.error_reg(1 downto 0);
+ when others =>
+ end case;
+
+
+ v.hreg.get := '0';
+-- ahb slave input part
+ if (ahbsi.hready = '1') and (ahbsi.hsel(shindex) = '1') then
+ if (ahbsi.haddr(15 downto 0) = "0000000000000000") and (ahbsi.hwrite = '1') and (ahbsi.htrans = HTRANS_NONSEQ) then
+ v.hreg.get := '1';
+ end if;
+ end if;
+ if r.hreg.get = '1' then
+ v.hreg.hdata(7 downto 0) := ahbsi.hwdata(7 downto 0);
+ v.hreg.written := '1';
+ end if;
+
+
+-- reset part
+ if rst = '0' then
+ v.hreg.hdata := (others => '0');
+ v.hreg.written := '0';
+ v.hreg.get := '0';
+ v.preg.xmcumax := (others => '0');
+ v.preg.ymcumax := (others => '0');
+ v.preg.incaddmcuy := (others => '0');
+ v.preg.error_reg := (others => '0');
+-- v.preg.startgen := '0';
+ end if;
+
+-- signal
+
+ rin <= v;
+ apbo.prdata <= vprdata;
+ ahbso.hirq <= virq;
+ ahbso.hrdata <= kready & "00000000000000000000000" & r.hreg.hdata;
+ startgen <= vstartgen;
+ kstrobe <= r.hreg.written;
+ kdata <= r.hreg.hdata;
+ xmcumax <= r.preg.xmcumax;
+ ymcumax <= r.preg.ymcumax;
+ incaddy <= r.preg.incaddy;
+ incaddmcux <= r.preg.incaddmcux;
+ incaddmcuy <= r.preg.incaddmcuy;
+ fbstartadd <= r.preg.fbstartadd;
+ samp_fact <= r.preg.sampf;
+end process;
+
+ apbo.pirq <= (others => '0');
+ apbo.pindex <= pindex;
+ apbo.pconfig <= pconfig;
+ ahbso.hconfig <= shconfig;
+ ahbso.hresp <= "00";
+ ahbso.hsplit <= (others => '0');
+ ahbso.hcache <= '0';
+ ahbso.hready <= '1';
+ ahbso.hindex <= shindex;
+
+-- registers
+reg : process(clk)
+begin
+ if rising_edge(clk) then
+ r <= rin;
+ end if;
+end process;
+
+
+end;
+
--- /dev/null
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+library grlib;
+--use grlib.amba.all;
+use grlib.stdlib.all;
+use grlib.devices.all;
+
+library techmap;
+use techmap.gencomp.all;
+
+entity yccmemcont is
+ generic (
+ memtech : integer := DEFMEMTECH);
+ port (
+ rst : in std_ulogic;
+ clk : in std_ulogic;
+ kready1 : out std_logic;
+ kstrobe1 : in std_logic;
+ kdata1 : in std_logic_vector(7 downto 0);
+ kready2 : in std_logic;
+ kstrobe2 : out std_logic;
+ kdata2 : out std_logic_vector(23 downto 0);
+ samp_fact : in std_logic;
+ error : out std_logic
+ );
+end;
+-- samp_fact = 0 -> 4:1:1
+-- samp_fact = 1 -> 4:2:2
+
+architecture rtl of yccmemcont is
+
+type sstate_type is (mem0, mem1);
+type mstate_type is (empty, writing, full, reading, standby);
+
+type control_reg is record
+ swf : sstate_type;
+ swb : sstate_type;
+ mem0state : mstate_type;
+ mem1state : mstate_type;
+ countf : std_logic_vector(8 downto 0);
+-- selectf : std_logic_vector(1 downto 0);
+ countb : std_logic_vector(7 downto 0);
+ stb2keep : std_logic;
+end record;
+
+signal r, rin : control_reg;
+signal y0address, y1address : std_logic_vector(7 downto 0);
+signal cb0address, cb1address, cr0address, cr1address : std_logic_vector(6 downto 0);
+signal y0datain, y1datain, cb0datain, cb1datain, cr0datain, cr1datain : std_logic_vector(7 downto 0);
+signal y0dataout, y1dataout, cb0dataout, cb1dataout, cr0dataout, cr1dataout : std_logic_vector(7 downto 0);
+signal y0enable, y1enable, cb0enable, cb1enable, cr0enable, cr1enable : std_logic;
+signal y0write, y1write, cb0write, cb1write, cr0write, cr1write : std_logic;
+
+begin
+yram0 : syncram generic map(tech => memtech, abits => 8, dbits => 8)
+ port map( clk, y0address, y0datain, y0dataout, y0enable, y0write);
+yram1 : syncram generic map(tech => memtech, abits => 8, dbits => 8)
+ port map( clk, y1address, y1datain, y1dataout, y1enable, y1write);
+cbram0 : syncram generic map(tech => memtech, abits => 7, dbits => 8)
+ port map( clk, cb0address, cb0datain, cb0dataout, cb0enable, cb0write);
+cbram1 : syncram generic map(tech => memtech, abits => 7, dbits => 8)
+ port map( clk, cb1address, cb1datain, cb1dataout, cb1enable, cb1write);
+crram0 : syncram generic map(tech => memtech, abits => 7, dbits => 8)
+ port map( clk, cr0address, cr0datain, cr0dataout, cr0enable, cr0write);
+crram1 : syncram generic map(tech => memtech, abits => 7, dbits => 8)
+ port map( clk, cr1address, cr1datain, cr1dataout, cr1enable, cr1write);
+
+
+comb : process (r, rst, kstrobe1, kdata1, kready2, samp_fact, y0dataout, y1dataout,
+ cb0dataout, cb1dataout, cr0dataout, cr1dataout)
+ variable v : control_reg;
+ variable vkready1 : std_logic;
+ variable verror : std_logic;
+ variable vy0address, vy1address : std_logic_vector(7 downto 0);
+ variable vcb0address, vcb1address, vcr0address, vcr1address : std_logic_vector(6 downto 0);
+ variable vy0enable, vy1enable, vcb0enable, vcb1enable, vcr0enable, vcr1enable : std_logic;
+ variable vy0write, vy1write, vcb0write, vcb1write, vcr0write, vcr1write : std_logic;
+ variable fcountup, bcountup : std_logic;
+ variable fcntint : integer;
+ variable vstrobe : std_logic;
+ variable outdata : std_logic_vector(23 downto 0);
+ begin
+
+ v := r;
+ verror := '0';
+ vy0enable := '0'; vy1enable := '0'; vcb0enable := '0'; vcb1enable := '0'; vcr0enable := '0'; vcr1enable := '0';
+ vy0write := '0'; vy1write := '0'; vcb0write := '0'; vcb1write := '0'; vcr0write := '0'; vcr1write := '0';
+ fcountup := '0'; bcountup := '0';
+ vy0address := (others => '0'); vy1address := (others => '0');
+ vcb0address := (others => '0'); vcb1address := (others => '0');
+ vcr0address := (others => '0'); vcr1address := (others => '0');
+
+ -- forward part
+ fcntint := to_integer(unsigned(r.countf));
+ if (kstrobe1 = '1') then
+ if ((r.swf = mem0 and (r.mem0state = full or r.mem0state = reading))or
+ (r.swf = mem1 and (r.mem1state = full or r.mem1state = reading)))then
+ verror := '1';
+ end if;
+ fcountup := '1';
+ if(r.swf = mem0) then
+ if(samp_fact = '0') then
+ if(fcntint < 256) then
+ vy0enable := '1';
+ vy0write := '1';
+ vy0address := r.countf(7 downto 0);
+ elsif(fcntint < 320) then
+ vcb0enable := '1';
+ vcb0write := '1';
+ vcb0address := r.countf(6 downto 0);
+ elsif(fcntint < 384) then
+ vcr0enable := '1';
+ vcr0write := '1';
+ vcr0address := '0' & r.countf(5 downto 0);
+ else
+ verror := '1';
+ end if;
+ else
+ if(fcntint < 256) then
+ vy0enable := '1';
+ vy0write := '1';
+ vy0address := r.countf(7 downto 0);
+ elsif(fcntint < 384) then
+ vcb0enable := '1';
+ vcb0write := '1';
+ vcb0address := r.countf(6 downto 0);
+ elsif(fcntint < 512) then
+ vcr0enable := '1';
+ vcr0write := '1';
+ vcr0address := r.countf(6 downto 0);
+ else
+ verror := '1';
+ end if;
+ end if;
+ else
+ if(samp_fact = '0') then
+ if(fcntint < 256) then
+ vy1enable := '1';
+ vy1write := '1';
+ vy1address := r.countf(7 downto 0);
+ elsif(fcntint < 320) then
+ vcb1enable := '1';
+ vcb1write := '1';
+ vcb1address := r.countf(6 downto 0);
+ elsif(fcntint < 384) then
+ vcr1enable := '1';
+ vcr1write := '1';
+ vcr1address := '0' & r.countf(5 downto 0);
+ else
+ verror := '1';
+ end if;
+ else
+ if(fcntint < 256) then
+ vy1enable := '1';
+ vy1write := '1';
+ vy1address := r.countf(7 downto 0);
+ elsif(fcntint < 384) then
+ vcb1enable := '1';
+ vcb1write := '1';
+ vcb1address := r.countf(6 downto 0);
+ elsif(fcntint < 512) then
+ vcr1enable := '1';
+ vcr1write := '1';
+ vcr1address := r.countf(6 downto 0);
+ else
+ verror := '1';
+ end if;
+ end if;
+ end if;
+ end if;
+
+ vkready1 := '0';
+ if (r.swf = mem0 and (r.mem0state = empty or r.mem0state = writing)) or (r.swf = mem1 and (r.mem1state = empty or r.mem1state = writing)) then
+ vkready1 := '1';
+ end if;
+
+ --backward part
+ v.stb2keep := '0';
+ if (kready2 = '1') then
+ if(r.swb = mem0 and (r.mem0state = full or r.mem0state = reading)) then
+ bcountup := '1';
+ v.stb2keep := '1';
+ vy0enable := '1';
+ vcb0enable := '1';
+ vcr0enable := '1';
+ vy0address := r.countb(7) & r.countb(3) & r.countb(6 downto 4) & r.countb(2 downto 0);
+ if(samp_fact = '0') then
+ vcb0address := '0' & r.countb(7 downto 5) & r.countb(3 downto 1);
+ vcr0address := '0' & r.countb(7 downto 5) & r.countb(3 downto 1);
+ else
+ vcb0address := r.countb(7 downto 1);
+ vcr0address := r.countb(7 downto 1);
+ end if;
+ elsif(r.swb = mem1 and (r.mem1state = full or r.mem1state = reading))then
+ bcountup := '1';
+ v.stb2keep := '1';
+ vy1enable := '1';
+ vcb1enable := '1';
+ vcr1enable := '1';
+ vy1address := r.countb(7) & r.countb(3) & r.countb(6 downto 4) & r.countb(2 downto 0);
+ if(samp_fact = '0') then
+ vcb1address := '0' & r.countb(7 downto 5) & r.countb(3 downto 1);
+ vcr1address := '0' & r.countb(7 downto 5) & r.countb(3 downto 1);
+ else
+ vcb1address := r.countb(7 downto 1);
+ vcr1address := r.countb(7 downto 1);
+ end if;
+ end if;
+ end if;
+
+ if(r.swb = mem0)then
+ outdata := y0dataout & cb0dataout & cr0dataout;
+ else
+ outdata := y1dataout & cb1dataout & cr1dataout;
+ end if;
+
+
+ --state-machine
+ --check empty case batting memory read write access
+
+
+ case r.mem0state is
+ when empty =>
+ if (r.swf = mem0 and fcountup = '1') then
+ v.mem0state := writing;
+ end if;
+ when writing =>
+ if ((samp_fact = '0' and fcntint = 383 and fcountup = '1')or(samp_fact = '1' and fcntint = 511 and fcountup = '1')) then
+ v.mem0state := full;
+ v.swf := mem1;
+ end if;
+ when full =>
+ if (r.swb = mem0 and kready2 = '1') then
+ v.mem0state := reading;
+ end if;
+ when reading =>
+ if (r.countb = "11111111") then
+ v.mem0state := standby;
+ end if;
+ when standby =>
+ v.swb := mem1;
+ v.mem0state := empty;
+ when others =>
+ end case;
+
+ case r.mem1state is
+ when empty =>
+ if (r.swf = mem1 and fcountup = '1') then
+ v.mem1state := writing;
+ end if;
+ when writing =>
+ if ((samp_fact = '0' and fcntint = 383 and fcountup = '1')or(samp_fact = '1' and fcntint = 511 and fcountup = '1')) then
+ v.mem1state := full;
+ v.swf := mem0;
+ end if;
+ when full =>
+ if (r.swb = mem1 and kready2 = '1') then
+ v.mem1state := reading;
+ end if;
+ when reading =>
+ if (r.countb = "11111111") then
+ v.mem1state := standby;
+ end if;
+ when standby =>
+ v.swb := mem0;
+ v.mem1state := empty;
+ when others =>
+ end case;
+
+-- counter
+ if(fcountup = '1') then
+ v.countf := r.countf + '1';
+ if (samp_fact = '0') and (fcntint = 383) then
+ v.countf := "000000000";
+ elsif (samp_fact = '1') and (fcntint = 511) then
+ v.countf := "000000000";
+ end if;
+ end if;
+ if (bcountup = '1') then
+ v.countb := r.countb + '1';
+ end if;
+
+-- reset part
+ if rst = '0' then
+ v.swf := mem0;
+ v.swb := mem0;
+ v.mem0state := empty;
+ v.mem1state := empty;
+ v.countf := (others => '0');
+ v.countb := (others => '0');
+ v.stb2keep := '0';
+ end if;
+
+-- signal
+
+ rin <= v;
+ kready1 <= vkready1;
+ kstrobe2 <= r.stb2keep;
+ kdata2 <= outdata;
+ error <= verror;
+ y0address <= vy0address;
+ y1address <= vy1address;
+ cb0address <= vcb0address;
+ cb1address <= vcb1address;
+ cr0address <= vcr0address;
+ cr1address <= vcr1address;
+ y0enable <= vy0enable;
+ y1enable <= vy1enable;
+ cb0enable <= vcb0enable;
+ cb1enable <= vcb1enable;
+ cr0enable <= vcr0enable;
+ cr1enable <= vcr1enable;
+ y0write <= vy0write;
+ y1write <= vy1write;
+ cb0write <= vcb0write;
+ cb1write <= vcb1write;
+ cr0write <= vcr0write;
+ cr1write <= vcr1write;
+
+end process;
+
+ y0datain <= kdata1;
+ y1datain <= kdata1;
+ cb0datain <= kdata1;
+ cb1datain <= kdata1;
+ cr0datain <= kdata1;
+ cr1datain <= kdata1;
+
+-- registers
+reg : process(clk)
+begin
+ if rising_edge(clk) then
+ r <= rin;
+ end if;
+end process;
+
+
+end;
+
\ No newline at end of file
--- /dev/null
+library ieee;\r
+use ieee.std_logic_1164.all;\r
+use ieee.numeric_std.all;\r
+\r
+library grlib;\r
+--use grlib.amba.all;\r
+use grlib.stdlib.all;\r
+use grlib.devices.all;\r
+\r
+library techmap;\r
+use techmap.gencomp.all;\r
+\r
+entity yccmemcont is\r
+ generic (\r
+ memtech : integer := DEFMEMTECH);\r
+ port (\r
+ rst : in std_ulogic;\r
+ clk : in std_ulogic;\r
+ kready1 : out std_logic;\r
+ kstrobe1 : in std_logic;\r
+ kdata1 : in std_logic_vector(7 downto 0);\r
+ kready2 : in std_logic;\r
+ kstrobe2 : out std_logic;\r
+ kdata2 : out std_logic_vector(23 downto 0);\r
+ samp_fact : in std_logic;\r
+ error : out std_logic\r
+ );\r
+end;\r
+-- samp_fact = 0 -> 4:1:1\r
+-- samp_fact = 1 -> 4:2:2\r
+\r
+\r
+architecture rtl of yccmemcont is\r
+\r
+function stdv2str(vec:std_logic_vector) return string is\r
+ variable str : string(vec'length downto 1);\r
+ begin\r
+ for i in vec'length-1 downto 0 loop\r
+ if(vec(i)='U') then\r
+ str(i+1) := 'U';\r
+ elsif(vec(i)='X') then\r
+ str(i+1) := 'X';\r
+ elsif(vec(i)='0') then\r
+ str(i+1) := '0';\r
+ elsif(vec(i)='1') then\r
+ str(i+1) := '1';\r
+ elsif(vec(i)='Z') then\r
+ str(i+1) := 'Z';\r
+ elsif(vec(i)='W') then\r
+ str(i+1) := 'W';\r
+ elsif(vec(i)='L') then\r
+ str(i+1) := 'L';\r
+ elsif(vec(i)='H') then\r
+ str(i+1) := 'H';\r
+ else\r
+ str(i+1) := '-';\r
+ end if;\r
+ end loop;\r
+ return str;\r
+end; \r
+ \r
+type sstate_type is (mem0, mem1);\r
+type mstate_type is (empty, writing, full, reading, standby);\r
+\r
+type control_reg is record\r
+ swf : sstate_type;\r
+ swb : sstate_type;\r
+ mem0state : mstate_type;\r
+ mem1state : mstate_type;\r
+ countf : std_logic_vector(8 downto 0);\r
+-- selectf : std_logic_vector(1 downto 0);\r
+ countb : std_logic_vector(7 downto 0);\r
+-- countby : std_logic_vector(7 downto 0);\r
+-- countbcb : std_logic_vector(7 downto 0);\r
+-- countbcr : std_logic_vector(7 downto 0);\r
+ stb2keep : std_logic;\r
+end record;\r
+\r
+signal r, rin : control_reg;\r
+signal y0address, y1address : std_logic_vector(7 downto 0);\r
+signal cb0address, cb1address, cr0address, cr1address : std_logic_vector(6 downto 0);\r
+signal y0datain, y1datain, cb0datain, cb1datain, cr0datain, cr1datain : std_logic_vector(7 downto 0);\r
+signal y0dataout, y1dataout, cb0dataout, cb1dataout, cr0dataout, cr1dataout : std_logic_vector(7 downto 0);\r
+signal y0enable, y1enable, cb0enable, cb1enable, cr0enable, cr1enable : std_logic;\r
+signal y0write, y1write, cb0write, cb1write, cr0write, cr1write : std_logic;\r
+\r
+begin\r
+yram0 : syncram generic map(tech => memtech, abits => 8, dbits => 8)\r
+ port map( clk, y0address, y0datain, y0dataout, y0enable, y0write);\r
+yram1 : syncram generic map(tech => memtech, abits => 8, dbits => 8)\r
+ port map( clk, y1address, y1datain, y1dataout, y1enable, y1write);\r
+cbram0 : syncram generic map(tech => memtech, abits => 7, dbits => 8)\r
+ port map( clk, cb0address, cb0datain, cb0dataout, cb0enable, cb0write);\r
+cbram1 : syncram generic map(tech => memtech, abits => 7, dbits => 8)\r
+ port map( clk, cb1address, cb1datain, cb1dataout, cb1enable, cb1write);\r
+crram0 : syncram generic map(tech => memtech, abits => 7, dbits => 8)\r
+ port map( clk, cr0address, cr0datain, cr0dataout, cr0enable, cr0write);\r
+crram1 : syncram generic map(tech => memtech, abits => 7, dbits => 8)\r
+ port map( clk, cr1address, cr1datain, cr1dataout, cr1enable, cr1write); \r
+ \r
+ \r
+comb : process (r, rst, kstrobe1, kdata1, kready2, samp_fact, y0dataout, y1dataout, \r
+ cb0dataout, cb1dataout, cr0dataout, cr1dataout)\r
+ variable v : control_reg; \r
+ variable vkready1 : std_logic;\r
+ variable verror : std_logic;\r
+ variable vy0address, vy1address : std_logic_vector(7 downto 0);\r
+ variable vcb0address, vcb1address, vcr0address, vcr1address : std_logic_vector(6 downto 0);\r
+-- variable vy0datain, vy1datain, vcb0datain, vcb1datain, vcr0datain, vcr1datain \r
+-- : std_logic_vector(7 downto 0);\r
+ variable vy0enable, vy1enable, vcb0enable, vcb1enable, vcr0enable, vcr1enable \r
+ : std_logic;\r
+ variable vy0write, vy1write, vcb0write, vcb1write, vcr0write, vcr1write : std_logic;\r
+ variable fcountup, bcountup : std_logic;\r
+ variable fcntint : integer;\r
+ variable vstrobe : std_logic;\r
+ variable outdata : std_logic_vector(23 downto 0);\r
+ begin\r
+\r
+ v := r;\r
+ verror := '0';\r
+ vy0enable := '0'; vy1enable := '0'; vcb0enable := '0'; vcb1enable := '0'; vcr0enable := '0'; vcr1enable := '0';\r
+ vy0write := '0'; vy1write := '0'; vcb0write := '0'; vcb1write := '0'; vcr0write := '0'; vcr1write := '0';\r
+ fcountup := '0'; bcountup := '0';\r
+ vy0address := (others => '0'); vy1address := (others => '0'); \r
+ vcb0address := (others => '0'); vcb1address := (others => '0');\r
+ vcr0address := (others => '0'); vcr1address := (others => '0');\r
+ \r
+ -- forward part\r
+ fcntint := to_integer(unsigned(r.countf));\r
+ if (kstrobe1 = '1') then\r
+ if ((r.swf = mem0 and (r.mem0state = full or r.mem0state = reading))or\r
+ (r.swf = mem1 and (r.mem1state = full or r.mem1state = reading)))then\r
+ verror := '1'; \r
+ end if;\r
+ fcountup := '1';\r
+ if(r.swf = mem0) then\r
+ if(samp_fact = '0') then\r
+ if(fcntint < 256) then\r
+ vy0enable := '1';\r
+ vy0write := '1';\r
+ vy0address := r.countf(7 downto 0);\r
+ elsif(fcntint < 320) then\r
+ vcb0enable := '1';\r
+ vcb0write := '1';\r
+ vcb0address := r.countf(6 downto 0);\r
+ elsif(fcntint < 384) then\r
+ vcr0enable := '1';\r
+ vcr0write := '1';\r
+ vcr0address := '0' & r.countf(5 downto 0);\r
+ else\r
+ verror := '1';\r
+ end if;\r
+ else\r
+ if(fcntint < 256) then\r
+ vy0enable := '1';\r
+ vy0write := '1';\r
+ vy0address := r.countf(7 downto 0);\r
+ elsif(fcntint < 384) then\r
+ vcb0enable := '1';\r
+ vcb0write := '1';\r
+ vcb0address := r.countf(6 downto 0);\r
+ elsif(fcntint < 512) then\r
+ vcr0enable := '1';\r
+ vcr0write := '1';\r
+ vcr0address := r.countf(6 downto 0);\r
+ else\r
+ verror := '1';\r
+ end if; \r
+ end if;\r
+ else\r
+ if(samp_fact = '0') then\r
+ if(fcntint < 256) then\r
+ vy1enable := '1';\r
+ vy1write := '1';\r
+ vy1address := r.countf(7 downto 0);\r
+ elsif(fcntint < 320) then\r
+ vcb1enable := '1';\r
+ vcb1write := '1';\r
+ vcb1address := r.countf(6 downto 0);\r
+ elsif(fcntint < 384) then\r
+ vcr1enable := '1';\r
+ vcr1write := '1';\r
+ vcr1address := '0' & r.countf(5 downto 0);\r
+ else\r
+ verror := '1';\r
+ end if;\r
+ else\r
+ if(fcntint < 256) then\r
+ vy1enable := '1';\r
+ vy1write := '1';\r
+ vy1address := r.countf(7 downto 0);\r
+ elsif(fcntint < 384) then\r
+ vcb1enable := '1';\r
+ vcb1write := '1';\r
+ vcb1address := r.countf(6 downto 0);\r
+ elsif(fcntint < 512) then\r
+ vcr1enable := '1';\r
+ vcr1write := '1';\r
+ vcr1address := r.countf(6 downto 0);\r
+ else\r
+ verror := '1';\r
+ end if; \r
+ end if;\r
+ end if; \r
+ end if;\r
+ \r
+ vkready1 := '0';\r
+ if (r.swf = mem0 and (r.mem0state = empty or r.mem0state = writing)) or (r.swf = mem1 and (r.mem1state = empty or r.mem1state = writing)) then\r
+ vkready1 := '1';\r
+ end if;\r
+ \r
+ --backward part\r
+ v.stb2keep := '0'; \r
+ if (kready2 = '1') then\r
+ if(r.swb = mem0 and (r.mem0state = full or r.mem0state = reading)) then\r
+ bcountup := '1';\r
+ v.stb2keep := '1';\r
+ vy0enable := '1'; \r
+ vcb0enable := '1';\r
+ vcr0enable := '1';\r
+ vy0address := r.countb(7) & r.countb(3) & r.countb(6 downto 4) & r.countb(2 downto 0);\r
+ if(samp_fact = '0') then \r
+ vcb0address := '0' & r.countb(7 downto 5) & r.countb(3 downto 1);\r
+ vcr0address := '0' & r.countb(7 downto 5) & r.countb(3 downto 1);\r
+ else\r
+ vcb0address := r.countb(7 downto 1); \r
+ vcr0address := r.countb(7 downto 1);\r
+ end if;\r
+ elsif(r.swb = mem1 and (r.mem1state = full or r.mem1state = reading))then\r
+ bcountup := '1';\r
+ v.stb2keep := '1';\r
+ vy1enable := '1';\r
+ vcb1enable := '1';\r
+ vcr1enable := '1';\r
+ vy1address := r.countb(7) & r.countb(3) & r.countb(6 downto 4) & r.countb(2 downto 0);\r
+ if(samp_fact = '0') then \r
+ vcb1address := '0' & r.countb(7 downto 5) & r.countb(3 downto 1);\r
+ vcr1address := '0' & r.countb(7 downto 5) & r.countb(3 downto 1);\r
+ else\r
+ vcb1address := r.countb(7 downto 1); \r
+ vcr1address := r.countb(7 downto 1);\r
+ end if;\r
+ end if;\r
+ end if;\r
+ \r
+ if(r.swb = mem0)then\r
+ outdata := y0dataout & cb0dataout & cr0dataout;\r
+ else\r
+ outdata := y1dataout & cb1dataout & cr1dataout;\r
+ end if;\r
+ \r
+ \r
+ --state-machine\r
+ --check empty case batting memory read write access\r
+ \r
+\r
+ case r.mem0state is\r
+ when empty =>\r
+ if (r.swf = mem0 and fcountup = '1') then\r
+ v.mem0state := writing;\r
+ end if;\r
+ when writing =>\r
+ if ((samp_fact = '0' and fcntint = 383 and fcountup = '1')or(samp_fact = '1' and fcntint = 511 and fcountup = '1')) then\r
+ v.mem0state := full; \r
+ v.swf := mem1;\r
+ end if;\r
+ when full => \r
+ if (r.swb = mem0 and kready2 = '1') then\r
+ v.mem0state := reading;\r
+ end if;\r
+ when reading =>\r
+ if (r.countb = "11111111") then\r
+ v.mem0state := standby;\r
+ end if;\r
+ when standby => \r
+ v.swb := mem1;\r
+ v.mem0state := empty;\r
+ when others =>\r
+ end case;\r
+ \r
+ case r.mem1state is\r
+ when empty =>\r
+ if (r.swf = mem1 and fcountup = '1') then\r
+ v.mem1state := writing;\r
+ end if;\r
+ when writing =>\r
+ if ((samp_fact = '0' and fcntint = 383 and fcountup = '1')or(samp_fact = '1' and fcntint = 511 and fcountup = '1')) then\r
+ v.mem1state := full; \r
+ v.swf := mem0;\r
+ end if;\r
+ when full => \r
+ if (r.swb = mem1 and kready2 = '1') then\r
+ v.mem1state := reading;\r
+ end if;\r
+ when reading =>\r
+ if (r.countb = "11111111") then\r
+ v.mem1state := standby;\r
+ end if;\r
+ when standby =>\r
+ v.swb := mem0;\r
+ v.mem1state := empty;\r
+ when others =>\r
+ end case; \r
+\r
+-- counter\r
+ if(fcountup = '1') then\r
+ v.countf := r.countf + '1';\r
+ if (samp_fact = '0') and (fcntint = 383) then\r
+ v.countf := "000000000";\r
+ elsif (samp_fact = '1') and (fcntint = 511) then\r
+ v.countf := "000000000";\r
+ end if; \r
+ end if;\r
+ if (bcountup = '1') then\r
+ v.countb := r.countb + '1';\r
+ end if;\r
+ \r
+-- reset part\r
+ if rst = '0' then\r
+ v.swf := mem0;\r
+ v.swb := mem0;\r
+ v.mem0state := empty;\r
+ v.mem1state := empty;\r
+ v.countf := (others => '0');\r
+ v.countb := (others => '0');\r
+ v.stb2keep := '0';\r
+ end if;\r
+ \r
+-- signal\r
+\r
+ rin <= v; \r
+ kready1 <= vkready1;\r
+ kstrobe2 <= r.stb2keep;\r
+ kdata2 <= outdata;\r
+ error <= verror;\r
+ y0address <= vy0address;\r
+ y1address <= vy1address;\r
+ cb0address <= vcb0address;\r
+ cb1address <= vcb1address;\r
+ cr0address <= vcr0address;\r
+ cr1address <= vcr1address;\r
+ y0enable <= vy0enable;\r
+ y1enable <= vy1enable;\r
+ cb0enable <= vcb0enable;\r
+ cb1enable <= vcb1enable;\r
+ cr0enable <= vcr0enable;\r
+ cr1enable <= vcr1enable;\r
+ y0write <= vy0write;\r
+ y1write <= vy1write;\r
+ cb0write <= vcb0write;\r
+ cb1write <= vcb1write;\r
+ cr0write <= vcr0write;\r
+ cr1write <= vcr1write;\r
+ \r
+end process;\r
+\r
+ y0datain <= kdata1;\r
+ y1datain <= kdata1;\r
+ cb0datain <= kdata1;\r
+ cb1datain <= kdata1;\r
+ cr0datain <= kdata1;\r
+ cr1datain <= kdata1;\r
+ \r
+-- registers \r
+reg : process(clk)\r
+begin\r
+ if rising_edge(clk) then\r
+ r <= rin;\r
+ end if;\r
+end process;\r
+\r
+\r
+end;\r
+
\ No newline at end of file
--- /dev/null
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+library grlib;
+use grlib.amba.all;
+use grlib.stdlib.all;
+use grlib.devices.all;
+
+library techmap;
+use techmap.gencomp.all;
+
+entity yccrgb is
+ generic (
+ memtech : integer := DEFMEMTECH;
+ hirq : integer := 0;
+ mhindex : integer := 0;
+ chprot : integer := 3);
+ port (
+ rst : in std_ulogic;
+ clk : in std_ulogic;
+ ahbmi : in ahb_mst_in_type;
+ ahbmo : out ahb_mst_out_type;
+ kready : out std_logic;
+ kstrobe : in std_logic;
+ kdata : in std_logic_vector(23 downto 0);
+ xmcumax : in std_logic_vector(5 downto 0);
+ ymcumax : in std_logic_vector(4 downto 0);
+ incaddy : in std_logic_vector(15 downto 0);
+ incaddmcux : in std_logic_vector(15 downto 0);
+ incaddmcuy : in std_logic_vector(10 downto 0);
+ fbstartadd : in std_logic_vector(31 downto 0);
+ startgen : in std_logic
+ );
+end;
+
+architecture rtl of yccrgb is
+
+constant mhconfig : ahb_config_type := (
+ 0 => ahb_device_reg( VENDOR_CONTRIB, CONTRIB_CORE1, 0, 0, 0),
+ others => zero32);
+
+constant fdepth : integer :=256;
+
+function mysigned_mul(a,b : std_logic_vector) return std_logic_vector is
+variable z : std_logic_vector(a'length + b'length -1 downto 0);
+begin
+ z := std_logic_vector(signed(a) * signed(b));
+ return(z);
+end;
+
+function mysigned_add(a,b : std_logic_vector) return std_logic_vector is
+variable ex_a : std_logic_vector(a'length downto 0);
+variable ex_b : std_logic_vector(b'length downto 0);
+variable z1 : std_logic_vector(a'length downto 0);
+variable z2 : std_logic_vector(b'length downto 0);
+begin
+ ex_a := a(a'left) & a;
+ ex_b := b(b'left) & b;
+ if( a'length > b'length)then
+ z1 := std_logic_vector(signed(ex_a) + signed(ex_b));
+ return(z1);
+ else
+ z2 := std_logic_vector(signed(ex_a) + signed(ex_b));
+ return(z2);
+ end if;
+end;
+
+type fstate_type is (ready, stuck);
+type mstate_type is (idle, busreq, grant, nonseq, seq);
+
+type control_reg is record
+ ycc : std_logic_vector(23 downto 0);
+ written : std_ulogic;
+ fifo_state : fstate_type;
+ fifo_rp : std_logic_vector(7 downto 0);
+ fifo_wp : std_logic_vector(7 downto 0);
+ gen_add : std_logic_vector(31 downto 0);
+ temp_data : std_logic_vector(15 downto 0);
+ mstate : mstate_type;
+ yxpoint : std_logic_vector( 6 downto 0);
+ xmcu : std_logic_vector(5 downto 0);
+ ymcu : std_logic_vector(4 downto 0);
+ keep_data : std_logic_vector(31 downto 0);
+ dhready : std_logic;
+end record;
+
+signal r, rin : control_reg;
+signal read_en_fifo, write_en_fifo : std_logic;
+signal read_pointer_fifo : std_logic_vector(7 downto 0);
+signal write_pointer_fifo : std_logic_vector(7 downto 0);
+signal data_out_fifo : std_logic_vector(31 downto 0);
+signal data_in_fifo : std_logic_vector(31 downto 0);
+
+begin
+ram0 : syncram_2p generic map(tech => memtech, abits => 8, dbits => 32, sepclk => 0)
+ port map( clk, read_en_fifo, read_pointer_fifo, data_out_fifo,
+ clk, write_en_fifo, write_pointer_fifo, data_in_fifo);
+
+comb : process (r, rst, ahbmi, kstrobe, kdata, xmcumax, ymcumax, incaddmcuy, fbstartadd, startgen, data_out_fifo)
+ variable v : control_reg;
+ variable virq : std_logic_vector(NAHBIRQ-1 downto 0);
+ variable vsready : std_logic;
+ variable fifo_write : std_logic;
+ variable fifo_read :std_logic;
+ variable write_point : integer;
+ variable read_point : integer;
+ variable num_ele : integer;
+ variable mhtrans : std_logic_vector(1 downto 0);
+ variable mhbusreq : std_ulogic;
+ variable mhprot : std_logic_vector(3 downto 0);
+ variable add_inc : std_logic;
+ variable vmhwdata : std_logic_vector(31 downto 0);
+ variable incval : std_logic_vector(15 downto 0);
+ variable refresh : std_logic;
+ variable rout : std_logic_vector(4 downto 0);
+ variable gout : std_logic_vector(5 downto 0);
+ variable bout : std_logic_vector(4 downto 0);
+ variable node1 : std_logic_vector(9 downto 0);
+ variable node2 : std_logic_vector(9 downto 0);
+ variable node3 : std_logic_vector(15 downto 0);
+ variable node4 : std_logic_vector(15 downto 0);
+ variable node5 : std_logic_vector(15 downto 0);
+ variable node6 : std_logic_vector(15 downto 0);
+ variable node7 : std_logic_vector(9 downto 0);
+ variable node8 : std_logic_vector(8 downto 0);
+ variable node9 : std_logic_vector(9 downto 0);
+ variable node10 : std_logic_vector(9 downto 0);
+ constant c_01011010 : std_logic_vector(7 downto 0) := "01011010";
+ constant c_11101010 : std_logic_vector(7 downto 0) := "11101010";
+ constant c_11010010 : std_logic_vector(7 downto 0) := "11010010";
+ constant c_01110001 : std_logic_vector(7 downto 0) := "01110001";
+ begin
+
+ v := r;
+ virq := (others => '0');
+ mhprot := conv_std_logic_vector(chprot,4);
+ v.written := '0';
+ fifo_write := '0';
+ vsready := '1';
+ mhbusreq := '0';
+ mhtrans := HTRANS_IDLE;
+
+ if kstrobe = '1' then
+ v.ycc(23 downto 0) := kdata;
+ v.written := '1';
+ end if;
+
+-- register write
+ node1 := mysigned_add(('0' & r.ycc(15 downto 8)), "110000000");
+ node2 := mysigned_add(('0' & r.ycc(7 downto 0)), "110000000");
+ node3 := mysigned_mul(c_01011010, node2(7 downto 0));
+ node4 := mysigned_mul(c_11101010, node1(7 downto 0));
+ node5 := mysigned_mul(c_11010010, node2(7 downto 0));
+ node6 := mysigned_mul(c_01110001, node1(7 downto 0));
+ node7 := mysigned_add(('0' & r.ycc(23 downto 16)), (node3(14 downto 7) & '0'));
+ node8 := mysigned_add((node4(13 downto 7) & '0'), (node5(13 downto 7) & '0'));
+ node9 := mysigned_add(('0' & r.ycc(23 downto 16)), ( node6(14 downto 7) & '0'));
+ node10 := mysigned_add(('0' & r.ycc(23 downto 16)), node8);
+ if(node7(9) = '1') then
+ rout := "00000";
+ elsif(node7(8) = '1') then
+ rout := "11111";
+ else
+ rout := node7(7 downto 3);
+ end if;
+
+ if(node10(9) = '1') then
+ gout := "000000";
+ elsif(node10(8) = '1') then
+ gout := "111111";
+ else
+ gout := node10(7 downto 2);
+ end if;
+
+ if(node9(9) = '1') then
+ bout := "00000";
+ elsif(node9(8) = '1') then
+ bout := "11111";
+ else
+ bout := node9(7 downto 3);
+ end if;
+
+-- Fifo part
+ write_point := to_integer(unsigned(r.fifo_wp));
+ read_point := to_integer(unsigned(r.fifo_rp));
+ if write_point >= read_point then
+ num_ele := write_point - read_point;
+ else
+ num_ele := fdepth - read_point + write_point;
+ end if;
+ if num_ele > fdepth/2 then
+ vsready := '0';
+ end if;
+ if (num_ele = fdepth/2) and ( r.written = '1' or r.fifo_state = stuck) then
+ vsready := '0';
+ end if;
+
+ case r.fifo_state is
+ when ready =>
+ if r.written = '1' then
+ v.temp_data := rout & gout & bout;
+ v.fifo_state := stuck;
+ end if;
+ when stuck =>
+ if r.written = '1' then
+ fifo_write := '1';
+ write_point := write_point + 1;
+ if write_point = fdepth then
+ write_point := 0;
+ end if;
+ v.fifo_state := ready;
+ end if;
+ end case;
+
+ data_in_fifo <= r.temp_data & rout & gout & bout;
+ write_en_fifo <= fifo_write;
+ v.fifo_wp := std_logic_vector(to_unsigned(write_point,8));
+
+-- AHB master part
+ fifo_read := '0';
+ add_inc := '0';
+
+ case r.mstate is
+ when idle =>
+ mhbusreq := '0';
+ mhtrans := HTRANS_IDLE;
+ if (num_ele >= 8) then
+ v.mstate := busreq;
+ end if;
+ when busreq =>
+ mhbusreq := '1';
+ mhtrans := HTRANS_NONSEQ;
+ if (ahbmi.hready = '1') and (ahbmi.hgrant(mhindex) = '1') then
+ v.mstate := nonseq;
+ end if;
+ when nonseq =>
+ mhbusreq := '1';
+ mhtrans := HTRANS_NONSEQ;
+ if ahbmi.hready = '1' then
+ fifo_read := '1';
+ add_inc := '1';
+ v.mstate := seq;
+ end if;
+ when seq =>
+ mhbusreq := '1';
+ mhtrans := HTRANS_SEQ;
+ if ahbmi.hready = '1' then
+ fifo_read := '1';
+ add_inc := '1';
+ if (r.yxpoint(2 downto 0) = "111") then
+ v.mstate := idle;
+ end if;
+ end if;
+ when others =>
+ end case;
+
+
+ refresh := '0';
+ incval := (others => '0');
+ if add_inc = '1' then
+ v.yxpoint := r.yxpoint + '1';
+ if r.yxpoint(2 downto 0) /= "111" then
+ incval := "0000000000000100";
+ else
+ if r.yxpoint(6 downto 3) /= "1111" then
+ incval := incaddy;
+ else
+ v.xmcu := r.xmcu + '1';
+ if r.xmcu /= xmcumax then
+ incval := incaddmcux;
+ else
+ v.xmcu := "000000";
+ v.ymcu := r.ymcu + '1';
+ if r.ymcu /= ymcumax then
+ incval := "00000" & incaddmcuy;
+ else
+ v.ymcu := "00000";
+ refresh := '1';
+ end if;
+ end if;
+ end if;
+ end if;
+ end if;
+
+ if refresh = '1' then
+ v.gen_add := fbstartadd;
+ else
+ v.gen_add := std_logic_vector(signed(r.gen_add) + signed(incval));
+ end if;
+
+ if fifo_read = '1' then
+ read_point := read_point + 1;
+ if read_point = fdepth then
+ read_point := 0;
+ end if;
+ end if;
+ v.fifo_rp := std_logic_vector(to_unsigned(read_point,8));
+
+-- for the hready assert
+ v.dhready := ahbmi.hready;
+ if (ahbmi.hready = '1') or (ahbmi.hgrant(mhindex) = '0') then
+ v.keep_data := data_out_fifo;
+ end if;
+ if (r.dhready = '0') and (ahbmi.hgrant(mhindex) = '1') then
+ vmhwdata := r.keep_data;
+ else
+ vmhwdata := data_out_fifo;
+ end if;
+
+-- soft reset
+ if startgen = '1' then
+ v.gen_add := fbstartadd;
+ v.written := '0';
+ v.fifo_state := ready;
+ v.fifo_rp := (others => '0');
+ v.fifo_wp := (others => '0');
+ v.mstate := idle;
+ v.yxpoint := (others => '0');
+ v.xmcu := (others => '0');
+ v.ymcu := (others => '0');
+ end if;
+-- reset part
+ if rst = '0' then
+ v.ycc := (others => '0');
+ v.written := '0';
+ v.fifo_state := ready;
+ v.fifo_rp := (others => '0');
+ v.fifo_wp := (others => '0');
+ v.mstate := idle;
+ v.yxpoint := (others => '0');
+ v.xmcu := (others => '0');
+ v.ymcu := (others => '0');
+ v.temp_data := (others => '0');
+ v.gen_add := (others => '0');
+ end if;
+
+-- signal
+ rin <= v;
+ kready <= vsready;
+ read_en_fifo <= '1';
+ write_pointer_fifo <= r.fifo_wp(7 downto 0);
+ read_pointer_fifo <= r.fifo_rp(7 downto 0);
+ ahbmo.haddr <= r.gen_add;
+ ahbmo.htrans <= mhtrans;
+ ahbmo.hbusreq <= mhbusreq;
+ ahbmo.hprot <= mhprot;
+ ahbmo.hwdata <= vmhwdata;
+
+
+end process;
+
+ ahbmo.hconfig <= mhconfig;
+ ahbmo.hlock <= '0';
+ ahbmo.hwrite <= '1';
+ ahbmo.hsize <= "010";
+ ahbmo.hburst <= HBURST_INCR;
+ ahbmo.hirq <= (others => '0');
+ ahbmo.hindex <= mhindex;
+
+
+-- registers
+reg : process(clk)
+begin
+ if rising_edge(clk) then
+ r <= rin;
+ end if;
+end process;
+
+
+end;
+
--- /dev/null
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+library grlib;
+use grlib.amba.all;
+use grlib.stdlib.all;
+use grlib.devices.all;
+
+library techmap;
+use techmap.gencomp.all;
+
+entity yccrgb is
+ generic (
+ memtech : integer := DEFMEMTECH;
+ hirq : integer := 0;
+ mhindex : integer := 0;
+ chprot : integer := 3);
+ port (
+ rst : in std_ulogic;
+ clk : in std_ulogic;
+ ahbmi : in ahb_mst_in_type;
+ ahbmo : out ahb_mst_out_type;
+ kready : out std_logic;
+ kstrobe : in std_logic;
+ kdata : in std_logic_vector(23 downto 0);
+ xmcumax : in std_logic_vector(5 downto 0);
+ ymcumax : in std_logic_vector(4 downto 0);
+ incaddy : in std_logic_vector(15 downto 0);
+ incaddmcux : in std_logic_vector(15 downto 0);
+ incaddmcuy : in std_logic_vector(10 downto 0);
+ fbstartadd : in std_logic_vector(31 downto 0);
+ startgen : in std_logic
+ );
+end;
+
+architecture rtl of yccrgb is
+
+constant mhconfig : ahb_config_type := (
+ 0 => ahb_device_reg( VENDOR_CONTRIB, CONTRIB_CORE1, 0, 0, 0),
+ others => zero32);
+
+--constant incaddy : std_logic_vector(15 downto 0) := "0000010011100100";
+--constant incaddmcux : std_logic_vector(15 downto 0) := "1011010100000100";
+
+constant fdepth : integer :=256;
+
+function stdv2str(vec:std_logic_vector) return string is
+ variable str : string(vec'length downto 1);
+ begin
+ for i in vec'length-1 downto 0 loop
+ if(vec(i)='U') then
+ str(i+1) := 'U';
+ elsif(vec(i)='X') then
+ str(i+1) := 'X';
+ elsif(vec(i)='0') then
+ str(i+1) := '0';
+ elsif(vec(i)='1') then
+ str(i+1) := '1';
+ elsif(vec(i)='Z') then
+ str(i+1) := 'Z';
+ elsif(vec(i)='W') then
+ str(i+1) := 'W';
+ elsif(vec(i)='L') then
+ str(i+1) := 'L';
+ elsif(vec(i)='H') then
+ str(i+1) := 'H';
+ else
+ str(i+1) := '-';
+ end if;
+ end loop;
+ return str;
+end;
+
+function mysigned_mul(a,b : std_logic_vector) return std_logic_vector is
+variable z : std_logic_vector(a'length + b'length -1 downto 0);
+begin
+ z := std_logic_vector(signed(a) * signed(b));
+ return(z);
+end;
+
+function mysigned_add(a,b : std_logic_vector) return std_logic_vector is
+variable ex_a : std_logic_vector(a'length downto 0);
+variable ex_b : std_logic_vector(b'length downto 0);
+variable z1 : std_logic_vector(a'length downto 0);
+variable z2 : std_logic_vector(b'length downto 0);
+begin
+ ex_a := a(a'left) & a;
+ ex_b := b(b'left) & b;
+ if( a'length > b'length)then
+ z1 := std_logic_vector(signed(ex_a) + signed(ex_b));
+ return(z1);
+ else
+ z2 := std_logic_vector(signed(ex_a) + signed(ex_b));
+ return(z2);
+ end if;
+end;
+
+type fstate_type is (ready, stuck);
+type mstate_type is (idle, busreq, grant, nonseq, seq);
+
+type control_reg is record
+ ycc : std_logic_vector(23 downto 0);
+ written : std_ulogic;
+ fifo_state : fstate_type;
+ fifo_rp : std_logic_vector(7 downto 0);
+ fifo_wp : std_logic_vector(7 downto 0);
+ gen_add : std_logic_vector(31 downto 0);
+ temp_data : std_logic_vector(15 downto 0);
+ mstate : mstate_type;
+ yxpoint : std_logic_vector( 6 downto 0);
+ xmcu : std_logic_vector(5 downto 0);
+ ymcu : std_logic_vector(4 downto 0);
+ keep_data : std_logic_vector(31 downto 0);
+ dhready : std_logic;
+end record;
+
+signal r, rin : control_reg;
+signal read_en_fifo, write_en_fifo : std_logic;
+signal read_pointer_fifo : std_logic_vector(7 downto 0);
+signal write_pointer_fifo : std_logic_vector(7 downto 0);
+signal data_out_fifo : std_logic_vector(31 downto 0);
+signal data_in_fifo : std_logic_vector(31 downto 0);
+
+signal dbg_node1 : std_logic_vector(9 downto 0);
+signal dbg_node2 : std_logic_vector(9 downto 0);
+signal dbg_node3 : std_logic_vector(15 downto 0);
+signal dbg_node4 : std_logic_vector(15 downto 0);
+signal dbg_node5 : std_logic_vector(15 downto 0);
+signal dbg_node6 : std_logic_vector(15 downto 0);
+signal dbg_node7 : std_logic_vector(9 downto 0);
+signal dbg_node8 : std_logic_vector(8 downto 0);
+signal dbg_node9 : std_logic_vector(9 downto 0);
+signal dbg_node10 : std_logic_vector(9 downto 0);
+signal debug_numele : std_logic_vector(15 downto 0);
+
+begin
+ram0 : syncram_2p generic map(tech => memtech, abits => 8, dbits => 32, sepclk => 0)
+ port map( clk, read_en_fifo, read_pointer_fifo, data_out_fifo,
+ clk, write_en_fifo, write_pointer_fifo, data_in_fifo);
+
+comb : process (r, rst, ahbmi, kstrobe, kdata, xmcumax, ymcumax, incaddmcuy, fbstartadd, startgen, data_out_fifo)
+ variable v : control_reg;
+ variable virq : std_logic_vector(NAHBIRQ-1 downto 0);
+ variable vsready : std_logic;
+ variable fifo_write : std_logic;
+ variable fifo_read :std_logic;
+ variable write_point : integer;
+ variable read_point : integer;
+ variable num_ele : integer;
+ variable mhtrans : std_logic_vector(1 downto 0);
+ variable mhbusreq : std_ulogic;
+ variable mhprot : std_logic_vector(3 downto 0);
+ variable add_inc : std_logic;
+ variable vmhwdata : std_logic_vector(31 downto 0);
+ variable incval : std_logic_vector(15 downto 0);
+ variable refresh : std_logic;
+ variable rout : std_logic_vector(4 downto 0);
+ variable gout : std_logic_vector(5 downto 0);
+ variable bout : std_logic_vector(4 downto 0);
+ variable node1 : std_logic_vector(9 downto 0);
+ variable node2 : std_logic_vector(9 downto 0);
+ variable node3 : std_logic_vector(15 downto 0);
+ variable node4 : std_logic_vector(15 downto 0);
+ variable node5 : std_logic_vector(15 downto 0);
+ variable node6 : std_logic_vector(15 downto 0);
+ variable node7 : std_logic_vector(9 downto 0);
+ variable node8 : std_logic_vector(8 downto 0);
+ variable node9 : std_logic_vector(9 downto 0);
+ variable node10 : std_logic_vector(9 downto 0);
+ constant c_01011010 : std_logic_vector(7 downto 0) := "01011010";
+ constant c_11101010 : std_logic_vector(7 downto 0) := "11101010";
+ constant c_11010010 : std_logic_vector(7 downto 0) := "11010010";
+ constant c_01110001 : std_logic_vector(7 downto 0) := "01110001";
+ begin
+
+ v := r;
+ virq := (others => '0');
+ mhprot := conv_std_logic_vector(chprot,4);
+ v.written := '0';
+ fifo_write := '0';
+ vsready := '1';
+ mhbusreq := '0';
+ mhtrans := HTRANS_IDLE;
+
+ if kstrobe = '1' then
+ v.ycc(23 downto 0) := kdata;
+ v.written := '1';
+ end if;
+
+-- register write
+-- yc_datapath(r.ycc(23 downto 16), r.ycc(15 downto 8),r.ycc(7 downto 0), red,green,blue);
+ node1 := mysigned_add(('0' & r.ycc(15 downto 8)), "110000000");
+ node2 := mysigned_add(('0' & r.ycc(7 downto 0)), "110000000");
+ node3 := mysigned_mul(c_01011010, node2(7 downto 0));
+ node4 := mysigned_mul(c_11101010, node1(7 downto 0));
+ node5 := mysigned_mul(c_11010010, node2(7 downto 0));
+ node6 := mysigned_mul(c_01110001, node1(7 downto 0));
+ node7 := mysigned_add(('0' & r.ycc(23 downto 16)), (node3(14 downto 7) & '0'));
+ node8 := mysigned_add((node4(13 downto 7) & '0'), (node5(13 downto 7) & '0'));
+ node9 := mysigned_add(('0' & r.ycc(23 downto 16)), ( node6(14 downto 7) & '0'));
+ node10 := mysigned_add(('0' & r.ycc(23 downto 16)), node8);
+ if(node7(9) = '1') then
+ rout := "00000";
+ elsif(node7(8) = '1') then
+ rout := "11111";
+ else
+ rout := node7(7 downto 3);
+ end if;
+
+ if(node10(9) = '1') then
+ gout := "000000";
+ elsif(node10(8) = '1') then
+ gout := "111111";
+ else
+ gout := node10(7 downto 2);
+ end if;
+
+ if(node9(9) = '1') then
+ bout := "00000";
+ elsif(node9(8) = '1') then
+ bout := "11111";
+ else
+ bout := node9(7 downto 3);
+ end if;
+
+-- Fifo part
+ write_point := to_integer(unsigned(r.fifo_wp));
+ read_point := to_integer(unsigned(r.fifo_rp));
+ if write_point >= read_point then
+ num_ele := write_point - read_point;
+ else
+ num_ele := fdepth - read_point + write_point;
+ end if;
+ if num_ele > fdepth/2 then
+ vsready := '0';
+ end if;
+ if (num_ele = fdepth/2) and ( r.written = '1' or r.fifo_state = stuck) then
+ vsready := '0';
+ end if;
+
+ case r.fifo_state is
+ when ready =>
+ if r.written = '1' then
+ v.temp_data := rout & gout & bout;
+ v.fifo_state := stuck;
+ end if;
+ when stuck =>
+ if r.written = '1' then
+ fifo_write := '1';
+ write_point := write_point + 1;
+ if write_point = fdepth then
+ write_point := 0;
+ end if;
+ v.fifo_state := ready;
+ end if;
+ end case;
+
+ data_in_fifo <= r.temp_data & rout & gout & bout;
+ write_en_fifo <= fifo_write;
+ v.fifo_wp := std_logic_vector(to_unsigned(write_point,8));
+ debug_numele <= std_logic_vector(to_unsigned(num_ele,16));
+
+-- AHB master part
+ fifo_read := '0';
+ add_inc := '0';
+
+ case r.mstate is
+ when idle =>
+ mhbusreq := '0';
+ mhtrans := HTRANS_IDLE;
+ if (num_ele >= 8) then
+ v.mstate := busreq;
+ end if;
+ when busreq =>
+ mhbusreq := '1';
+ mhtrans := HTRANS_NONSEQ;
+ if (ahbmi.hready = '1') and (ahbmi.hgrant(mhindex) = '1') then
+ v.mstate := nonseq;
+ end if;
+ when nonseq =>
+ mhbusreq := '1';
+ mhtrans := HTRANS_NONSEQ;
+ if ahbmi.hready = '1' then
+ fifo_read := '1';
+ add_inc := '1';
+ v.mstate := seq;
+ end if;
+ when seq =>
+ mhbusreq := '1';
+ mhtrans := HTRANS_SEQ;
+ if ahbmi.hready = '1' then
+ fifo_read := '1';
+ add_inc := '1';
+ if (r.yxpoint(2 downto 0) = "111") then
+ v.mstate := idle;
+ end if;
+ end if;
+ when others =>
+ end case;
+
+
+ refresh := '0';
+ incval := (others => '0');
+ if add_inc = '1' then
+ v.yxpoint := r.yxpoint + '1';
+ if r.yxpoint(2 downto 0) /= "111" then
+ incval := "0000000000000100";
+ else
+ if r.yxpoint(6 downto 3) /= "1111" then
+ incval := incaddy;
+ else
+ v.xmcu := r.xmcu + '1';
+ if r.xmcu /= xmcumax then
+ incval := incaddmcux;
+ else
+ v.xmcu := "000000";
+ v.ymcu := r.ymcu + '1';
+ if r.ymcu /= ymcumax then
+ incval := "00000" & incaddmcuy;
+ else
+ v.ymcu := "00000";
+ refresh := '1';
+ end if;
+ end if;
+ end if;
+ end if;
+ end if;
+
+
+ if refresh = '1' then
+ v.gen_add := fbstartadd;
+ else
+ v.gen_add := std_logic_vector(signed(r.gen_add) + signed(incval));
+ end if;
+
+
+ if fifo_read = '1' then
+ read_point := read_point + 1;
+ if read_point = fdepth then
+ read_point := 0;
+ end if;
+ end if;
+ v.fifo_rp := std_logic_vector(to_unsigned(read_point,8));
+
+-- for the hready assert
+ v.dhready := ahbmi.hready;
+ if (ahbmi.hready = '1') or (ahbmi.hgrant(mhindex) = '0') then
+ v.keep_data := data_out_fifo;
+ end if;
+ if (r.dhready = '0') and (ahbmi.hgrant(mhindex) = '1') then
+ vmhwdata := r.keep_data;
+ else
+ vmhwdata := data_out_fifo;
+ end if;
+
+-- soft reset
+ if startgen = '1' then
+ v.gen_add := fbstartadd;
+ v.written := '0';
+ v.fifo_state := ready;
+ v.fifo_rp := (others => '0');
+ v.fifo_wp := (others => '0');
+ v.mstate := idle;
+ v.yxpoint := (others => '0');
+ v.xmcu := (others => '0');
+ v.ymcu := (others => '0');
+ end if;
+-- reset part
+ if rst = '0' then
+ v.ycc := (others => '0');
+ v.written := '0';
+ v.fifo_state := ready;
+ v.fifo_rp := (others => '0');
+ v.fifo_wp := (others => '0');
+ v.mstate := idle;
+ v.yxpoint := (others => '0');
+ v.xmcu := (others => '0');
+ v.ymcu := (others => '0');
+ v.temp_data := (others => '0');
+ v.gen_add := (others => '0');
+ end if;
+
+-- signal
+
+ rin <= v;
+ kready <= vsready;
+ read_en_fifo <= '1';
+ write_pointer_fifo <= r.fifo_wp(7 downto 0);
+ read_pointer_fifo <= r.fifo_rp(7 downto 0);
+ ahbmo.haddr <= r.gen_add;
+ ahbmo.htrans <= mhtrans;
+ ahbmo.hbusreq <= mhbusreq;
+ ahbmo.hprot <= mhprot;
+ ahbmo.hwdata <= vmhwdata;
+
+
+ dbg_node1 <= node1;
+ dbg_node2 <= node2;
+ dbg_node3 <= node3;
+ dbg_node4 <= node4;
+ dbg_node5 <= node5;
+ dbg_node6 <= node6;
+ dbg_node7 <= node7;
+ dbg_node8 <= node8;
+ dbg_node9 <= node9;
+ dbg_node10 <= node10;
+
+
+
+end process;
+
+ ahbmo.hconfig <= mhconfig;
+ ahbmo.hlock <= '0';
+ ahbmo.hwrite <= '1';
+ ahbmo.hsize <= "010";
+ ahbmo.hburst <= HBURST_INCR;
+ ahbmo.hirq <= (others => '0');
+ ahbmo.hindex <= mhindex;
+
+
+-- registers
+reg : process(clk)
+begin
+ if rising_edge(clk) then
+ r <= rin;
+ end if;
+end process;
+
+
+end;
+
amba dsu3 greth_api grcan \
spictrl i2cmst misc spimctrl svgactrl apbps2 \
i2cslv i2c yccrgbs_connect yccrgbs_pic yccrgbs_connect_neek \
- yccrgbs_pic_neek $(EXTRA_PROGS)
+ yccrgbs_pic_neek upycc_connect upycc_pic upycc_connect_neek \
+ upycc_pic_neek $(EXTRA_PROGS)
OFILES = $(PROGS:%=%.o)
--- /dev/null
+../../../snapgear-2.6-p42/user/jpeg-6b-host/in_upycc.txt
\ No newline at end of file
--- /dev/null
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\ No newline at end of file
--- /dev/null
+#include "testmod.h"
+#include <stdio.h>
+
+// You must set the following AHB address according to your system
+// This sample address is for leon3-gr-xc3s-1500-mjpeg
+#define HSADDR 0xa0000000
+#define HPADDR 0x80000c00
+#define IOADDR 0x80000800
+
+static unsigned int indata[9][1024] =
+ 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+
+struct yrsreg {
+ volatile unsigned int fbadd;
+ volatile unsigned int sizeinfo;
+ volatile unsigned int incadd;
+ volatile unsigned int reset;
+}
+
+ upycc_connect(){
+ struct yrsreg *sreg = (struct yrsreg *) HPADDR;
+ volatile unsigned int *dataad = (unsigned int *)HSADDR;
+ unsigned int rdata;
+ volatile unsigned int *raddr;
+ int i,j;
+ unsigned int *allocadd;
+ volatile unsigned int *ioaddr = (unsigned int *)IOADDR;
+ unsigned int iodata;
+
+ allocadd = (unsigned int *)memalign(1024, 2*640*480);
+ if (allocadd == NULL) fail(0);
+
+ sreg->fbadd = (unsigned int) allocadd;
+ sreg->sizeinfo = 0x00082464;
+ sreg->incadd = 0x4e4b504;
+ sreg->reset = 0x0;
+ sreg->reset = 0xffffffff;
+
+ for(i=0;i<1024;i++){
+ *dataad = indata[0][i];
+ }
+
+ for(i=0; i<300; i++){}
+
+ raddr = allocadd;
+ *(ioaddr + 2) = 0xffffffff;
+ *(ioaddr + 3) = 0x00000000;
+ *(ioaddr + 1) = 0x0000aaaa;
+
+ for(i=0;i<40;i++){
+ rdata = *raddr;
+ iodata = (rdata & 0x0000ffff) | 0x00010000;
+ *(ioaddr + 1) = iodata;
+ *(ioaddr + 1) = 0x0000aaaa;
+ iodata = (rdata & 0xffff0000) >> 16;
+ iodata = iodata | 0x00010000;
+ // iodata = rdata;
+ *(ioaddr + 1) = iodata;
+ *(ioaddr + 1) = 0x0000aaaa;
+ raddr++;
+ }
+ }
--- /dev/null
+#include "testmod.h"
+#include <stdio.h>
+
+// You must set the following AHB address according to your system
+// This sample address is for NEEK
+#define HSADDR 0xb0000000
+#define HPADDR 0x80000700
+#define IOADDR 0x80000500
+
+static unsigned int indata[9][1024] =
+ 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+
+struct yrsreg {
+ volatile unsigned int fbadd;
+ volatile unsigned int sizeinfo;
+ volatile unsigned int incadd;
+ volatile unsigned int reset;
+}
+
+ upycc_connect_neek(){
+ struct yrsreg *sreg = (struct yrsreg *) HPADDR;
+ volatile unsigned int *dataad = (unsigned int *)HSADDR;
+ unsigned int rdata;
+ volatile unsigned int *raddr;
+ int i,j;
+ unsigned int *allocadd;
+ volatile unsigned int *ioaddr = (unsigned int *)IOADDR;
+ unsigned int iodata;
+
+ allocadd = (unsigned int *)memalign(1024, 2*640*480);
+ if (allocadd == NULL) fail(0);
+
+ sreg->fbadd = (unsigned int) allocadd;
+ sreg->sizeinfo = 0x00082464;
+ sreg->incadd = 0x0624a244;
+ sreg->reset = 0x0;
+ sreg->reset = 0xffffffff;
+
+ for(i=0;i<1024;i++){
+ *dataad = indata[0][i];
+ }
+
+ for(i=0; i<300; i++){}
+
+ raddr = allocadd;
+ *(ioaddr + 2) = 0xffffffff;
+ *(ioaddr + 3) = 0x00000000;
+ *(ioaddr + 1) = 0x0000aaaa;
+
+ for(i=0;i<40;i++){
+ rdata = *raddr;
+ iodata = (rdata & 0x0000ffff) | 0x00010000;
+ *(ioaddr + 1) = iodata;
+ *(ioaddr + 1) = 0x0000aaaa;
+ iodata = (rdata & 0xffff0000) >> 16;
+ iodata = iodata | 0x00010000;
+ // iodata = rdata;
+ *(ioaddr + 1) = iodata;
+ *(ioaddr + 1) = 0x0000aaaa;
+ raddr++;
+ }
+ }
--- /dev/null
+#include "testmod.h"\r
+#include <stdio.h>\r
+\r
+// You must set the following AHB address according to your system\r
+// This sample address is for leon3-gr-xc3s-1500-mjpeg\r
+#define HSADDR 0xa0000000\r
+#define HPADDR 0x80000c00\r
+#define SVGAADDR 0x80000600\r
+\r
+static unsigned int indata[9][1024] = {\r
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+\r
+struct yrsreg {\r
+ volatile unsigned int fbadd;\r
+ volatile unsigned int size_info;\r
+ volatile unsigned int incadd;\r
+ volatile unsigned int reset;\r
+}\r
+\r
+ upycc_pic(){\r
+ struct yrsreg *sreg = (struct yrsreg *) HPADDR;\r
+ volatile unsigned int *dataad = (unsigned int *)HSADDR;\r
+ unsigned int rdata;\r
+ volatile unsigned int *raddr; \r
+ int i,j,k;\r
+ unsigned int *allocadd;\r
+ volatile unsigned int *svaddr = (unsigned int *)SVGAADDR;\r
+\r
+ allocadd = (unsigned int *)memalign(1024, 2*640*480);\r
+ if (allocadd == NULL) fail(0);\r
+\r
+ sreg->fbadd = (unsigned int) allocadd;\r
+ sreg->size_info = 0x00082464;\r
+ sreg->incadd = 0x4e4b504;\r
+ sreg->reset = 0x00000000;\r
+ sreg->reset = 0xffffffff;\r
+\r
+ /* For checking data*/\r
+\r
+ *(svaddr + 1) = 0x01df027f;\r
+ *(svaddr + 2) = 0x000b0010;\r
+ *(svaddr + 3) = 0x00020060;\r
+ *(svaddr + 4) = 0x020b031f;\r
+ *(svaddr + 5) = (unsigned int) allocadd;\r
+ *(svaddr + 6) = 0x00009c40;\r
+ *(svaddr + 7) = 0x000061a8;\r
+ *(svaddr + 8) = 0x00004e20;\r
+ *(svaddr + 9) = 0x00003c19;\r
+ *(svaddr + 10) = 0x00000000;\r
+\r
+ *svaddr = 0x00000021;\r
+ for(i=0;i<480;i++){\r
+ for(j=0;j<320;j++){\r
+ *(allocadd + i*320 +j) = 0x0;\r
+ }\r
+ }\r
+ for(i=0;i<9;i++){\r
+ for(j=0;j<1024;j++){\r
+ *dataad = indata[i][j];\r
+ // for(k=0;k<100000;k++);\r
+ }\r
+ }\r
+ }\r
+\r
+\r
+\r
+ \r
+\r
--- /dev/null
+#include "testmod.h"\r
+#include <stdio.h>\r
+\r
+// You must set the following AHB address according to your system\r
+// This sample address is for NEEK\r
+#define HSADDR 0xb0000000\r
+#define HPADDR 0x80000700\r
+#define SVGAADDR 0x80000b00\r
+\r
+static unsigned int indata[9][1024] = {\r
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3,0xD3,0xD5,0xD5,0xD2,0xCF,0xCD,0xD0,0xD2,0xD4,0xD5,0xD5,0xD1,0xCD,0xCB,0xCD,0xD0,0xD4,0xD5,0xD4,0xD0,0xCC,0xCA,0xCC,0xCF}};\r
+\r
+struct yrsreg {\r
+ volatile unsigned int fbadd;\r
+ volatile unsigned int size_info;\r
+ volatile unsigned int incadd;\r
+ volatile unsigned int reset;\r
+}\r
+\r
+ upycc_pic_neek(){\r
+ struct yrsreg *sreg = (struct yrsreg *) HPADDR;\r
+ volatile unsigned int *dataad = (unsigned int *)HSADDR;\r
+ unsigned int rdata;\r
+ volatile unsigned int *raddr; \r
+ int i,j,k;\r
+ unsigned int *allocadd;\r
+ volatile unsigned int *svaddr = (unsigned int *)SVGAADDR;\r
+\r
+ allocadd = (unsigned int *)memalign(1024, 2*800*480);\r
+ if (allocadd == NULL) fail(0);\r
+\r
+ sreg->fbadd = (unsigned int) allocadd;\r
+ sreg->size_info = 0x000825A4;\r
+ sreg->incadd = 0x0624a244;\r
+ sreg->reset = 0x00000000;\r
+ sreg->reset = 0xffffffff;\r
+\r
+ /* For checking data*/\r
+\r
+ *(svaddr + 1) = 0x01df027f;\r
+ *(svaddr + 2) = 0x000b0010;\r
+ *(svaddr + 3) = 0x00020060;\r
+ *(svaddr + 4) = 0x020b031f;\r
+ *(svaddr + 5) = (unsigned int) allocadd;\r
+ *(svaddr + 6) = 0x00009c40;\r
+ *(svaddr + 7) = 0x000061a8;\r
+ *(svaddr + 8) = 0x00004e20;\r
+ *(svaddr + 9) = 0x00003c19;\r
+ *(svaddr + 10) = 0x00000000;\r
+\r
+ *svaddr = 0x00000021;\r
+ for(i=0;i<480;i++){\r
+ for(j=0;j<400;j++){\r
+ *(allocadd + i*320 +j) = 0x0;\r
+ }\r
+ }\r
+ for(i=0;i<9;i++){\r
+ for(j=0;j<1024;j++){\r
+ *dataad = indata[i][j];\r
+ // for(k=0;k<100000;k++);\r
+ }\r
+ }\r
+ }\r
+\r
+\r
+\r
+ \r
+\r
#define APBADD 0x80000c00
-/* Physical address for NEEK
-#define AHBADD 0xb0000000
+/* Physical address for NEEK*/
+/*#define AHBADD 0xb0000000
#define RDYADD 0xb0000200
-#define APBADD 0x80000700
-*/
+#define APBADD 0x80000700*/
+
static struct kmjpeg_priv *kmjpeg_devices;
struct kmjpeg_sregs_t {
volatile unsigned int fbadd;
volatile unsigned int size_info;
- volatile unsigned int inc_add;
+ volatile unsigned int incadd;
volatile unsigned int reset;
};
if((tmp & 0x80000000) == 0x80000000)break;
for(i=0;i<800;i++);
}
- // *hdata = datawrite.pixeldata;
- for(i=0;i<128;i++){
- *hdata = datawrite.fourbdata[i];
- }
+ *hdata = datawrite.pixeldata;
+ // for(i=0;i<128;i++){
+ // *hdata = datawrite.fourbdata[i];
+ // }
break;
case IOCTL_REGSET :
// printk("IOCTL regset2 ..............................\n");
kmjpeg_sregs->fbadd = datareg.fb;
kmjpeg_sregs->size_info = datareg.size_info;
- kmjpeg_sregs->inc_add = datareg.inc_add;
+ kmjpeg_sregs->incadd = datareg.incadd;
kmjpeg_sregs->reset = 0x0;
kmjpeg_sregs->reset =0xffffffff;
iounmap(kmjpeg_sregs);
#include <linux/ioctl.h>
struct ioctl_cmdwrite{
- // unsigned int pixeldata;
- unsigned int fourbdata[128];
+ unsigned int pixeldata;
+ // unsigned int fourbdata[128];
};
struct ioctl_cmdreg{
unsigned int fb;
unsigned int size_info;
- unsigned int inc_add;
+ unsigned int incadd;
};
#define IOC_MAGIC 'k'
fprintf(stderr,"out_yccrgbs.txt File open error!\n");
exit(1);
}
+ if((cinfo->in_upycc = fopen("in_upycc.txt", "w"))==NULL){
+ fprintf(stderr,"in_upycc.txt File open error!\n");
+ exit(1);
+ }
+ if((cinfo->out_upycc = fopen("out_upycc.txt", "w"))==NULL){
+ fprintf(stderr,"out_upycc.txt File open error!\n");
+ exit(1);
+ }
}
--- /dev/null
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XDrawPoint(wininfo.dpy,wininfo.win,wininfo.gc,col,call_num);
if(call_flag ==0){
- fprintf(cinfo->out_yccrgbs,"%x",(unsigned short)pixcoldata);
+ fprintf(cinfo->out_upycc,"%x",(unsigned short)pixcoldata);
call_flag =1;
}else{
- fprintf(cinfo->out_yccrgbs,"%x\n",(unsigned short)pixcoldata);
+ fprintf(cinfo->out_upycc,"%x\n",(unsigned short)pixcoldata);
call_flag = 0;
}
}
#include "jinclude.h"
#include "jpeglib.h"
+#define HW_TEST_PT
/* Pointer to routine to upsample a single component */
typedef JMETHOD(void, upsample1_ptr,
JSAMPROW outend;
int inrow;
+
for (inrow = 0; inrow < cinfo->max_v_samp_factor; inrow++) {
inptr = input_data[inrow];
outptr = output_data[inrow];
register JDIMENSION colctr;
int inrow;
- for (inrow = 0; inrow < cinfo->max_v_samp_factor; inrow++) {
+ for (inrow = 0; inrow < cinfo->max_v_samp_factor; inrow++) {
inptr = input_data[inrow];
outptr = output_data[inrow];
/* Special case for first column */
register JDIMENSION colctr;
int inrow, outrow, v;
+ //printf("come here!");
+
+#ifdef HW_TEST_PT
+ register JSAMPROW inptr;
+ register JSAMPLE invalue;
+ JSAMPROW outend;
+
+ inrow = outrow = 0;
+ while (outrow < cinfo->max_v_samp_factor) {
+ inptr = input_data[inrow];
+ outptr = output_data[outrow];
+ outend = outptr + cinfo->output_width;
+ while (outptr < outend) {
+ invalue = *inptr++; /* don't need GETJSAMPLE() here */
+ *outptr++ = invalue;
+ *outptr++ = invalue;
+ }
+ jcopy_sample_rows(output_data, outrow, output_data, outrow+1,
+ 1, cinfo->output_width);
+ inrow++;
+ outrow += 2;
+ }
+#else
inrow = outrow = 0;
while (outrow < cinfo->max_v_samp_factor) {
for (v = 0; v < 2; v++) {
}
inrow++;
}
+#endif
}
+/* modified by Kenichi Kurimoto */
+
/*
* jidctint.c
*
outptr[7] = dcval;
wsptr += DCTSIZE; /* advance pointer to next row */
+
+
+ fprintf(cinfo->in_upycc,"%02X\n",outptr[0]);
+ fprintf(cinfo->in_upycc,"%02X\n",outptr[1]);
+ fprintf(cinfo->in_upycc,"%02X\n",outptr[2]);
+ fprintf(cinfo->in_upycc,"%02X\n",outptr[3]);
+ fprintf(cinfo->in_upycc,"%02X\n",outptr[4]);
+ fprintf(cinfo->in_upycc,"%02X\n",outptr[5]);
+ fprintf(cinfo->in_upycc,"%02X\n",outptr[6]);
+ fprintf(cinfo->in_upycc,"%02X\n",outptr[7]);
+
continue;
}
#endif
& RANGE_MASK];
wsptr += DCTSIZE; /* advance pointer to next row */
+
+ fprintf(cinfo->in_upycc,"%02X\n",outptr[0]);
+ fprintf(cinfo->in_upycc,"%02X\n",outptr[1]);
+ fprintf(cinfo->in_upycc,"%02X\n",outptr[2]);
+ fprintf(cinfo->in_upycc,"%02X\n",outptr[3]);
+ fprintf(cinfo->in_upycc,"%02X\n",outptr[4]);
+ fprintf(cinfo->in_upycc,"%02X\n",outptr[5]);
+ fprintf(cinfo->in_upycc,"%02X\n",outptr[6]);
+ fprintf(cinfo->in_upycc,"%02X\n",outptr[7]);
+
}
}
FILE *in_yccrgbs;
FILE *out_yccrgbs;
+ FILE *in_upycc;
+ FILE *out_upycc;
};
--- /dev/null
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#include <sys/time.h>
#include "kmjpeg.h"
static int f_num = 0;
-//#define DEBUG
+#define DEBUG
/*
// int xres,yres,vbpp,line_len,yfac;
long int screensize;
struct ioctl_cmdreg regset;
- unsigned int size,inc;
- int i;
+ unsigned int xmcumax,ymcumax,incaddmcuy,size, incaddy, incadd;
+ int i, j, samp_f, incaddmcux;
+ jpeg_component_info *compptr;
+ int h_samp[3];
+ int v_samp[3];
+ int qtbl_no[3];
+
/** V1 framebuffer & motionJPEG support **/
if(!(cinfo->fd_framebuffer = open( "/dev/fb0", O_RDWR))){
fprintf(stderr, "Framebuffer variable information get error\n");
exit(1);
}
-#ifdef DEBUG
+ //#ifdef DEBUG
fprintf(stderr, "Framebuffer xsize:%d, ysize:%d, vbpp:%d\n",
cinfo->fb_vinfo.xres, cinfo->fb_vinfo.yres, cinfo->fb_vinfo.bits_per_pixel);
-#endif
+ //#endif
if(cinfo->fb_vinfo.xres % 16 != 0 || cinfo->fb_vinfo.yres % 16 != 0){
fprintf(stderr, "This system support only multiple of 16 X,Y size Framebuffer.\n");
exit(1);
exit(1);
}
regset.fb = cinfo->fb_start_add;
- size = (unsigned int)((cinfo->image_width) <<16 | (unsigned int)(cinfo->image_height));
+ xmcumax = cinfo->image_width / 16 -1;
+ ymcumax = cinfo->image_height /16 -1;
+ incaddmcuy = (cinfo->fb_vinfo.xres - (xmcumax +1)*16 )* 2 + 4;
+
+#ifdef DEBUG
+ fprintf(stderr, "xmcumax = %d, ymcumax = %d, incaddmcuy = %x\n",xmcumax,ymcumax,incaddmcuy);
+#endif
+
+ compptr = cinfo->comp_info;
+ for(j=0;j<3;j++,compptr++){
+ h_samp[j] = compptr->h_samp_factor;
+ v_samp[j] = compptr->v_samp_factor;
+ qtbl_no[j] = compptr->quant_tbl_no;
+ printf("h_samp = %d, v_samp = %d, quant table no =%d\n", h_samp[j],v_samp[j],qtbl_no[j]);
+ }
+
+ if(!((h_samp[0] == 2) && (v_samp[0]==2))){
+ printf("this mjpeg file is not 4:1:1 4:2:2\n");
+ exit(1);
+ }
+ if((h_samp[1]==1) && (v_samp[1]==1) && (h_samp[2]==1) && (v_samp[2]==1)){
+ samp_f = 0;
+ printf("this mjpeg file is 4:1:1\n");
+ }else if((h_samp[1]==1) && (v_samp[1]==2) && (h_samp[2]==1) && (v_samp[2]==2)){
+ samp_f = 1;
+ printf("this mjpeg file is 4:2:2\n");
+ }else{
+ printf("this mjpeg file is not 4:1:1, 4:2:2\n");
+ exit(1);
+ }
+
+
+ size = (unsigned int) ((samp_f <<22) | (ymcumax <<17) | (xmcumax <<11) | incaddmcuy) ;
regset.size_info = size;
- inc = (unsigned int)(cinfo->fb_vinfo.xres - cinfo->image_width)*2;
- regset.inc_add = inc;
+
+ incaddy = cinfo->fb_vinfo.xres * 2 - 28;
+ incaddmcux = -1 *(15 * cinfo->fb_vinfo.xres * 2 - 4);
+
+ incadd = (unsigned int)((incaddy <<16) |(incaddmcux & 0x0000ffff));
+ regset.incadd = incadd;
+
#ifdef DEBUG
- printf(stderr, "ioctl fb_start_add = %x, size_info = %x, inc_add = %x\n");
+ fprintf(stderr, "ioctl fb_start_add = %x, size_info = %x, incadd = %x\n",regset.fb, regset.size_info, regset.incadd );
for(i=0;i<10000;i++);
#endif
+
ioctl(cinfo->dev_fd, IOCTL_REGSET, ®set);
}
#endif
fprintf(stderr, "Switches (names may be abbreviated):\n");
- fprintf(stderr, " -colors N Reduce image to no more than N colors\n");
- fprintf(stderr, " -fast Fast, low-quality processing\n");
- fprintf(stderr, " -grayscale Force grayscale output\n");
-#ifdef IDCT_SCALING_SUPPORTED
- fprintf(stderr, " -scale M/N Scale output image by fraction M/N, eg, 1/8\n");
-#endif
-#ifdef BMP_SUPPORTED
- fprintf(stderr, " -bmp Select BMP output format (Windows style)%s\n",
- (DEFAULT_FMT == FMT_BMP ? " (default)" : ""));
-#endif
-#ifdef GIF_SUPPORTED
- fprintf(stderr, " -gif Select GIF output format%s\n",
- (DEFAULT_FMT == FMT_GIF ? " (default)" : ""));
-#endif
-#ifdef BMP_SUPPORTED
- fprintf(stderr, " -os2 Select BMP output format (OS/2 style)%s\n",
- (DEFAULT_FMT == FMT_OS2 ? " (default)" : ""));
-#endif
-#ifdef PPM_SUPPORTED
- fprintf(stderr, " -pnm Select PBMPLUS (PPM/PGM) output format%s\n",
- (DEFAULT_FMT == FMT_PPM ? " (default)" : ""));
-#endif
-#ifdef RLE_SUPPORTED
- fprintf(stderr, " -rle Select Utah RLE output format%s\n",
- (DEFAULT_FMT == FMT_RLE ? " (default)" : ""));
-#endif
-#ifdef TARGA_SUPPORTED
- fprintf(stderr, " -targa Select Targa output format%s\n",
- (DEFAULT_FMT == FMT_TARGA ? " (default)" : ""));
-#endif
- fprintf(stderr, "Switches for advanced users:\n");
-#ifdef DCT_ISLOW_SUPPORTED
- fprintf(stderr, " -dct int Use integer DCT method%s\n",
- (JDCT_DEFAULT == JDCT_ISLOW ? " (default)" : ""));
-#endif
-#ifdef DCT_IFAST_SUPPORTED
- fprintf(stderr, " -dct fast Use fast integer DCT (less accurate)%s\n",
- (JDCT_DEFAULT == JDCT_IFAST ? " (default)" : ""));
-#endif
-#ifdef DCT_FLOAT_SUPPORTED
- fprintf(stderr, " -dct float Use floating-point DCT method%s\n",
- (JDCT_DEFAULT == JDCT_FLOAT ? " (default)" : ""));
-#endif
- fprintf(stderr, " -dither fs Use F-S dithering (default)\n");
- fprintf(stderr, " -dither none Don't use dithering in quantization\n");
- fprintf(stderr, " -dither ordered Use ordered dither (medium speed, quality)\n");
-#ifdef QUANT_2PASS_SUPPORTED
- fprintf(stderr, " -map FILE Map to colors used in named image file\n");
-#endif
- fprintf(stderr, " -nosmooth Don't use high-quality upsampling\n");
-#ifdef QUANT_1PASS_SUPPORTED
- fprintf(stderr, " -onepass Use 1-pass quantization (fast, low quality)\n");
-#endif
- fprintf(stderr, " -maxmemory N Maximum memory to use (in kbytes)\n");
- fprintf(stderr, " -outfile name Specify name for output file\n");
- fprintf(stderr, " -verbose or -debug Emit debug output\n");
+ fprintf(stderr, " -fb_add FramebufferAddress (Hexadecimal number of Framebuffer start address. ex:41a00000) \n");
+
+
exit(EXIT_FAILURE);
}
+/* modified by Kenichi Kurimoto */
+
/*
* jdcolor.c
*
*((unsigned int *)(cinfo->fbptr + location)) = pixcoldata;
}*/
/*LEON-motionJPEG prj for hard IP : yccrgbs*/
- pixcoldata =(unsigned int)( y <<16 | cb <<8 | cr);
+ /* pixcoldata =(unsigned int)( y <<16 | cb <<8 | cr);
writedata.fourbdata[pixel_num] = pixcoldata;
pixel_num++;
if(pixel_num == 128){
ioctl(cinfo->dev_fd, IOCTL_WRITE, &writedata);
pixel_num = 0;
- }
+ } */
outptr += RGB_PIXELSIZE;
}
}
+/* modified by Kenichi Kurimoto */
+
/*
* jdsample.c
*
register JDIMENSION colctr;
int inrow;
+ return;
+
for (inrow = 0; inrow < cinfo->max_v_samp_factor; inrow++) {
inptr = input_data[inrow];
outptr = output_data[inrow];
register JDIMENSION colctr;
int inrow, outrow, v;
+ return;
+
inrow = outrow = 0;
while (outrow < cinfo->max_v_samp_factor) {
for (v = 0; v < 2; v++) {
+/* modified by Kenichi Kurimoto */
+
/*
* jidctint.c
*
#ifdef DCT_ISLOW_SUPPORTED
+#include "kmjpeg.h"
/*
* This module is specialized to the case DCTSIZE = 8.
int workspace[DCTSIZE2]; /* buffers data between passes */
SHIFT_TEMPS
+ struct ioctl_cmdwrite writedata;
+
+
+
/* Pass 1: process columns from input, store into work array. */
/* Note results are scaled up by sqrt(8) compared to a true IDCT; */
/* furthermore, we scale the results by 2**PASS1_BITS. */
outptr[6] = dcval;
outptr[7] = dcval;
+ writedata.pixeldata = (unsigned int)outptr[0];
+ ioctl(cinfo->dev_fd, IOCTL_WRITE, &writedata);
+ writedata.pixeldata = (unsigned int)outptr[1];
+ ioctl(cinfo->dev_fd, IOCTL_WRITE, &writedata);
+ writedata.pixeldata = (unsigned int)outptr[2];
+ ioctl(cinfo->dev_fd, IOCTL_WRITE, &writedata);
+ writedata.pixeldata = (unsigned int)outptr[3];
+ ioctl(cinfo->dev_fd, IOCTL_WRITE, &writedata);
+ writedata.pixeldata = (unsigned int)outptr[4];
+ ioctl(cinfo->dev_fd, IOCTL_WRITE, &writedata);
+ writedata.pixeldata = (unsigned int)outptr[5];
+ ioctl(cinfo->dev_fd, IOCTL_WRITE, &writedata);
+ writedata.pixeldata = (unsigned int)outptr[6];
+ ioctl(cinfo->dev_fd, IOCTL_WRITE, &writedata);
+ writedata.pixeldata = (unsigned int)outptr[7];
+ ioctl(cinfo->dev_fd, IOCTL_WRITE, &writedata);
+
+
+
wsptr += DCTSIZE; /* advance pointer to next row */
continue;
}
CONST_BITS+PASS1_BITS+3)
& RANGE_MASK];
+ writedata.pixeldata = (unsigned int)outptr[0];
+ ioctl(cinfo->dev_fd, IOCTL_WRITE, &writedata);
+ writedata.pixeldata = (unsigned int)outptr[1];
+ ioctl(cinfo->dev_fd, IOCTL_WRITE, &writedata);
+ writedata.pixeldata = (unsigned int)outptr[2];
+ ioctl(cinfo->dev_fd, IOCTL_WRITE, &writedata);
+ writedata.pixeldata = (unsigned int)outptr[3];
+ ioctl(cinfo->dev_fd, IOCTL_WRITE, &writedata);
+ writedata.pixeldata = (unsigned int)outptr[4];
+ ioctl(cinfo->dev_fd, IOCTL_WRITE, &writedata);
+ writedata.pixeldata = (unsigned int)outptr[5];
+ ioctl(cinfo->dev_fd, IOCTL_WRITE, &writedata);
+ writedata.pixeldata = (unsigned int)outptr[6];
+ ioctl(cinfo->dev_fd, IOCTL_WRITE, &writedata);
+ writedata.pixeldata = (unsigned int)outptr[7];
+ ioctl(cinfo->dev_fd, IOCTL_WRITE, &writedata);
+
wsptr += DCTSIZE; /* advance pointer to next row */
}
}
hostname sparky
/sbin/ifconfig lo up 127.0.0.1 netmask 255.0.0.0
-/sbin/ifconfig eth0 up 192.168.0.80
+/sbin/ifconfig eth0 up 192.168.24.80
route add 127.0.0.1 dev lo
route add default dev eth0
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