r_temp = tcg_temp_new(TCG_TYPE_TL);
tcg_gen_xor_tl(r_temp, src1, src2);
- tcg_gen_xori_tl(r_temp, r_temp, -1);
+ tcg_gen_not_tl(r_temp, r_temp);
tcg_gen_xor_tl(cpu_tmp0, src1, dst);
tcg_gen_and_tl(r_temp, r_temp, cpu_tmp0);
tcg_gen_andi_tl(r_temp, r_temp, (1ULL << 31));
r_temp = tcg_temp_new(TCG_TYPE_TL);
tcg_gen_xor_tl(r_temp, src1, src2);
- tcg_gen_xori_tl(r_temp, r_temp, -1);
+ tcg_gen_not_tl(r_temp, r_temp);
tcg_gen_xor_tl(cpu_tmp0, src1, dst);
tcg_gen_and_tl(r_temp, r_temp, cpu_tmp0);
tcg_gen_andi_tl(r_temp, r_temp, (1ULL << 63));
r_temp = tcg_temp_new(TCG_TYPE_TL);
tcg_gen_xor_tl(r_temp, src1, src2);
- tcg_gen_xori_tl(r_temp, r_temp, -1);
+ tcg_gen_not_tl(r_temp, r_temp);
tcg_gen_xor_tl(cpu_tmp0, src1, dst);
tcg_gen_and_tl(r_temp, r_temp, cpu_tmp0);
tcg_gen_andi_tl(r_temp, r_temp, (1ULL << 31));
gen_op_logic_cc(cpu_dst);
break;
case 0x7:
- tcg_gen_xori_tl(cpu_tmp0, cpu_src2, -1);
+ tcg_gen_not_tl(cpu_tmp0, cpu_src2);
tcg_gen_xor_tl(cpu_dst, cpu_src1, cpu_tmp0);
if (xop & 0x10)
gen_op_logic_cc(cpu_dst);
break;
case 0x066: /* VIS I fnot2 */
CHECK_FPU_FEATURE(dc, VIS1);
- tcg_gen_xori_i32(cpu_fpr[DFPREG(rd)], cpu_fpr[DFPREG(rs2)],
- -1);
- tcg_gen_xori_i32(cpu_fpr[DFPREG(rd) + 1],
- cpu_fpr[DFPREG(rs2) + 1], -1);
+ tcg_gen_not_i32(cpu_fpr[DFPREG(rd)], cpu_fpr[DFPREG(rs2)]);
+ tcg_gen_not_i32(cpu_fpr[DFPREG(rd) + 1],
+ cpu_fpr[DFPREG(rs2) + 1]);
break;
case 0x067: /* VIS I fnot2s */
CHECK_FPU_FEATURE(dc, VIS1);
- tcg_gen_xori_i32(cpu_fpr[rd], cpu_fpr[rs2], -1);
+ tcg_gen_not_i32(cpu_fpr[rd], cpu_fpr[rs2]);
break;
case 0x068: /* VIS I fandnot1 */
CHECK_FPU_FEATURE(dc, VIS1);
break;
case 0x06a: /* VIS I fnot1 */
CHECK_FPU_FEATURE(dc, VIS1);
- tcg_gen_xori_i32(cpu_fpr[DFPREG(rd)], cpu_fpr[DFPREG(rs1)],
- -1);
- tcg_gen_xori_i32(cpu_fpr[DFPREG(rd) + 1],
- cpu_fpr[DFPREG(rs1) + 1], -1);
+ tcg_gen_not_i32(cpu_fpr[DFPREG(rd)], cpu_fpr[DFPREG(rs1)]);
+ tcg_gen_not_i32(cpu_fpr[DFPREG(rd) + 1],
+ cpu_fpr[DFPREG(rs1) + 1]);
break;
case 0x06b: /* VIS I fnot1s */
CHECK_FPU_FEATURE(dc, VIS1);
- tcg_gen_xori_i32(cpu_fpr[rd], cpu_fpr[rs1], -1);
+ tcg_gen_not_i32(cpu_fpr[rd], cpu_fpr[rs1]);
break;
case 0x06c: /* VIS I fxor */
CHECK_FPU_FEATURE(dc, VIS1);