plt_step_cnt := 0;\r
nt_step_cnt := 0;\r
spr_step_cnt := 0;\r
+ dma_step_cnt := 0;\r
enable_ppu_step_cnt := 0;\r
cpu_cnt := 0;\r
\r
end if;\r
\r
if (i < 64) then\r
+ --set dma value on the ram.\r
if (dma_step_cnt = (0 + j) * cpu_io_multi) then\r
- io_out(16#0200# + dma_step_cnt, i);\r
+ io_out(16#0200# + j, i);\r
elsif (dma_step_cnt = (1 + j) * cpu_io_multi) then\r
- io_out(16#0201# + dma_step_cnt, ch);\r
+ io_out(16#0201# + j, ch);\r
elsif (dma_step_cnt = (2 + j) * cpu_io_multi) then\r
- io_out(16#0202# + dma_step_cnt, 16#01#);\r
+ io_out(16#0202# + j, 16#01#);\r
elsif (dma_step_cnt = (3 + j) * cpu_io_multi) then\r
- io_out(16#0203# + dma_step_cnt, j);\r
- else\r
+ io_out(16#0203# + j, j);\r
+ elsif (dma_step_cnt = (0 + j) * cpu_io_multi + 1) or\r
+ (dma_step_cnt = (1 + j) * cpu_io_multi + 1) or\r
+ (dma_step_cnt = (2 + j) * cpu_io_multi + 1) or\r
+ (dma_step_cnt = (3 + j) * cpu_io_multi + 1) then\r
io_brk;\r
- if (dma_step_cnt > 17 * cpu_io_multi) then\r
- global_step_cnt := global_step_cnt + 1;\r
- end if;\r
end if;\r
else\r
if (dma_step_cnt = (0 + j) * cpu_io_multi) then\r
--start dma\r
io_out(16#4014#, 16#02#);\r
- else\r
+ elsif (dma_step_cnt = (0 + j) * cpu_io_multi + 1) then\r
io_brk;\r
- if (dma_step_cnt > 17 * cpu_io_multi) then\r
- global_step_cnt := global_step_cnt + 1;\r
- end if;\r
+ elsif (dma_step_cnt = (0 + j) * cpu_io_multi + 2) then\r
+ global_step_cnt := global_step_cnt + 1;\r
end if;\r
end if;\r
end loop;\r
vlib rtl_work\r
vmap work rtl_work\r
\r
-vcom -93 -work work {D:/daisuke/nes/repo/motonesfpga/de1_nes/motonesfpga_common.vhd}\r
-vcom -93 -work work {D:/daisuke/nes/repo/motonesfpga/de1_nes/mem/ram.vhd}\r
-vcom -93 -work work {D:/daisuke/nes/repo/motonesfpga/de1_nes/ppu/ppu_registers.vhd}\r
-vcom -93 -work work {D:/daisuke/nes/repo/motonesfpga/de1_nes/clock/clock_divider.vhd}\r
-vcom -93 -work work {D:/daisuke/nes/repo/motonesfpga/de1_nes/address_decoder.vhd}\r
-vcom -93 -work work {D:/daisuke/nes/repo/motonesfpga/de1_nes/de1_nes.vhd}\r
-vcom -93 -work work {D:/daisuke/nes/repo/motonesfpga/de1_nes/mem/chr_rom.vhd}\r
-vcom -93 -work work {D:/daisuke/nes/repo/motonesfpga/de1_nes/ppu/vga_ppu.vhd}\r
-vcom -93 -work work {D:/daisuke/nes/repo/motonesfpga/de1_nes/ppu/ppu.vhd}\r
-vcom -93 -work work {D:/daisuke/nes/repo/motonesfpga/de1_nes/dummy-mos6502.vhd}\r
-\r
-#vcom -93 -work work {D:/daisuke/nes/repo/motonesfpga/de1_nes/apu/apu.vhd}\r
-#vcom -93 -work work {D:/daisuke/nes/repo/motonesfpga/de1_nes/mem/prg_rom.vhd}\r
-#vcom -93 -work work {D:/daisuke/nes/repo/motonesfpga/de1_nes/cpu/cpu_registers.vhd}\r
-#vcom -93 -work work {D:/daisuke/nes/repo/motonesfpga/de1_nes/cpu/mos6502.vhd}\r
-#vcom -93 -work work {D:/daisuke/nes/repo/motonesfpga/de1_nes/cpu/decoder.vhd}\r
-#vcom -93 -work work {D:/daisuke/nes/repo/motonesfpga/de1_nes/cpu/alu.vhd}\r
-\r
-vcom -93 -work work {D:/daisuke/nes/repo/motonesfpga/de1_nes/testbench_motones_sim.vhd}\r
+vcom -93 -work work {../../motonesfpga_common.vhd}\r
+vcom -93 -work work {../../mem/ram.vhd}\r
+vcom -93 -work work {../../ppu/ppu_registers.vhd}\r
+vcom -93 -work work {../../clock/clock_divider.vhd}\r
+vcom -93 -work work {../../address_decoder.vhd}\r
+vcom -93 -work work {../../de1_nes.vhd}\r
+vcom -93 -work work {../../mem/chr_rom.vhd}\r
+vcom -93 -work work {../../ppu/vga_ppu.vhd}\r
+vcom -93 -work work {../../ppu/ppu.vhd}\r
+vcom -93 -work work {../../dummy-mos6502.vhd}\r
+\r
+#vcom -93 -work work {../../apu/apu.vhd}\r
+#vcom -93 -work work {../../mem/prg_rom.vhd}\r
+#vcom -93 -work work {../../cpu/cpu_registers.vhd}\r
+#vcom -93 -work work {../../cpu/mos6502.vhd}\r
+#vcom -93 -work work {../../cpu/decoder.vhd}\r
+#vcom -93 -work work {../../cpu/alu.vhd}\r
+\r
+vcom -93 -work work {../../testbench_motones_sim.vhd}\r
\r
vsim -t 1ps -L lpm -L altera -L altera_mf -L sgate -L cycloneii -L rtl_work -L work testbench_motones_sim\r
\r
view structure\r
view signals\r
\r
-run 2 us\r
+run 10 us\r
wave zoom full\r
\r
-run 2 us\r
+run 70 us\r
#run 65 us\r
\r