update

diff --git a/de0_cv_nes/mos6502.vhd b/de0_cv_nes/mos6502.vhd
index 1ef5ea8..151dcff 100644 (file)
--- a/de0_cv_nes/mos6502.vhd
+++ b/de0_cv_nes/mos6502.vhd
@@ -232,7 +232,7 @@ begin
         end if;--if (pi_rst_n = '0') then\r
     end process;\r
 \r
-    --state change to next.\r
+    --fixed length sub status change (0 - 31 because cpu clock is 1/32 of base clock).\r
     tx_next_sub_stat_p : process (reg_sub_state, pi_cpu_en)\r
     begin\r
         case reg_sub_state is\r
@@ -969,6 +969,11 @@ begin
         end case;\r
     end process;\r
 \r
+\r
+    po_r_nw     <= reg_r_nw;\r
+    po_addr     <= reg_addr;\r
+    pio_d_io    <= reg_d_out;\r
+\r
     --addressing general process...\r
     --pc, io bus, r/w, instruction regs...\r
     ad_general_p : process (pi_rst_n, pi_base_clk)\r
@@ -991,8 +996,14 @@ end;
             reg_inst    <= (others => '0');\r
             reg_addr    <= (others => 'Z');\r
             reg_d_out   <= (others => 'Z');\r
+            reg_d_in    <= (others => '0');\r
             reg_r_nw    <= 'Z';\r
         elsif (rising_edge(pi_base_clk)) then\r
+\r
+            --general input data register.\r
+            reg_d_in    <= pio_d_io;\r
+            \r
+            --i/o data bus state change.\r
             if (reg_main_state = ST_RS_T0) then\r
                 reg_pc_l    <= (others => '0');\r
                 reg_pc_h    <= (others => '0');\r
@@ -1157,11 +1168,6 @@ end;
         end if;--if (pi_rst_n = '0') then\r
     end process;\r
 \r
-    po_r_nw     <= reg_r_nw;\r
-    po_addr     <= reg_addr;\r
-    pio_d_io    <= reg_d_out;\r
-    reg_d_in    <= pio_d_io;\r
-\r
     --internal data latch...\r
     --fetch first and second operand.\r
     idl_p : process (pi_rst_n, pi_base_clk)\r

diff --git a/de0_cv_nes/simulation/modelsim/de0_cv_nes_run_msim_rtl_vhdl.do b/de0_cv_nes/simulation/modelsim/de0_cv_nes_run_msim_rtl_vhdl.do
index 58b61cd..d301659 100644 (file)
--- a/de0_cv_nes/simulation/modelsim/de0_cv_nes_run_msim_rtl_vhdl.do
+++ b/de0_cv_nes/simulation/modelsim/de0_cv_nes_run_msim_rtl_vhdl.do
@@ -61,7 +61,7 @@ view signals
 run 12 us\r
 wave zoom full\r
 \r
-run 180 us\r
+run 170 us\r
 \r
 \r
 #################################### PPU part.... ###########################################\r