IPW_DEBUG_IO("%s %d: write_direct8(0x%08X, 0x%08X)\n", __FILE__, __LINE__, (u32)(ofs), (u32)(val)); \
_ipw_write8(ipw, ofs, val)
-
/* 16-bit direct write (low 4K) */
#define _ipw_write16(ipw, ofs, val) writew((val), (ipw)->hw_base + (ofs))
IPW_DEBUG_IO("%s %d: write_direct16(0x%08X, 0x%08X)\n", __FILE__, __LINE__, (u32)(ofs), (u32)(val)); \
_ipw_write16(ipw, ofs, val)
-
/* 32-bit direct write (low 4K) */
#define _ipw_write32(ipw, ofs, val) writel((val), (ipw)->hw_base + (ofs))
IPW_DEBUG_IO("%s %d: write_direct32(0x%08X, 0x%08X)\n", __FILE__, __LINE__, (u32)(ofs), (u32)(val)); \
_ipw_write32(ipw, ofs, val)
-
/* 8-bit direct read (low 4K) */
#define _ipw_read8(ipw, ofs) readb((ipw)->hw_base + (ofs))
/* alias to 8-bit direct read (low 4K of SRAM/regs), with debug wrapper */
#define ipw_read8(ipw, ofs) __ipw_read8(__FILE__, __LINE__, ipw, ofs)
-
/* 16-bit direct read (low 4K) */
#define _ipw_read16(ipw, ofs) readw((ipw)->hw_base + (ofs))
/* alias to 16-bit direct read (low 4K of SRAM/regs), with debug wrapper */
#define ipw_read16(ipw, ofs) __ipw_read16(__FILE__, __LINE__, ipw, ofs)
-
/* 32-bit direct read (low 4K) */
#define _ipw_read32(ipw, ofs) readl((ipw)->hw_base + (ofs))
/* alias to 32-bit direct read (low 4K of SRAM/regs), with debug wrapper */
#define ipw_read32(ipw, ofs) __ipw_read32(__FILE__, __LINE__, ipw, ofs)
-
/* multi-byte read (above 4K), with debug wrapper */
static void _ipw_read_indirect(struct ipw_priv *, u32, u8 *, int);
static inline void __ipw_read_indirect(const char *f, int l,
/* 8-bit indirect write (above 4K) */
static void _ipw_write_reg8(struct ipw_priv *priv, u32 reg, u8 value)
{
- u32 aligned_addr = reg & IPW_INDIRECT_ADDR_MASK; /* dword align */
+ u32 aligned_addr = reg & IPW_INDIRECT_ADDR_MASK; /* dword align */
u32 dif_len = reg - aligned_addr;
IPW_DEBUG_IO(" reg = 0x%8X : value = 0x%8X\n", reg, value);
/* 16-bit indirect write (above 4K) */
static void _ipw_write_reg16(struct ipw_priv *priv, u32 reg, u16 value)
{
- u32 aligned_addr = reg & IPW_INDIRECT_ADDR_MASK; /* dword align */
+ u32 aligned_addr = reg & IPW_INDIRECT_ADDR_MASK; /* dword align */
u32 dif_len = (reg - aligned_addr) & (~0x1ul);
IPW_DEBUG_IO(" reg = 0x%8X : value = 0x%8X\n", reg, value);
_ipw_write16(priv, IPW_INDIRECT_DATA + dif_len, value);
}
-
/* 8-bit indirect read (above 4K) */
static u8 _ipw_read_reg8(struct ipw_priv *priv, u32 reg)
{
static void _ipw_read_indirect(struct ipw_priv *priv, u32 addr, u8 * buf,
int num)
{
- u32 aligned_addr = addr & IPW_INDIRECT_ADDR_MASK; /* dword align */
+ u32 aligned_addr = addr & IPW_INDIRECT_ADDR_MASK; /* dword align */
u32 dif_len = addr - aligned_addr;
u32 i;
static void _ipw_write_indirect(struct ipw_priv *priv, u32 addr, u8 * buf,
int num)
{
- u32 aligned_addr = addr & IPW_INDIRECT_ADDR_MASK; /* dword align */
+ u32 aligned_addr = addr & IPW_INDIRECT_ADDR_MASK; /* dword align */
u32 dif_len = addr - aligned_addr;
u32 i;
#endif
printk_buf(IPW_DL_HOST_COMMAND, (u8 *) cmd->param, cmd->len);
-
rc = ipw_queue_tx_hcmd(priv, cmd->cmd, cmd->param, cmd->len, 0);
if (rc) {
priv->status &= ~STATUS_HCMD_ACTIVE;
goto exit;
}
-exit:
+ exit:
if (priv->cmdlog) {
priv->cmdlog[priv->cmdlog_pos++].retcode = rc;
priv->cmdlog_pos %= priv->cmdlog_len;
}
return ipw_send_cmd_pdu(priv, IPW_CMD_SYSTEM_CONFIG, sizeof(*config),
- config);
+ config);
}
static int ipw_send_ssid(struct ipw_priv *priv, u8 * ssid, int len)
}
return ipw_send_cmd_pdu(priv, IPW_CMD_SSID, min(len, IW_ESSID_MAX_SIZE),
- ssid);
+ ssid);
}
static int ipw_send_adapter_address(struct ipw_priv *priv, u8 * mac)
IPW_DEBUG_INFO("%s: Setting MAC to " MAC_FMT "\n",
priv->net_dev->name, MAC_ARG(mac));
- return ipw_send_cmd_pdu(priv, IPW_CMD_ADAPTER_ADDRESS, ETH_ALEN,
- mac);
+ return ipw_send_cmd_pdu(priv, IPW_CMD_ADAPTER_ADDRESS, ETH_ALEN, mac);
}
/*
struct ipw_scan_request_ext *request)
{
return ipw_send_cmd_pdu(priv, IPW_CMD_SCAN_REQUEST_EXT,
- sizeof(*request), request);
+ sizeof(*request), request);
}
static int ipw_send_scan_abort(struct ipw_priv *priv)
};
return ipw_send_cmd_pdu(priv, IPW_CMD_SENSITIVITY_CALIB, sizeof(calib),
- &calib);
+ &calib);
}
static int ipw_send_associate(struct ipw_priv *priv,
tmp_associate.atim_window = cpu_to_le16(tmp_associate.atim_window);
return ipw_send_cmd_pdu(priv, IPW_CMD_ASSOCIATE, sizeof(tmp_associate),
- &tmp_associate);
+ &tmp_associate);
}
static int ipw_send_supported_rates(struct ipw_priv *priv,
}
return ipw_send_cmd_pdu(priv, IPW_CMD_SUPPORTED_RATES, sizeof(*rates),
- rates);
+ rates);
}
static int ipw_set_random_seed(struct ipw_priv *priv)
}
return ipw_send_cmd_pdu(priv, IPW_CMD_CARD_DISABLE, sizeof(phy_off),
- &phy_off);
+ &phy_off);
}
static int ipw_send_tx_power(struct ipw_priv *priv, struct ipw_tx_power *power)
return -1;
}
- return ipw_send_cmd_pdu(priv, IPW_CMD_TX_POWER, sizeof(*power),
- power);
+ return ipw_send_cmd_pdu(priv, IPW_CMD_TX_POWER, sizeof(*power), power);
}
static int ipw_set_tx_power(struct ipw_priv *priv)
}
return ipw_send_cmd_pdu(priv, IPW_CMD_POWER_MODE, sizeof(param),
- ¶m);
+ ¶m);
}
static int ipw_send_retry_limit(struct ipw_priv *priv, u8 slimit, u8 llimit)
}
return ipw_send_cmd_pdu(priv, IPW_CMD_RETRY_LIMIT, sizeof(retry_limit),
- &retry_limit);
+ &retry_limit);
}
/*
#ifdef CONFIG_PM
}
#endif
-
+
/* DMA the ucode into the device */
rc = ipw_load_ucode(priv, ucode->data + sizeof(struct fw_header),
ucode->size - sizeof(struct fw_header));
IPW_ERROR("Unable to load firmware: %d\n", rc);
goto error;
}
-
#ifdef CONFIG_PM
fw_loaded = 1;
#endif
"because of age: %ums.\n",
escape_essid(network->ssid, network->ssid_len),
MAC_ARG(network->bssid),
- jiffies_to_msecs(jiffies - network->last_scanned));
+ jiffies_to_msecs(jiffies -
+ network->last_scanned));
return 0;
}
"assoc attempt).\n",
escape_essid(network->ssid, network->ssid_len),
MAC_ARG(network->bssid),
- jiffies_to_msecs(jiffies - network->last_associate));
+ jiffies_to_msecs(jiffies -
+ network->last_associate));
return 0;
}
"because of age: %ums.\n",
escape_essid(network->ssid, network->ssid_len),
MAC_ARG(network->bssid),
- jiffies_to_msecs(jiffies - network->last_scanned));
+ jiffies_to_msecs(jiffies -
+ network->last_scanned));
return 0;
}
IPW_DEBUG_HC("HOST_CMD_RSN_CAPABILITIES\n");
return ipw_send_cmd_pdu(priv, IPW_CMD_RSN_CAPABILITIES, length,
- capabilities);
+ capabilities);
}
/*
/* Support Bluetooth if we have BT h/w on board, and user wants to.
* Does not support BT priority yet (don't abort or defer our Tx) */
if (bt_coexist) {
- unsigned char bt_caps = priv->eeprom[EEPROM_SKU_CAPABILITY];
+ unsigned char bt_caps = priv->eeprom[EEPROM_SKU_CAPABILITY];
if (bt_caps & EEPROM_SKU_CAP_BT_CHANNEL_SIG)
priv->sys_config.bt_coexistence
- |= CFG_BT_COEXISTENCE_SIGNAL_CHNL;
+ |= CFG_BT_COEXISTENCE_SIGNAL_CHNL;
if (bt_caps & EEPROM_SKU_CAP_BT_OOB)
priv->sys_config.bt_coexistence
- |= CFG_BT_COEXISTENCE_OOB;
+ |= CFG_BT_COEXISTENCE_OOB;
}
if (priv->ieee->iw_mode == IW_MODE_ADHOC)
#define IPW_DOMAIN_0_END 0x1000
#define CLX_MEM_BAR_SIZE 0x1000
-
/* Dino/baseband control registers bits */
-#define DINO_ENABLE_SYSTEM 0x80 /* 1 = baseband processor on, 0 = reset */
-#define DINO_ENABLE_CS 0x40 /* 1 = enable ucode load */
-#define DINO_RXFIFO_DATA 0x01 /* 1 = data available */
+#define DINO_ENABLE_SYSTEM 0x80 /* 1 = baseband processor on, 0 = reset */
+#define DINO_ENABLE_CS 0x40 /* 1 = enable ucode load */
+#define DINO_RXFIFO_DATA 0x01 /* 1 = data available */
#define IPW_BASEBAND_CONTROL_STATUS 0X00200000
#define IPW_BASEBAND_TX_FIFO_WRITE 0X00200004
#define IPW_BASEBAND_RX_FIFO_READ 0X00200004
#define EEPROM_NIC_TYPE_4 4
/* Bluetooth Coexistence capabilities as found in EEPROM_SKU_CAPABILITY */
-#define EEPROM_SKU_CAP_BT_CHANNEL_SIG 0x01 /* we can tell BT our channel # */
-#define EEPROM_SKU_CAP_BT_PRIORITY 0x02 /* BT can take priority over us */
-#define EEPROM_SKU_CAP_BT_OOB 0x04 /* we can signal BT out-of-band */
+#define EEPROM_SKU_CAP_BT_CHANNEL_SIG 0x01 /* we can tell BT our channel # */
+#define EEPROM_SKU_CAP_BT_PRIORITY 0x02 /* BT can take priority over us */
+#define EEPROM_SKU_CAP_BT_OOB 0x04 /* we can signal BT out-of-band */
#define FW_MEM_REG_LOWER_BOUND 0x00300000
#define FW_MEM_REG_EEPROM_ACCESS (FW_MEM_REG_LOWER_BOUND + 0x40)
/* SysConfig command parameters ... */
/* bt_coexistence param */
-#define CFG_BT_COEXISTENCE_SIGNAL_CHNL 0x01 /* tell BT our chnl # */
-#define CFG_BT_COEXISTENCE_DEFER 0x02 /* defer our Tx if BT traffic */
-#define CFG_BT_COEXISTENCE_KILL 0x04 /* kill our Tx if BT traffic */
-#define CFG_BT_COEXISTENCE_WME_OVER_BT 0x08 /* multimedia extensions */
-#define CFG_BT_COEXISTENCE_OOB 0x10 /* signal BT via out-of-band */
+#define CFG_BT_COEXISTENCE_SIGNAL_CHNL 0x01 /* tell BT our chnl # */
+#define CFG_BT_COEXISTENCE_DEFER 0x02 /* defer our Tx if BT traffic */
+#define CFG_BT_COEXISTENCE_KILL 0x04 /* kill our Tx if BT traffic */
+#define CFG_BT_COEXISTENCE_WME_OVER_BT 0x08 /* multimedia extensions */
+#define CFG_BT_COEXISTENCE_OOB 0x10 /* signal BT via out-of-band */
/* clear-to-send to self param */
#define CFG_CTS_TO_ITSELF_ENABLED_MIN 0x00
#define CFG_CTS_TO_ITSELF_ENABLED_DEF CFG_CTS_TO_ITSELF_ENABLED_MIN
/* Antenna diversity param (h/w can select best antenna, based on signal) */
-#define CFG_SYS_ANTENNA_BOTH 0x00 /* NIC selects best antenna */
-#define CFG_SYS_ANTENNA_A 0x01 /* force antenna A */
-#define CFG_SYS_ANTENNA_B 0x03 /* force antenna B */
+#define CFG_SYS_ANTENNA_BOTH 0x00 /* NIC selects best antenna */
+#define CFG_SYS_ANTENNA_A 0x01 /* force antenna A */
+#define CFG_SYS_ANTENNA_B 0x03 /* force antenna B */
/*
* The definitions below were lifted off the ipw2100 driver, which only
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