OSDN Git Service
(root)
/
qmiga
/
qemu.git
/ commitdiff
commit
grep
author
committer
pickaxe
?
search:
re
summary
|
shortlog
|
log
|
commit
| commitdiff |
tree
raw
|
patch
| inline |
side by side
(parent:
bbb0250
)
hw/arm/smmuv3: Add missing fields for IDR0
author
Mostafa Saleh
<smostafa@google.com>
Thu, 25 May 2023 09:37:49 +0000
(10:37 +0100)
committer
Peter Maydell
<peter.maydell@linaro.org>
Tue, 30 May 2023 12:02:53 +0000
(13:02 +0100)
In preparation for adding stage-2 support.
Add IDR0 fields related to stage-2.
VMID16: 16-bit VMID supported.
S2P: Stage-2 translation supported.
They are described in 6.3.1 SMMU_IDR0.
No functional change intended.
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Eric Auger <eric.auger@redhat.com>
Signed-off-by: Mostafa Saleh <smostafa@google.com>
Tested-by: Eric Auger <eric.auger@redhat.com>
Tested-by: Jean-Philippe Brucker <jean-philippe@linaro.org>
Message-id:
20230516203327
.
2051088
-2-smostafa@google.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
hw/arm/smmuv3-internal.h
patch
|
blob
|
history
diff --git
a/hw/arm/smmuv3-internal.h
b/hw/arm/smmuv3-internal.h
index
e8f0ebf
..
183d5ac
100644
(file)
--- a/
hw/arm/smmuv3-internal.h
+++ b/
hw/arm/smmuv3-internal.h
@@
-34,10
+34,12
@@
typedef enum SMMUTranslationStatus {
/* MMIO Registers */
REG32(IDR0, 0x0)
+ FIELD(IDR0, S2P, 0 , 1)
FIELD(IDR0, S1P, 1 , 1)
FIELD(IDR0, TTF, 2 , 2)
FIELD(IDR0, COHACC, 4 , 1)
FIELD(IDR0, ASID16, 12, 1)
+ FIELD(IDR0, VMID16, 18, 1)
FIELD(IDR0, TTENDIAN, 21, 2)
FIELD(IDR0, STALL_MODEL, 24, 2)
FIELD(IDR0, TERM_MODEL, 26, 1)