2004-02-10 Kazuhiro Inaoka <inaoka.kazuhiro@renesas.dot.com>

	* cpu/m32r.opc (my_print_insn): Fixed incorrect output when
	disassembling codes for 0x*2 addresses.

diff --git a/cgen/ChangeLog b/cgen/ChangeLog
index c4e8aad..9f8cb7f 100644 (file)
--- a/cgen/ChangeLog
+++ b/cgen/ChangeLog
@@ -1,3 +1,8 @@
+2004-02-10  Kazuhiro Inaoka  <inaoka.kazuhiro@renesas.dot.com>
+
+       * cpu/m32r.opc (my_print_insn): Fixed incorrect output when
+       disassembling codes for 0x*2 addresses.
+
 2004-01-29  Dave Brolley  <brolley@redhat.com>
 
        * decode.scm (-opcode-slots): For short insns, generate 'opcode' with

diff --git a/cgen/cpu/m32r.opc b/cgen/cpu/m32r.opc
index ac87da3..2a3ac44 100644 (file)
--- a/cgen/cpu/m32r.opc
+++ b/cgen/cpu/m32r.opc
@@ -273,7 +273,8 @@ my_print_insn (cd, pc, info)
 
   /* Read the base part of the insn.  */
 
-  status = (*info->read_memory_func) (pc, buf, buflen, info);
+  status = (*info->read_memory_func) (pc - ((!big_p && (pc & 3) != 0) ? 2 : 0),
+                                      buf, buflen, info);
   if (status != 0)
     {
       (*info->memory_error_func) (status, pc, info);
@@ -286,13 +287,13 @@ my_print_insn (cd, pc, info)
     return print_insn (cd, pc, info, buf, buflen);
 
   /* Print the first insn.  */
-  buf += (big_p ? 0 : 2);
   if ((pc & 3) == 0)
     {
+      buf += (big_p ? 0 : 2);
       if (print_insn (cd, pc, info, buf, 2) == 0)
        (*info->fprintf_func) (info->stream, UNKNOWN_INSN_MSG);
+      buf += (big_p ? 2 : -2);
     }
-  buf += (big_p ? 2 : -2);
 
   x = (big_p ? &buf[0] : &buf[1]);
   if (*x & 0x80)