* openrisc.cpu (or32): Setup semantics for h-delay-insn to

        current insn plus 4.
        (h-delay-insn): New hardware register.
        (l-jal): Uses h-delay-insn instead of pc when setting link register.
        (l-jalr): Likewise.
        (l-bal): Likewise.

        * openrisc.opc (parse_hi16): Sign extend value.
        (parse_lo16): Likewise.

diff --git a/cgen/ChangeLog b/cgen/ChangeLog
index 19355da..5836a95 100644 (file)
--- a/cgen/ChangeLog
+++ b/cgen/ChangeLog
@@ -1,3 +1,15 @@
+2001-01-06  Johan Rydberg  <jrydberg@opencores.org>
+
+       * openrisc.cpu (or32): Setup semantics for h-delay-insn to
+       current insn plus 4.
+       (h-delay-insn): New hardware register.
+       (l-jal): Uses h-delay-insn instead of pc when setting link register.
+       (l-jalr): Likewise.
+       (l-bal): Likewise.
+
+       * openrisc.opc (parse_hi16): Sign extend value.
+       (parse_lo16): Likewise.
+
 2001-01-06  Ben Elliston  <bje@redhat.com>
 
        * utils-gen.scm (gen-sfmt-enum-decl): Use @prefix@ and @PREFIX@

diff --git a/cgen/openrisc.cpu b/cgen/openrisc.cpu
index 9f00f78..77c32d7 100644 (file)
--- a/cgen/openrisc.cpu
+++ b/cgen/openrisc.cpu
@@ -73,6 +73,9 @@
 
   ; Base insturction length.  The insns is always 32 bits wide.
   (base-insn-bitsize 32)
+
+  ; Address of insn in delay slot
+  (setup-semantics (set-quiet (reg h-delay-insn) (add pc (attr (current-insn) 4))))
 )
 
 \f
@@ -257,6 +260,7 @@
 (dnh h-lo16 "low 16 bits"  () (immediate (INT 16)) () () ())
 
 (dsh h-cbit "condition bit" () (register BI))
+(dsh h-delay-insn "delay insn addr" () (register SI))
 
 \f
 ; Instruction operands.
@@ -328,9 +332,9 @@
      (+ OP1_0 OP2_1 abs-26)
 
      ; We execute the delay slot before doin' the real branch
-     ; Set LR to (pc + 4)
+     ; Set LR to (delay insn addr + 4)
      (sequence ()
-               (set (reg h-gr 11) (add pc 4))
+               (set (reg h-gr 11) (add (reg h-delay-insn) 4))
                (delay 1 (set pc abs-26)))
      ()
 )
@@ -361,7 +365,7 @@
      ; We execute the delay slot before doin' the real branch
      (sequence ((WI tmp-slot))
                (set tmp-slot rA)
-               (set (reg h-gr 11) (add pc 4))
+               (set (reg h-gr 11) (add (reg h-delay-insn) 4))
                (delay 1 (set pc tmp-slot)))
      ()
 )
@@ -374,9 +378,9 @@
      (+ OP1_0 OP2_2 disp-26)
 
      ; We execute the delay slot before doin' the real branch
-     ; Set LR to (pc + 4)
+     ; Set LR to (delay insn addr + 4)
      (sequence ()
-               (set (reg h-gr 11) (add pc 4))
+               (set (reg h-gr 11) (add (reg h-delay-insn) 4))
                (delay 1 (set pc disp-26)))
      ()
 )

diff --git a/cgen/openrisc.opc b/cgen/openrisc.opc
index 74bd4c7..621db0e 100644 (file)
--- a/cgen/openrisc.opc
+++ b/cgen/openrisc.opc
@@ -76,7 +76,7 @@ parse_hi16 (cd, strp, opindex, valuep)
       if (errmsg == NULL
           && result_type == CGEN_PARSE_OPERAND_RESULT_NUMBER)
         value >>= 16;
-      *valuep = value;
+      *valuep = (long) (short) value;
 
       return errmsg;
     }
@@ -87,7 +87,7 @@ parse_hi16 (cd, strp, opindex, valuep)
       else
         errmsg = cgen_parse_unsigned_integer (cd, strp, opindex, &value);
     }
-  *valuep = value & 0xffff;
+  *valuep = (long) (short) (value & 0xffff);
   return errmsg;
 }
 
@@ -127,7 +127,7 @@ parse_lo16 (cd, strp, opindex, valuep)
       if (errmsg == NULL
           && result_type == CGEN_PARSE_OPERAND_RESULT_NUMBER)
         value &= 0xffff;
-      *valuep = value;
+      *valuep = (long) (short) value;
 
       return errmsg;
     }
@@ -136,7 +136,7 @@ parse_lo16 (cd, strp, opindex, valuep)
     errmsg = cgen_parse_signed_integer (cd, strp, opindex, (long *) &value);
   else
     errmsg = cgen_parse_unsigned_integer (cd, strp, opindex, &value);
-  *valuep = value & 0xffff;
+  *valuep = (long) (short) (value & 0xffff);
   return errmsg;
 }