signal ppu_addr_in : std_logic_vector (13 downto 0);
signal ppu_addr_cnt : std_logic_vector (0 downto 0);
signal ppu_data : std_logic_vector (dsize - 1 downto 0);
+signal ppu_data_in : std_logic_vector (dsize - 1 downto 0);
signal ppu_data_out : std_logic_vector (dsize - 1 downto 0);
signal read_data_n : std_logic;
signal ppu_latch_rst_n : std_logic;
signal oam_bus_ce_n : std_logic;
signal plt_bus_ce_n : std_logic;
-signal oam_plt_addr : std_logic_vector (7 downto 0);
-signal oam_plt_data : std_logic_vector (7 downto 0);
+signal oam_plt_addr : std_logic_vector (dsize - 1 downto 0);
+signal oam_plt_data : std_logic_vector (dsize - 1 downto 0);
+signal plt_data_out : std_logic_vector (dsize - 1 downto 0);
begin
ppu_data_inst : d_flip_flop generic map(dsize)
port map (clk_n, rst_n, '1', ppu_data_we_n, cpu_d, ppu_data);
+ ppu_data_in_inst : d_flip_flop generic map(dsize)
+ port map (clk_n, rst_n, '1', ppu_data_we_n, vram_ad, ppu_data_in);
+
ppu_data_out_inst : d_flip_flop generic map(dsize)
- port map (clk_n, rst_n, '1', read_data_n, ppu_data, ppu_data_out);
+ port map (read_data_n, rst_n, '1', '0', ppu_data_in, ppu_data_out);
+ plt_data_out_inst : d_flip_flop generic map(dsize)
+ port map (clk_n, rst_n, '1', ppu_data_we_n, oam_plt_data, plt_data_out);
reg_set_p : process (rst_n, ce_n, r_nw, cpu_addr, cpu_d,
ppu_status(ST_VBL), ppu_ctrl(PPUNEN))
ppu_addr_we_n <= '1';
end if;
- if (cpu_addr = PPUDATA and r_nw = '0') then
+ if (cpu_addr = PPUDATA and r_nw = '1') then
read_data_n <= '0';
else
read_data_n <= '1';
if (r_nw = '0') then
vram_ad <= cpu_d;
else
- vram_ad <= (others => 'Z');
- cpu_d <= vram_ad;
+ cpu_d <= ppu_data_out;
end if;
end if;
else
--sustain cpu output data when reading.
if (cpu_addr = PPUDATA and r_nw = '1' and ppu_clk_cnt /= "00") then
- cpu_d <= ppu_data;
+ if (ppu_addr(13 downto 8) = "111111") then
+ cpu_d <= plt_data_out;
+ else
+ cpu_d <= ppu_data_out;
+ end if;
end if;
if (cpu_addr = OAMDATA and r_nw = '1' and ppu_clk_cnt /= "00") then
cpu_d <= oam_data;
sta $2000\r
sta $2001\r
\r
+;;; ;;;carry flag set.\r
+;;; lda #$ff\r
+;;; adc #$01\r
+;;; jmp branch_boundary_test1\r
+;;; ;;fill dummy data to test page boundary instruction.\r
+;;; .byte $00, $01, $02, $03, $04, $05, $06, $07, $08, $09, $0a, $0b, $0c, $0d, $0e, $0f\r
+;;; .byte $00, $01, $02, $03, $04, $05, $06, $07, $08, $09, $0a, $0b, $0c, $0d, $0e, $0f\r
+;;; .byte $00, $01, $02, $03, $04, $05, $06, $07, $08, $09, $0a, $0b, $0c, $0d, $0e, $0f\r
+;;; .byte $00, $01, $02, $03, $04, $05, $06, $07, $08, $09, $0a, $0b, $0c, $0d, $0e, $0f\r
+;;; .byte $00, $01, $02, $03, $04, $05, $06, $07, $08, $09, $0a, $0b, $0c, $0d, $0e, $0f\r
+;;; .byte $00, $01, $02, $03, $04, $05, $06, $07, $08, $09, $0a, $0b, $0c, $0d, $0e, $0f\r
+;;; .byte $00, $01, $02, $03, $04, $05, $06, $07, $08, $09, $0a, $0b, $0c, $0d, $0e, $0f\r
+;;; .byte $00, $01, $02, $03, $04, $05, $06, $07, $08, $09, $0a, $0b, $0c, $0d, $0e, $0f\r
+;;; .byte $00, $01, $02, $03, $04, $05, $06, $07, $08, $09, $0a, $0b, $0c, $0d, $0e, $0f\r
+;;; .byte $00, $01, $02, $03, $04, $05, $06, $07, $08, $09, $0a, $0b, $0c, $0d, $0e, $0f\r
+;;; .byte $00, $01, $02, $03, $04, $05, $06, $07, $08, $09, $0a, $0b, $0c, $0d, $0e, $0f\r
+;;; .byte $00, $01, $02, $03, $04, $05, $06, $07, $08, $09, $0a, $0b, $0c, $0d, $0e, $0f\r
+;;; .byte $00, $01, $02, $03, $04, $05, $06, $07, $08, $09, $0a, $0b, $0c, $0d, $0e, $0f\r
+;;; .byte $00, $01, $02, $03, $04, $05, $06, $07, $08, $09, $0a, $0b, $0c, $0d, $0e, $0f\r
+;;; .byte $00\r
+;;; ;;;single byte instruction page boundary test.\r
+;;;branch_boundary_test1:\r
+;;; BCS br_ad1\r
+;;; AND #$fb ;;this is skipped.\r
+;;;br_ad1:\r
+;;; STA $2000\r
+;;;\r
+;;; ;;dma test data.\r
+;;; ldy #$00\r
+;;; ldx #$41\r
+;;; stx $00\r
+;;; ldx #$00\r
+;;;dma_set:\r
+;;; ;;y pos\r
+;;; txa\r
+;;; sta $0200, y\r
+;;; iny\r
+;;; ;;tile index\r
+;;; lda $00\r
+;;; cmp #$5b\r
+;;; bne inc_tile\r
+;;; lda #$41\r
+;;; sta $00\r
+;;;inc_tile:\r
+;;; inc $00\r
+;;; sta $0200, y\r
+;;; iny\r
+;;; ;;attribute\r
+;;; lda #$01\r
+;;; sta $0200, y\r
+;;; iny\r
+;;; ;;x pos\r
+;;; txa\r
+;;; adc #$03\r
+;;; tax\r
+;;; rol\r
+;;; sta $0200, y\r
+;;; iny\r
+;;; bne dma_set\r
+\r
+;;; ;;dma start.\r
+;;; lda #$02\r
+;;; sta $4014\r
+\r
lda #$3f\r
sta $2006\r
lda #$00\r
sta $2006\r
\r
- ;;;carry flag set.\r
- lda #$ff\r
- adc #$01\r
- jmp branch_boundary_test1\r
- ;;fill dummy data to test page boundary instruction.\r
- .byte $00, $01, $02, $03, $04, $05, $06, $07, $08, $09, $0a, $0b, $0c, $0d, $0e, $0f\r
- .byte $00, $01, $02, $03, $04, $05, $06, $07, $08, $09, $0a, $0b, $0c, $0d, $0e, $0f\r
- .byte $00, $01, $02, $03, $04, $05, $06, $07, $08, $09, $0a, $0b, $0c, $0d, $0e, $0f\r
- .byte $00, $01, $02, $03, $04, $05, $06, $07, $08, $09, $0a, $0b, $0c, $0d, $0e, $0f\r
- .byte $00, $01, $02, $03, $04, $05, $06, $07, $08, $09, $0a, $0b, $0c, $0d, $0e, $0f\r
- .byte $00, $01, $02, $03, $04, $05, $06, $07, $08, $09, $0a, $0b, $0c, $0d, $0e, $0f\r
- .byte $00, $01, $02, $03, $04, $05, $06, $07, $08, $09, $0a, $0b, $0c, $0d, $0e, $0f\r
- .byte $00, $01, $02, $03, $04, $05, $06, $07, $08, $09, $0a, $0b, $0c, $0d, $0e, $0f\r
- .byte $00, $01, $02, $03, $04, $05, $06, $07, $08, $09, $0a, $0b, $0c, $0d, $0e, $0f\r
- .byte $00, $01, $02, $03, $04, $05, $06, $07, $08, $09, $0a, $0b, $0c, $0d, $0e, $0f\r
- .byte $00, $01, $02, $03, $04, $05, $06, $07, $08, $09, $0a, $0b, $0c, $0d, $0e, $0f\r
- .byte $00, $01, $02, $03, $04, $05, $06, $07, $08, $09, $0a, $0b, $0c, $0d, $0e, $0f\r
- .byte $00, $01, $02, $03, $04, $05, $06, $07, $08, $09, $0a, $0b, $0c, $0d, $0e, $0f\r
- .byte $00, $01, $02, $03, $04, $05, $06, $07, $08, $09, $0a, $0b, $0c, $0d, $0e, $0f\r
- .byte $00\r
- ;;;single byte instruction page boundary test.\r
-branch_boundary_test1:\r
- BCS br_ad1\r
- AND #$fb ;;this is skipped.\r
-br_ad1:\r
- STA $2000\r
-\r
- ;;dma test data.\r
- ldy #$00\r
- ldx #$41\r
- stx $00\r
- ldx #$00\r
-dma_set:\r
- ;;y pos\r
- txa\r
- sta $0200, y\r
- iny\r
- ;;tile index\r
- lda $00\r
- cmp #$5b\r
- bne inc_tile\r
- lda #$41\r
- sta $00\r
-inc_tile:\r
- inc $00\r
- sta $0200, y\r
- iny\r
- ;;attribute\r
- lda #$01\r
- sta $0200, y\r
- iny\r
- ;;x pos\r
- txa\r
- adc #$03\r
- tax\r
- rol\r
- sta $0200, y\r
- iny\r
- bne dma_set\r
-\r
- ;;dma start.\r
- lda #$02\r
- sta $4014\r
-\r
;;load palette.\r
ldx #$00\r
ldy #$20\r
dey\r
bne copymap\r
\r
- ;;;vertical show test.\r
- lda #$04\r
- sta $2000\r
+;; ;;;vertical show test.\r
+;; lda #$04\r
+;; sta $2000\r
+;;\r
+;; lda #$20\r
+;; sta $2006\r
+;; lda #$cb\r
+;; sta $2006\r
+;; ldx #$00\r
+;; ldy #$0d\r
+;;\r
+;; ;;load name table.\r
+;;copymap2:\r
+;; lda string, x\r
+;; sta $2007\r
+;; inx\r
+;; dey\r
+;; bne copymap2\r
\r
+ ;;vram read test\r
lda #$20\r
sta $2006\r
- lda #$cb\r
+ lda #$ab\r
sta $2006\r
- ldx #$00\r
- ldy #$0d\r
\r
- ;;load name table.\r
-copymap2:\r
- lda string, x\r
- sta $2007\r
- inx\r
- dey\r
- bne copymap2\r
+ ldx #$0a\r
+ lda $2007\r
+load_vram:\r
+ lda $2007\r
+ dex\r
+ bne load_vram\r
+\r
+ ;;palette read test\r
+ lda #$3f\r
+ sta $2006\r
+ lda #$00\r
+ sta $2006\r
+\r
+ ldx #$0a\r
+ lda $2007\r
+load_plt:\r
+ lda $2007\r
+ dex\r
+ bne load_plt\r
\r
;;scroll reg set.\r
lda #$00\r