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drm/amd/pp: implement function notify_cac_buffer_info on VI
authorRex Zhu <Rex.Zhu@amd.com>
Fri, 15 Sep 2017 11:39:52 +0000 (19:39 +0800)
committerAlex Deucher <alexander.deucher@amd.com>
Thu, 19 Oct 2017 19:26:52 +0000 (15:26 -0400)
Used for smu power logging.

Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Rex Zhu <Rex.Zhu@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
drivers/gpu/drm/amd/powerplay/hwmgr/cz_hwmgr.c
drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c
drivers/gpu/drm/amd/powerplay/inc/smumgr.h
drivers/gpu/drm/amd/powerplay/smumgr/ci_smc.c
drivers/gpu/drm/amd/powerplay/smumgr/fiji_smc.c
drivers/gpu/drm/amd/powerplay/smumgr/iceland_smc.c
drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smc.c
drivers/gpu/drm/amd/powerplay/smumgr/tonga_smc.c

index bd5b0c1..96da4fc 100644 (file)
@@ -1871,6 +1871,33 @@ static int cz_read_sensor(struct pp_hwmgr *hwmgr, int idx,
        }
 }
 
+static int cz_notify_cac_buffer_info(struct pp_hwmgr *hwmgr,
+                                       uint32_t virtual_addr_low,
+                                       uint32_t virtual_addr_hi,
+                                       uint32_t mc_addr_low,
+                                       uint32_t mc_addr_hi,
+                                       uint32_t size)
+{
+       smum_send_msg_to_smc_with_parameter(hwmgr,
+                                       PPSMC_MSG_DramAddrHiVirtual,
+                                       mc_addr_hi);
+       smum_send_msg_to_smc_with_parameter(hwmgr,
+                                       PPSMC_MSG_DramAddrLoVirtual,
+                                       mc_addr_low);
+       smum_send_msg_to_smc_with_parameter(hwmgr,
+                                       PPSMC_MSG_DramAddrHiPhysical,
+                                       virtual_addr_hi);
+       smum_send_msg_to_smc_with_parameter(hwmgr,
+                                       PPSMC_MSG_DramAddrLoPhysical,
+                                       virtual_addr_low);
+
+       smum_send_msg_to_smc_with_parameter(hwmgr,
+                                       PPSMC_MSG_DramBufferSize,
+                                       size);
+       return 0;
+}
+
+
 static const struct pp_hwmgr_func cz_hwmgr_funcs = {
        .backend_init = cz_hwmgr_backend_init,
        .backend_fini = cz_hwmgr_backend_fini,
@@ -1901,6 +1928,7 @@ static const struct pp_hwmgr_func cz_hwmgr_funcs = {
        .dynamic_state_management_enable = cz_enable_dpm_tasks,
        .power_state_set = cz_set_power_state_tasks,
        .dynamic_state_management_disable = cz_disable_dpm_tasks,
+       .notify_cac_buffer_info = cz_notify_cac_buffer_info,
 };
 
 int cz_init_function_pointers(struct pp_hwmgr *hwmgr)
index 4826b29..e32f18a 100644 (file)
@@ -4645,6 +4645,47 @@ static int smu7_avfs_control(struct pp_hwmgr *hwmgr, bool enable)
        return 0;
 }
 
+static int smu7_notify_cac_buffer_info(struct pp_hwmgr *hwmgr,
+                                       uint32_t virtual_addr_low,
+                                       uint32_t virtual_addr_hi,
+                                       uint32_t mc_addr_low,
+                                       uint32_t mc_addr_hi,
+                                       uint32_t size)
+{
+       struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
+
+       cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
+                                       data->soft_regs_start +
+                                       smum_get_offsetof(hwmgr,
+                                       SMU_SoftRegisters, DRAM_LOG_ADDR_H),
+                                       mc_addr_hi);
+
+       cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
+                                       data->soft_regs_start +
+                                       smum_get_offsetof(hwmgr,
+                                       SMU_SoftRegisters, DRAM_LOG_ADDR_L),
+                                       mc_addr_low);
+
+       cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
+                                       data->soft_regs_start +
+                                       smum_get_offsetof(hwmgr,
+                                       SMU_SoftRegisters, DRAM_LOG_PHY_ADDR_H),
+                                       virtual_addr_hi);
+
+       cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
+                                       data->soft_regs_start +
+                                       smum_get_offsetof(hwmgr,
+                                       SMU_SoftRegisters, DRAM_LOG_PHY_ADDR_L),
+                                       virtual_addr_low);
+
+       cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
+                                       data->soft_regs_start +
+                                       smum_get_offsetof(hwmgr,
+                                       SMU_SoftRegisters, DRAM_LOG_BUFF_SIZE),
+                                       size);
+       return 0;
+}
+
 static const struct pp_hwmgr_func smu7_hwmgr_funcs = {
        .backend_init = &smu7_hwmgr_backend_init,
        .backend_fini = &smu7_hwmgr_backend_fini,
@@ -4696,6 +4737,7 @@ static const struct pp_hwmgr_func smu7_hwmgr_funcs = {
        .avfs_control = smu7_avfs_control,
        .disable_smc_firmware_ctf = smu7_thermal_disable_alert,
        .start_thermal_controller = smu7_start_thermal_controller,
+       .notify_cac_buffer_info = smu7_notify_cac_buffer_info,
 };
 
 uint8_t smu7_get_sleep_divider_id_from_clock(uint32_t clock,
index 7c9aba8..b1b27b2 100644 (file)
@@ -75,6 +75,11 @@ enum SMU_MEMBER {
        VceBootLevel,
        SamuBootLevel,
        LowSclkInterruptThreshold,
+       DRAM_LOG_ADDR_H,
+       DRAM_LOG_ADDR_L,
+       DRAM_LOG_PHY_ADDR_H,
+       DRAM_LOG_PHY_ADDR_L,
+       DRAM_LOG_BUFF_SIZE,
 };
 
 
index 0017b9e..4d672cd 100644 (file)
@@ -2266,6 +2266,16 @@ static uint32_t ci_get_offsetof(uint32_t type, uint32_t member)
                        return offsetof(SMU7_SoftRegisters, PreVBlankGap);
                case VBlankTimeout:
                        return offsetof(SMU7_SoftRegisters, VBlankTimeout);
+               case DRAM_LOG_ADDR_H:
+                       return offsetof(SMU7_SoftRegisters, DRAM_LOG_ADDR_H);
+               case DRAM_LOG_ADDR_L:
+                       return offsetof(SMU7_SoftRegisters, DRAM_LOG_ADDR_L);
+               case DRAM_LOG_PHY_ADDR_H:
+                       return offsetof(SMU7_SoftRegisters, DRAM_LOG_PHY_ADDR_H);
+               case DRAM_LOG_PHY_ADDR_L:
+                       return offsetof(SMU7_SoftRegisters, DRAM_LOG_PHY_ADDR_L);
+               case DRAM_LOG_BUFF_SIZE:
+                       return offsetof(SMU7_SoftRegisters, DRAM_LOG_BUFF_SIZE);
                }
        case SMU_Discrete_DpmTable:
                switch (member) {
index b1a66b5..e130b77 100644 (file)
@@ -2199,6 +2199,16 @@ uint32_t fiji_get_offsetof(uint32_t type, uint32_t member)
                        return offsetof(SMU73_SoftRegisters, VBlankTimeout);
                case UcodeLoadStatus:
                        return offsetof(SMU73_SoftRegisters, UcodeLoadStatus);
+               case DRAM_LOG_ADDR_H:
+                       return offsetof(SMU73_SoftRegisters, DRAM_LOG_ADDR_H);
+               case DRAM_LOG_ADDR_L:
+                       return offsetof(SMU73_SoftRegisters, DRAM_LOG_ADDR_L);
+               case DRAM_LOG_PHY_ADDR_H:
+                       return offsetof(SMU73_SoftRegisters, DRAM_LOG_PHY_ADDR_H);
+               case DRAM_LOG_PHY_ADDR_L:
+                       return offsetof(SMU73_SoftRegisters, DRAM_LOG_PHY_ADDR_L);
+               case DRAM_LOG_BUFF_SIZE:
+                       return offsetof(SMU73_SoftRegisters, DRAM_LOG_BUFF_SIZE);
                }
        case SMU_Discrete_DpmTable:
                switch (member) {
index efb0fc0..da0c93b 100644 (file)
@@ -2125,6 +2125,16 @@ uint32_t iceland_get_offsetof(uint32_t type, uint32_t member)
                        return offsetof(SMU71_SoftRegisters, VBlankTimeout);
                case UcodeLoadStatus:
                        return offsetof(SMU71_SoftRegisters, UcodeLoadStatus);
+               case DRAM_LOG_ADDR_H:
+                       return offsetof(SMU71_SoftRegisters, DRAM_LOG_ADDR_H);
+               case DRAM_LOG_ADDR_L:
+                       return offsetof(SMU71_SoftRegisters, DRAM_LOG_ADDR_L);
+               case DRAM_LOG_PHY_ADDR_H:
+                       return offsetof(SMU71_SoftRegisters, DRAM_LOG_PHY_ADDR_H);
+               case DRAM_LOG_PHY_ADDR_L:
+                       return offsetof(SMU71_SoftRegisters, DRAM_LOG_PHY_ADDR_L);
+               case DRAM_LOG_BUFF_SIZE:
+                       return offsetof(SMU71_SoftRegisters, DRAM_LOG_BUFF_SIZE);
                }
        case SMU_Discrete_DpmTable:
                switch (member) {
index c92ea38..113cadb 100644 (file)
@@ -2190,6 +2190,16 @@ uint32_t polaris10_get_offsetof(uint32_t type, uint32_t member)
                        return offsetof(SMU74_SoftRegisters, VBlankTimeout);
                case UcodeLoadStatus:
                        return offsetof(SMU74_SoftRegisters, UcodeLoadStatus);
+               case DRAM_LOG_ADDR_H:
+                       return offsetof(SMU74_SoftRegisters, DRAM_LOG_ADDR_H);
+               case DRAM_LOG_ADDR_L:
+                       return offsetof(SMU74_SoftRegisters, DRAM_LOG_ADDR_L);
+               case DRAM_LOG_PHY_ADDR_H:
+                       return offsetof(SMU74_SoftRegisters, DRAM_LOG_PHY_ADDR_H);
+               case DRAM_LOG_PHY_ADDR_L:
+                       return offsetof(SMU74_SoftRegisters, DRAM_LOG_PHY_ADDR_L);
+               case DRAM_LOG_BUFF_SIZE:
+                       return offsetof(SMU74_SoftRegisters, DRAM_LOG_BUFF_SIZE);
                }
        case SMU_Discrete_DpmTable:
                switch (member) {
index 1f720cc..6675a85 100644 (file)
@@ -2668,6 +2668,16 @@ uint32_t tonga_get_offsetof(uint32_t type, uint32_t member)
                        return offsetof(SMU72_SoftRegisters, VBlankTimeout);
                case UcodeLoadStatus:
                        return offsetof(SMU72_SoftRegisters, UcodeLoadStatus);
+               case DRAM_LOG_ADDR_H:
+                       return offsetof(SMU72_SoftRegisters, DRAM_LOG_ADDR_H);
+               case DRAM_LOG_ADDR_L:
+                       return offsetof(SMU72_SoftRegisters, DRAM_LOG_ADDR_L);
+               case DRAM_LOG_PHY_ADDR_H:
+                       return offsetof(SMU72_SoftRegisters, DRAM_LOG_PHY_ADDR_H);
+               case DRAM_LOG_PHY_ADDR_L:
+                       return offsetof(SMU72_SoftRegisters, DRAM_LOG_PHY_ADDR_L);
+               case DRAM_LOG_BUFF_SIZE:
+                       return offsetof(SMU72_SoftRegisters, DRAM_LOG_BUFF_SIZE);
                }
        case SMU_Discrete_DpmTable:
                switch (member) {