[VM][PC9801] Fix FTBFS with PC9801V*.

[VM][PC9801] Enable SASI BIOS at reset.

diff --git a/source/src/vm/memory.cpp b/source/src/vm/memory.cpp
index 8858a0c..1e8c7df 100644 (file)
--- a/source/src/vm/memory.cpp
+++ b/source/src/vm/memory.cpp
@@ -16,7 +16,7 @@ void MEMORY::initialize()
 {
        // allocate tables here to support multiple instances with different address range
        if(rd_table == NULL) {
-               int bank_num = addr_max / bank_size;
+               int64_t bank_num = addr_max / bank_size;
                
                rd_dummy = (uint8_t *)malloc(bank_size);
                wr_dummy = (uint8_t *)malloc(bank_size);
@@ -34,7 +34,7 @@ void MEMORY::initialize()
                        rd_table[i].wait = 0;
                }
                for(int i = 0;; i++) {
-                       if(bank_size == (1 << i)) {
+                       if(bank_size == (int64_t)(1 << i)) {
                                addr_shift = i;
                                break;
                        }

diff --git a/source/src/vm/memory.h b/source/src/vm/memory.h
index 7bd57e0..dd1d27e 100644 (file)
--- a/source/src/vm/memory.h
+++ b/source/src/vm/memory.h
@@ -117,8 +117,8 @@ public:
        bool read_image(const _TCHAR *file_path, uint8_t *buffer, int size);
        bool write_image(const _TCHAR *file_path, uint8_t *buffer, int size);
        
-       int addr_max;
-       int bank_size;
+       int64_t addr_max;
+       int64_t bank_size;
 };
 
 #endif

diff --git a/source/src/vm/pc9801/membus.cpp b/source/src/vm/pc9801/membus.cpp
index 1a2acca..b37a475 100644 (file)
--- a/source/src/vm/pc9801/membus.cpp
+++ b/source/src/vm/pc9801/membus.cpp
@@ -183,7 +183,7 @@ void MEMBUS::reset()
 
        // SASI
 #if defined(SUPPORT_SASI_IF)
-       sasi_bios_selected = false;
+       sasi_bios_selected = true;
        sasi_bios_ram_selected = false; // OK?
 #endif
        // SASI
@@ -756,7 +756,7 @@ void MEMBUS::update_bios()
        #if defined(SUPPORT_16_COLORS)
        set_memory_mapped_io_rw(0xe0000, 0xe7fff, d_display);
        #endif
-       #if defined(SUPPORT_32BIT_ADDRESS) || defined(SUPPORT_24BIT_ADDRESS)
+       #if defined(SUPPORT_32BIT_ADDRESS)
        if(is_shadow_bank_a0000h) {
                set_memory_rw(0xa0000, 0xbffff, &(shadow_bank_i386_80000h[0x20000]));
        }// else {
@@ -770,13 +770,13 @@ void MEMBUS::update_bios()
        set_memory_r(0xd6000, 0xd6fff, fd_bios_2dd);
        set_memory_r(0xd7000, 0xd7fff, fd_bios_2hd);
 #endif
-#if defined(SUPPORT_BIOS_RAM)
+//#if defined(SUPPORT_BIOS_RAM)
        #if defined(SUPPORT_32BIT_ADDRESS)
        if(is_shadow_bank_80000h) {
                set_memory_rw(0x80000, 0x9ffff, &(shadow_bank_i386_80000h[0x00000]));
-       }// else {
-       //      set_memory_rw(0x80000, 0x9ffff, &(ram[0x80000]));
-       //}             
+       } else {
+               set_memory_rw(0x80000, 0x9ffff, &(ram[0x80000]));
+       }               
        #endif
        #if defined(SUPPORT_32BIT_ADDRESS) || defined(SUPPORT_24BIT_ADDRESS)
        #if !defined(SUPPORT_HIRESO)
@@ -788,9 +788,12 @@ void MEMBUS::update_bios()
        #else
        unset_memory_rw(0xc0000, 0xe7fff);
        #endif
+       #if defined(SUPPORT_BIOS_RAM)
        if(shadow_ram_selected) {
                set_memory_rw(0xc0000, 0xe7fff, shadow_ram);
-       } else {
+       } else
+       #endif
+       {
                #if defined(SUPPORT_HIRESO)
                set_memory_mapped_io_rw(0xe0000, 0xe4fff, d_display);
                #else           
@@ -808,7 +811,7 @@ void MEMBUS::update_bios()
                #endif
        }
        #endif
-#endif
+//#endif
        
 #if defined(SUPPORT_ITF_ROM)
        if(itf_selected) {