i40e: Use the new rx ctl register helpers. Don't use AQ calls from clear_hw.

Use the new AdminQ functions for safely accessing the Rx control
registers that may be affected by heavy small packet traffic.

We can't use AdminQ calls in i40e_clear_hw() because the HW is being
initialized and the AdminQ is not alive.  We recently added an AQ
related replacement for reading PFLAN_QALLOC, and this patch puts
back the original register read.

Change-ID: Ib027168c954a5733299aa3a4ce5f8218c6bb5636
Signed-off-by: Shannon Nelson <shannon.nelson@intel.com>
Tested-by: Andrew Bowers <andrewx.bowers@intel.com>
Signed-off-by: Jeff Kirsher <jeffrey.t.kirsher@intel.com>

diff --git a/drivers/net/ethernet/intel/i40e/i40e_common.c b/drivers/net/ethernet/intel/i40e/i40e_common.c
index 74d9599..4596294 100644 (file)
--- a/drivers/net/ethernet/intel/i40e/i40e_common.c
+++ b/drivers/net/ethernet/intel/i40e/i40e_common.c
@@ -1328,7 +1328,7 @@ void i40e_clear_hw(struct i40e_hw *hw)
        num_vf_int = (val & I40E_GLPCI_CNF2_MSI_X_VF_N_MASK) >>
                     I40E_GLPCI_CNF2_MSI_X_VF_N_SHIFT;
 
-       val = i40e_read_rx_ctl(hw, I40E_PFLAN_QALLOC);
+       val = rd32(hw, I40E_PFLAN_QALLOC);
        base_queue = (val & I40E_PFLAN_QALLOC_FIRSTQ_MASK) >>
                     I40E_PFLAN_QALLOC_FIRSTQ_SHIFT;
        j = (val & I40E_PFLAN_QALLOC_LASTQ_MASK) >>

diff --git a/drivers/net/ethernet/intel/i40e/i40e_ethtool.c b/drivers/net/ethernet/intel/i40e/i40e_ethtool.c
index f1ad101..a85bc94 100644 (file)
--- a/drivers/net/ethernet/intel/i40e/i40e_ethtool.c
+++ b/drivers/net/ethernet/intel/i40e/i40e_ethtool.c
@@ -2181,8 +2181,8 @@ static int i40e_get_rxnfc(struct net_device *netdev, struct ethtool_rxnfc *cmd,
 static int i40e_set_rss_hash_opt(struct i40e_pf *pf, struct ethtool_rxnfc *nfc)
 {
        struct i40e_hw *hw = &pf->hw;
-       u64 hena = (u64)rd32(hw, I40E_PFQF_HENA(0)) |
-                  ((u64)rd32(hw, I40E_PFQF_HENA(1)) << 32);
+       u64 hena = (u64)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(0)) |
+                  ((u64)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(1)) << 32);
 
        /* RSS does not support anything other than hashing
         * to queues on src and dst IPs and ports
@@ -2291,8 +2291,8 @@ static int i40e_set_rss_hash_opt(struct i40e_pf *pf, struct ethtool_rxnfc *nfc)
                return -EINVAL;
        }
 
-       wr32(hw, I40E_PFQF_HENA(0), (u32)hena);
-       wr32(hw, I40E_PFQF_HENA(1), (u32)(hena >> 32));
+       i40e_write_rx_ctl(hw, I40E_PFQF_HENA(0), (u32)hena);
+       i40e_write_rx_ctl(hw, I40E_PFQF_HENA(1), (u32)(hena >> 32));
        i40e_flush(hw);
 
        /* Save setting for future output/update */

diff --git a/drivers/net/ethernet/intel/i40e/i40e_fcoe.c b/drivers/net/ethernet/intel/i40e/i40e_fcoe.c
index 052df93..8ad162c 100644 (file)
--- a/drivers/net/ethernet/intel/i40e/i40e_fcoe.c
+++ b/drivers/net/ethernet/intel/i40e/i40e_fcoe.c
@@ -295,11 +295,11 @@ void i40e_init_pf_fcoe(struct i40e_pf *pf)
        }
 
        /* enable FCoE hash filter */
-       val = rd32(hw, I40E_PFQF_HENA(1));
+       val = i40e_read_rx_ctl(hw, I40E_PFQF_HENA(1));
        val |= BIT(I40E_FILTER_PCTYPE_FCOE_OX - 32);
        val |= BIT(I40E_FILTER_PCTYPE_FCOE_RX - 32);
        val &= I40E_PFQF_HENA_PTYPE_ENA_MASK;
-       wr32(hw, I40E_PFQF_HENA(1), val);
+       i40e_write_rx_ctl(hw, I40E_PFQF_HENA(1), val);
 
        /* enable flag */
        pf->flags |= I40E_FLAG_FCOE_ENABLED;
@@ -317,11 +317,11 @@ void i40e_init_pf_fcoe(struct i40e_pf *pf)
        pf->filter_settings.fcoe_cntx_num = I40E_DMA_CNTX_SIZE_4K;
 
        /* Setup max frame with FCoE_MTU plus L2 overheads */
-       val = rd32(hw, I40E_GLFCOE_RCTL);
+       val = i40e_read_rx_ctl(hw, I40E_GLFCOE_RCTL);
        val &= ~I40E_GLFCOE_RCTL_MAX_SIZE_MASK;
        val |= ((FCOE_MTU + ETH_HLEN + VLAN_HLEN + ETH_FCS_LEN)
                 << I40E_GLFCOE_RCTL_MAX_SIZE_SHIFT);
-       wr32(hw, I40E_GLFCOE_RCTL, val);
+       i40e_write_rx_ctl(hw, I40E_GLFCOE_RCTL, val);
 
        dev_info(&pf->pdev->dev, "FCoE is supported.\n");
 }

diff --git a/drivers/net/ethernet/intel/i40e/i40e_main.c b/drivers/net/ethernet/intel/i40e/i40e_main.c
index 3ff3e83..87325db 100644 (file)
--- a/drivers/net/ethernet/intel/i40e/i40e_main.c
+++ b/drivers/net/ethernet/intel/i40e/i40e_main.c
@@ -8032,7 +8032,7 @@ static int i40e_config_rss_reg(struct i40e_vsi *vsi, const u8 *seed,
                u32 *seed_dw = (u32 *)seed;
 
                for (i = 0; i <= I40E_PFQF_HKEY_MAX_INDEX; i++)
-                       wr32(hw, I40E_PFQF_HKEY(i), seed_dw[i]);
+                       i40e_write_rx_ctl(hw, I40E_PFQF_HKEY(i), seed_dw[i]);
        }
 
        if (lut) {
@@ -8069,7 +8069,7 @@ static int i40e_get_rss_reg(struct i40e_vsi *vsi, u8 *seed,
                u32 *seed_dw = (u32 *)seed;
 
                for (i = 0; i <= I40E_PFQF_HKEY_MAX_INDEX; i++)
-                       seed_dw[i] = rd32(hw, I40E_PFQF_HKEY(i));
+                       seed_dw[i] = i40e_read_rx_ctl(hw, I40E_PFQF_HKEY(i));
        }
        if (lut) {
                u32 *lut_dw = (u32 *)lut;
@@ -8152,19 +8152,19 @@ static int i40e_pf_config_rss(struct i40e_pf *pf)
        int ret;
 
        /* By default we enable TCP/UDP with IPv4/IPv6 ptypes */
-       hena = (u64)rd32(hw, I40E_PFQF_HENA(0)) |
-               ((u64)rd32(hw, I40E_PFQF_HENA(1)) << 32);
+       hena = (u64)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(0)) |
+               ((u64)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(1)) << 32);
        hena |= i40e_pf_get_default_rss_hena(pf);
 
-       wr32(hw, I40E_PFQF_HENA(0), (u32)hena);
-       wr32(hw, I40E_PFQF_HENA(1), (u32)(hena >> 32));
+       i40e_write_rx_ctl(hw, I40E_PFQF_HENA(0), (u32)hena);
+       i40e_write_rx_ctl(hw, I40E_PFQF_HENA(1), (u32)(hena >> 32));
 
        /* Determine the RSS table size based on the hardware capabilities */
-       reg_val = rd32(hw, I40E_PFQF_CTL_0);
+       reg_val = i40e_read_rx_ctl(hw, I40E_PFQF_CTL_0);
        reg_val = (pf->rss_table_size == 512) ?
                        (reg_val | I40E_PFQF_CTL_0_HASHLUTSIZE_512) :
                        (reg_val & ~I40E_PFQF_CTL_0_HASHLUTSIZE_512);
-       wr32(hw, I40E_PFQF_CTL_0, reg_val);
+       i40e_write_rx_ctl(hw, I40E_PFQF_CTL_0, reg_val);
 
        /* Determine the RSS size of the VSI */
        if (!vsi->rss_size)
@@ -11211,8 +11211,8 @@ static void i40e_remove(struct pci_dev *pdev)
        i40e_ptp_stop(pf);
 
        /* Disable RSS in hw */
-       wr32(hw, I40E_PFQF_HENA(0), 0);
-       wr32(hw, I40E_PFQF_HENA(1), 0);
+       i40e_write_rx_ctl(hw, I40E_PFQF_HENA(0), 0);
+       i40e_write_rx_ctl(hw, I40E_PFQF_HENA(1), 0);
 
        /* no more scheduling of any task */
        set_bit(__I40E_DOWN, &pf->state);

diff --git a/drivers/net/ethernet/intel/i40e/i40e_virtchnl_pf.c b/drivers/net/ethernet/intel/i40e/i40e_virtchnl_pf.c
index 5dcd198..93d8d98 100644 (file)
--- a/drivers/net/ethernet/intel/i40e/i40e_virtchnl_pf.c
+++ b/drivers/net/ethernet/intel/i40e/i40e_virtchnl_pf.c
@@ -602,8 +602,8 @@ static void i40e_enable_vf_mappings(struct i40e_vf *vf)
         * that VF queues be mapped using this method, even when they are
         * contiguous in real life
         */
-       wr32(hw, I40E_VSILAN_QBASE(vf->lan_vsi_id),
-            I40E_VSILAN_QBASE_VSIQTABLE_ENA_MASK);
+       i40e_write_rx_ctl(hw, I40E_VSILAN_QBASE(vf->lan_vsi_id),
+                         I40E_VSILAN_QBASE_VSIQTABLE_ENA_MASK);
 
        /* enable VF vplan_qtable mappings */
        reg = I40E_VPLAN_MAPENA_TXRX_ENA_MASK;
@@ -630,7 +630,8 @@ static void i40e_enable_vf_mappings(struct i40e_vf *vf)
                                                      (j * 2) + 1);
                        reg |= qid << 16;
                }
-               wr32(hw, I40E_VSILAN_QTABLE(j, vf->lan_vsi_id), reg);
+               i40e_write_rx_ctl(hw, I40E_VSILAN_QTABLE(j, vf->lan_vsi_id),
+                                 reg);
        }
 
        i40e_flush(hw);