drm/amdgpu/gmc9: add vega12 support (v2)

Same as vega10.

v2: squash in golden regs fix from Feifei

Acked-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Feifei Xu <Feifei.Xu@amd.com>

diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c b/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
index a70cbc4..e687363 100644 (file)
--- a/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
@@ -791,6 +791,7 @@ static int gmc_v9_0_mc_init(struct amdgpu_device *adev)
        if (amdgpu_gart_size == -1) {
                switch (adev->asic_type) {
                case CHIP_VEGA10:  /* all engines support GPUVM */
+               case CHIP_VEGA12:  /* all engines support GPUVM */
                default:
                        adev->gmc.gart_size = 512ULL << 20;
                        break;
@@ -849,6 +850,7 @@ static int gmc_v9_0_sw_init(void *handle)
                }
                break;
        case CHIP_VEGA10:
+       case CHIP_VEGA12:
                /*
                 * To fulfill 4-level page support,
                 * vm size is 256TB (48bit), maximum size of Vega10,
@@ -965,6 +967,8 @@ static void gmc_v9_0_init_golden_registers(struct amdgpu_device *adev)
                                                golden_settings_athub_1_0_0,
                                                ARRAY_SIZE(golden_settings_athub_1_0_0));
                break;
+       case CHIP_VEGA12:
+               break;
        case CHIP_RAVEN:
                soc15_program_register_sequence(adev,
                                                golden_settings_athub_1_0_0,