phy: phy-brcm-usb-init: Some Low Speed keyboards fail on 7271

Enable the the Low Speed Keep Alive signal on the 7271b0 by setting
the LS_KEEP_ALIVE bit in the USB CTRL OBRIDGE register otherwise
some Dell Low Speed keyboards fail.

Also do a little cleanup of the EBRIDGE ESTOP_SCB_REQ bit. Since
this is only used on one platform, remove it from the platform
tables and just use "if (family == ").

Fixes: 49859e55e364 ("phy: usb: phy-brcm-usb: Add Broadcom STB USB phy driver")
Signed-off-by: Al Cooper <alcooperx@gmail.com>
Acked-by: Florian Fainelli <f.fainelli@gmail.com>
Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>

diff --git a/drivers/phy/broadcom/phy-brcm-usb-init.c b/drivers/phy/broadcom/phy-brcm-usb-init.c
index 1e7ce0b..69ea479 100644 (file)
--- a/drivers/phy/broadcom/phy-brcm-usb-init.c
+++ b/drivers/phy/broadcom/phy-brcm-usb-init.c
@@ -50,6 +50,8 @@
 #define   USB_CTRL_PLL_CTL_PLL_IDDQ_PWRDN_MASK         0x80000000 /* option */
 #define USB_CTRL_EBRIDGE               0x0c
 #define   USB_CTRL_EBRIDGE_ESTOP_SCB_REQ_MASK          0x00020000 /* option */
+#define USB_CTRL_OBRIDGE               0x10
+#define   USB_CTRL_OBRIDGE_LS_KEEP_ALIVE_MASK          0x08000000
 #define USB_CTRL_MDIO                  0x14
 #define USB_CTRL_MDIO2                 0x18
 #define USB_CTRL_UTMI_CTL_1            0x2c
@@ -116,7 +118,6 @@ enum {
        USB_CTRL_SETUP_STRAP_IPP_SEL_SELECTOR,
        USB_CTRL_SETUP_OC3_DISABLE_SELECTOR,
        USB_CTRL_PLL_CTL_PLL_IDDQ_PWRDN_SELECTOR,
-       USB_CTRL_EBRIDGE_ESTOP_SCB_REQ_SELECTOR,
        USB_CTRL_USB_PM_BDC_SOFT_RESETB_SELECTOR,
        USB_CTRL_USB_PM_XHC_SOFT_RESETB_SELECTOR,
        USB_CTRL_USB_PM_USB_PWRDN_SELECTOR,
@@ -203,7 +204,6 @@ usb_reg_bits_map_table[BRCM_FAMILY_COUNT][USB_CTRL_SELECTOR_COUNT] = {
                USB_CTRL_SETUP_STRAP_IPP_SEL_MASK,
                USB_CTRL_SETUP_OC3_DISABLE_MASK,
                0, /* USB_CTRL_PLL_CTL_PLL_IDDQ_PWRDN_MASK */
-               USB_CTRL_EBRIDGE_ESTOP_SCB_REQ_MASK,
                0, /* USB_CTRL_USB_PM_BDC_SOFT_RESETB_MASK */
                USB_CTRL_USB_PM_XHC_SOFT_RESETB_MASK,
                USB_CTRL_USB_PM_USB_PWRDN_MASK,
@@ -225,7 +225,6 @@ usb_reg_bits_map_table[BRCM_FAMILY_COUNT][USB_CTRL_SELECTOR_COUNT] = {
                0, /* USB_CTRL_SETUP_STRAP_IPP_SEL_MASK */
                USB_CTRL_SETUP_OC3_DISABLE_MASK,
                USB_CTRL_PLL_CTL_PLL_IDDQ_PWRDN_MASK,
-               USB_CTRL_EBRIDGE_ESTOP_SCB_REQ_MASK,
                0, /* USB_CTRL_USB_PM_BDC_SOFT_RESETB_MASK */
                USB_CTRL_USB_PM_XHC_SOFT_RESETB_VAR_MASK,
                0, /* USB_CTRL_USB_PM_USB_PWRDN_MASK */
@@ -247,7 +246,6 @@ usb_reg_bits_map_table[BRCM_FAMILY_COUNT][USB_CTRL_SELECTOR_COUNT] = {
                USB_CTRL_SETUP_STRAP_IPP_SEL_MASK,
                USB_CTRL_SETUP_OC3_DISABLE_MASK,
                0, /* USB_CTRL_PLL_CTL_PLL_IDDQ_PWRDN_MASK */
-               USB_CTRL_EBRIDGE_ESTOP_SCB_REQ_MASK,
                USB_CTRL_USB_PM_BDC_SOFT_RESETB_MASK,
                USB_CTRL_USB_PM_XHC_SOFT_RESETB_MASK,
                USB_CTRL_USB_PM_USB_PWRDN_MASK,
@@ -269,7 +267,6 @@ usb_reg_bits_map_table[BRCM_FAMILY_COUNT][USB_CTRL_SELECTOR_COUNT] = {
                0, /* USB_CTRL_SETUP_STRAP_IPP_SEL_MASK */
                USB_CTRL_SETUP_OC3_DISABLE_MASK,
                USB_CTRL_PLL_CTL_PLL_IDDQ_PWRDN_MASK,
-               USB_CTRL_EBRIDGE_ESTOP_SCB_REQ_MASK,
                0, /* USB_CTRL_USB_PM_BDC_SOFT_RESETB_MASK */
                USB_CTRL_USB_PM_XHC_SOFT_RESETB_VAR_MASK,
                0, /* USB_CTRL_USB_PM_USB_PWRDN_MASK */
@@ -291,7 +288,6 @@ usb_reg_bits_map_table[BRCM_FAMILY_COUNT][USB_CTRL_SELECTOR_COUNT] = {
                0, /* USB_CTRL_SETUP_STRAP_IPP_SEL_MASK */
                USB_CTRL_SETUP_OC3_DISABLE_MASK,
                0, /* USB_CTRL_PLL_CTL_PLL_IDDQ_PWRDN_MASK */
-               USB_CTRL_EBRIDGE_ESTOP_SCB_REQ_MASK,
                0, /* USB_CTRL_USB_PM_BDC_SOFT_RESETB_MASK */
                USB_CTRL_USB_PM_XHC_SOFT_RESETB_VAR_MASK,
                USB_CTRL_USB_PM_USB_PWRDN_MASK,
@@ -313,7 +309,6 @@ usb_reg_bits_map_table[BRCM_FAMILY_COUNT][USB_CTRL_SELECTOR_COUNT] = {
                0, /* USB_CTRL_SETUP_STRAP_IPP_SEL_MASK */
                0, /* USB_CTRL_SETUP_OC3_DISABLE_MASK */
                USB_CTRL_PLL_CTL_PLL_IDDQ_PWRDN_MASK,
-               0, /* USB_CTRL_EBRIDGE_ESTOP_SCB_REQ_MASK */
                0, /* USB_CTRL_USB_PM_BDC_SOFT_RESETB_MASK */
                0, /* USB_CTRL_USB_PM_XHC_SOFT_RESETB_MASK */
                0, /* USB_CTRL_USB_PM_USB_PWRDN_MASK */
@@ -335,7 +330,6 @@ usb_reg_bits_map_table[BRCM_FAMILY_COUNT][USB_CTRL_SELECTOR_COUNT] = {
                USB_CTRL_SETUP_STRAP_IPP_SEL_MASK,
                USB_CTRL_SETUP_OC3_DISABLE_MASK,
                0, /* USB_CTRL_PLL_CTL_PLL_IDDQ_PWRDN_MASK */
-               0, /* USB_CTRL_EBRIDGE_ESTOP_SCB_REQ_MASK */
                USB_CTRL_USB_PM_BDC_SOFT_RESETB_MASK,
                USB_CTRL_USB_PM_XHC_SOFT_RESETB_MASK,
                USB_CTRL_USB_PM_USB_PWRDN_MASK,
@@ -357,7 +351,6 @@ usb_reg_bits_map_table[BRCM_FAMILY_COUNT][USB_CTRL_SELECTOR_COUNT] = {
                0, /* USB_CTRL_SETUP_STRAP_IPP_SEL_MASK */
                USB_CTRL_SETUP_OC3_DISABLE_MASK,
                USB_CTRL_PLL_CTL_PLL_IDDQ_PWRDN_MASK,
-               0, /* USB_CTRL_EBRIDGE_ESTOP_SCB_REQ_MASK */
                0, /* USB_CTRL_USB_PM_BDC_SOFT_RESETB_MASK */
                0, /* USB_CTRL_USB_PM_XHC_SOFT_RESETB_MASK */
                0, /* USB_CTRL_USB_PM_USB_PWRDN_MASK */
@@ -379,7 +372,6 @@ usb_reg_bits_map_table[BRCM_FAMILY_COUNT][USB_CTRL_SELECTOR_COUNT] = {
                USB_CTRL_SETUP_STRAP_IPP_SEL_MASK,
                USB_CTRL_SETUP_OC3_DISABLE_MASK,
                0, /* USB_CTRL_PLL_CTL_PLL_IDDQ_PWRDN_MASK */
-               USB_CTRL_EBRIDGE_ESTOP_SCB_REQ_MASK,
                USB_CTRL_USB_PM_BDC_SOFT_RESETB_MASK,
                USB_CTRL_USB_PM_XHC_SOFT_RESETB_MASK,
                USB_CTRL_USB_PM_USB_PWRDN_MASK,
@@ -401,7 +393,6 @@ usb_reg_bits_map_table[BRCM_FAMILY_COUNT][USB_CTRL_SELECTOR_COUNT] = {
                USB_CTRL_SETUP_STRAP_IPP_SEL_MASK,
                USB_CTRL_SETUP_OC3_DISABLE_MASK,
                0, /* USB_CTRL_PLL_CTL_PLL_IDDQ_PWRDN_MASK */
-               USB_CTRL_EBRIDGE_ESTOP_SCB_REQ_MASK,
                USB_CTRL_USB_PM_BDC_SOFT_RESETB_MASK,
                USB_CTRL_USB_PM_XHC_SOFT_RESETB_MASK,
                USB_CTRL_USB_PM_USB_PWRDN_MASK,
@@ -952,13 +943,17 @@ void brcm_usb_init_eohci(struct brcm_usb_init_params *params)
                 * Don't enable this so the memory controller doesn't read
                 * into memory holes. NOTE: This bit is low true on 7366C0.
                 */
-               USB_CTRL_SET_FAMILY(params, EBRIDGE, ESTOP_SCB_REQ);
+               USB_CTRL_SET(ctrl, EBRIDGE, ESTOP_SCB_REQ);
 
        /* Setup the endian bits */
        reg = brcmusb_readl(USB_CTRL_REG(ctrl, SETUP));
        reg &= ~USB_CTRL_SETUP_ENDIAN_BITS;
        reg |= USB_CTRL_MASK_FAMILY(params, SETUP, ENDIAN);
        brcmusb_writel(reg, USB_CTRL_REG(ctrl, SETUP));
+
+       if (params->selected_family == BRCM_FAMILY_7271A0)
+               /* Enable LS keep alive fix for certain keyboards */
+               USB_CTRL_SET(ctrl, OBRIDGE, LS_KEEP_ALIVE);
 }
 
 void brcm_usb_init_xhci(struct brcm_usb_init_params *params)