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drm/exynos: gsc: Increase Exynos5433 buffer width alignment to 16 pixels
author
Marek Szyprowski
<m.szyprowski@samsung.com>
Thu, 7 Jun 2018 11:06:11 +0000
(13:06 +0200)
committer
Inki Dae
<inki.dae@samsung.com>
Fri, 29 Jun 2018 09:02:57 +0000
(18:02 +0900)
Investigation revealed that GScaler hardware requires the real buffer width
(pitch) to be aligned to 16 pixels.
Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com>
Signed-off-by: Inki Dae <inki.dae@samsung.com>
drivers/gpu/drm/exynos/exynos_drm_gsc.c
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diff --git
a/drivers/gpu/drm/exynos/exynos_drm_gsc.c
b/drivers/gpu/drm/exynos/exynos_drm_gsc.c
index
8af7f16
..
2463007
100644
(file)
--- a/
drivers/gpu/drm/exynos/exynos_drm_gsc.c
+++ b/
drivers/gpu/drm/exynos/exynos_drm_gsc.c
@@
-1341,7
+1341,7
@@
static const struct drm_exynos_ipp_limit gsc_5420_limits[] = {
};
static const struct drm_exynos_ipp_limit gsc_5433_limits[] = {
- { IPP_SIZE_LIMIT(BUFFER, .h = { 32, 8191,
2
}, .v = { 16, 8191, 2 }) },
+ { IPP_SIZE_LIMIT(BUFFER, .h = { 32, 8191,
16
}, .v = { 16, 8191, 2 }) },
{ IPP_SIZE_LIMIT(AREA, .h = { 16, 4800, 1 }, .v = { 8, 3344, 1 }) },
{ IPP_SIZE_LIMIT(ROTATED, .h = { 32, 2047 }, .v = { 8, 8191 }) },
{ IPP_SCALE_LIMIT(.h = { (1 << 16) / 16, (1 << 16) * 8 },