- address decoder bug fixed.
- ram i/o ok.
signal rom_ce_n : std_logic;
signal ram_ce_n : std_logic;
- signal ram_we_n : std_logic;
+ signal ram_oe_n : std_logic;
signal rom_out : std_logic_vector (dsize - 1 downto 0);
signal ram_io : std_logic_vector (dsize - 1 downto 0);
romport : prg_rom generic map (rom_32k, dsize)
port map (rom_ce_n, addr(rom_32k - 1 downto 0), rom_out);
- ram_we_n <= not R_nW;
+ ram_oe_n <= not R_nW;
ramport : ram generic map (ram_2k, dsize)
- port map (ram_ce_n, ram_we_n, R_nW,
+ port map (ram_ce_n, ram_oe_n, R_nW,
addr(ram_2k - 1 downto 0), ram_io);
rom_ce_n <= '0' when (addr(15) = '1' and R_nW = '1') else
when (r_nw = '0' and ((addr(15) or addr(14) or addr(13)) = '0')) else
"ZZZZZZZZ";
- main_p : process (phi2)
+ main_p : process (phi2, addr, R_nW)
begin
-- ram range : 0 - 0x2000.
-- 0x2000 is 0010_0000_0000_0000
- if ((addr(15) or addr(14) or addr(13)) = '1') then
- ram_ce_n <= '1';
- else
+ if (addr < "0010000000000000") then
if (R_nW = '0') then
--write
--write timing slided by half clock.
end if;
elsif (R_nW = '1') then
--read
- if (phi2'event and phi2 = '0') then
- ram_ce_n <= '0';
- end if;
+ ram_ce_n <= '0';
else
ram_ce_n <= '1';
end if;
+ --if ((addr(15) or addr(14) or addr(13)) = '1') then
+ else
+ ram_ce_n <= '1';
end if;
end process;
);
end component;
signal oe_n : std_logic;
+signal dff_we_n : std_logic;
signal q : std_logic_vector (dsize - 1 downto 0);
signal d : std_logic_vector (dsize - 1 downto 0);
signal q_buf : std_logic_vector (dsize - 1 downto 0);
begin
oe_n <= (int_d_oe_n and int_a_oe_n);
+ dff_we_n <= (we_n and push_n and pop_n);
int_dbus <= q when int_d_oe_n = '0' else
(others =>'Z');
-- int_abus_l <= q when int_a_oe_n = '0' else
-- (others =>'Z');
---push: address decrement after push is done.
+ ---pop: address increment before pop is done.
al_p : process (int_a_oe_n, push_n, clk, q_buf, q)
begin
if (int_a_oe_n = '0') then
else
int_abus_l <= q;
end if;
+ elsif (pop_n = '0') then
+ if (clk = '1') then
+ int_abus_l <= q;
+ else
+ int_abus_l <= q + 1;
+ end if;
else
int_abus_l <= q;
end if;
int_abus_h <= "00000001" when int_a_oe_n = '0' else
(others =>'Z');
- d <= int_dbus when we_n = '0' and push_n /= '0' else
- (q - 1) when we_n = '0' and push_n = '0' else
+ d <= int_dbus when we_n = '0' else
+ (q - 1) when push_n = '0' else
+ (q + 1) when pop_n = '0' else
(others =>'Z');
dff_inst : dff generic map (dsize)
- port map(clk, we_n, oe_n, d, q);
+ port map(clk, dff_we_n, oe_n, d, q);
buf : dff generic map (dsize)
- port map(clk, we_n, '0', q, q_buf);
+ port map(clk, dff_we_n, '0', q, q_buf);
end rtl;
pcl_a_oe_n <= '0';
pch_a_oe_n <= '0';
inst_we_n <= '0';
+ pc_inc_n <= '0';
+
x_we_n <= '1';
sp_we_n <= '1';
sp_push_n <= '1';
sp_pop_n <= '1';
x_oe_n <= '1';
r_nw <= '1';
- pc_inc_n <= '0';
dbuf_int_oe_n <= '1';
stat_dec_we_n <= '1';
stat_bus_we_n <= '1';
dl_we_n <= '1';
dl_int_al_oe_n <= '1';
pcl_d_we_n <= '1';
+
cur_status <= decode;
---for debug....
pc_inc_n <= '1';
else
- pcl_a_oe_n <= '0';
- pch_a_oe_n <= '0';
- pc_inc_n <= '0';
- dbuf_int_oe_n <= '0';
-
if instruction = conv_std_logic_vector(16#00#, dsize) then
d_print("brk");
elsif instruction = conv_std_logic_vector(16#20#, dsize) then
d_print("jsr abs 2");
--fetch opcode.
+ pcl_a_oe_n <= '0';
+ pch_a_oe_n <= '0';
+ pc_inc_n <= '0';
+ dbuf_int_oe_n <= '0';
+ --latch data
dl_we_n <= '0';
cur_status <= exec2;
d_print("40");
elsif instruction = conv_std_logic_vector(16#60#, dsize) then
d_print("rts 2");
+ pcl_a_oe_n <= '1';
+ pch_a_oe_n <= '1';
+ pc_inc_n <= '1';
+ --pop pcl
+ sp_int_a_oe_n <= '0';
+ sp_pop_n <= '0';
+ --latch data
+ --dbuf_int_oe_n <= '0';
+ --dl_we_n <= '0';
+ --cur_status <= exec2;
elsif instruction (4 downto 0) = "10000" then
---conditional branch instruction..
---addressing mode identifier
cur_mode := decode_addr_mode(instruction);
+ pcl_a_oe_n <= '0';
+ pch_a_oe_n <= '0';
+ pc_inc_n <= '0';
+ dbuf_int_oe_n <= '0';
+
if cur_mode = ad_imm then
d_print("immediate");
cur_status <= fetch;
--pch <= (pc + 2)
--push return addr high into stack.
- sp_we_n <= '0';
sp_push_n <= '0';
pch_d_oe_n <= '0';
sp_int_a_oe_n <= '0';
--push return addr low into stack.
pch_d_oe_n <= '1';
- sp_we_n <= '0';
sp_push_n <= '0';
pcl_d_oe_n <= '0';
sp_int_a_oe_n <= '0';
if instruction = conv_std_logic_vector(16#00#, dsize) then
elsif instruction = conv_std_logic_vector(16#20#, dsize) then
d_print("jsr 5");
- sp_we_n <= '1';
sp_push_n <= '1';
pcl_d_oe_n <= '1';
sp_int_a_oe_n <= '1';
pc_cry_n, pc_cry, dum_terminate, internal_dbus, internal_abus_h);
dec_inst : decoder generic map (dsize)
- port map(set_clk, trigger_clk, rst_n, irq_n, nmi_n,
- rdy, instruction, status_reg, ad_oe_n,
- pcl_d_we_n, pcl_a_we_n, pcl_d_oe_n, pcl_a_oe_n,
- pch_d_we_n, pch_a_we_n, pch_d_oe_n, pch_a_oe_n,
+ port map(set_clk,
+ trigger_clk,
+ rst_n,
+ irq_n,
+ nmi_n,
+ rdy,
+ instruction,
+ status_reg,
+ ad_oe_n,
+ pcl_d_we_n,
+ pcl_a_we_n,
+ pcl_d_oe_n,
+ pcl_a_oe_n,
+ pch_d_we_n,
+ pch_a_we_n,
+ pch_d_oe_n,
+ pch_a_oe_n,
pc_inc_n,
inst_we_n,
dbuf_int_oe_n,
- dl_we_n, dl_int_d_oe_n, dl_int_al_oe_n, dl_int_ah_oe_n,
- sp_we_n, sp_push_n, sp_pop_n, sp_int_d_oe_n, sp_int_a_oe_n,
- x_we_n, x_oe_n, y_we_n, y_oe_n,
- stat_dec_we_n, stat_dec_oe_n, stat_bus_we_n, stat_bus_oe_n,
- dbuf_r_nw);
+ dl_we_n,
+ dl_int_d_oe_n,
+ dl_int_al_oe_n,
+ dl_int_ah_oe_n,
+ sp_we_n,
+ sp_push_n,
+ sp_pop_n,
+ sp_int_d_oe_n,
+ sp_int_a_oe_n,
+ x_we_n,
+ x_oe_n,
+ y_we_n,
+ y_oe_n,
+ stat_dec_we_n,
+ stat_dec_oe_n,
+ stat_bus_we_n,
+ stat_bus_oe_n,
+ dbuf_r_nw
+ );
instruction_register : dff generic map (dsize)
port map(trigger_clk, inst_we_n, '0', d_io, instruction);
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