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mlxsw: Set time stamp type as part of config profile
authorDanielle Ratson <danieller@nvidia.com>
Sun, 24 Jul 2022 08:03:20 +0000 (11:03 +0300)
committerDavid S. Miller <davem@davemloft.net>
Mon, 25 Jul 2022 12:58:55 +0000 (13:58 +0100)
The type of time stamp field in the CQE is configured via the
CONFIG_PROFILE command during driver initialization. Add the definition
of the relevant fields to the command's payload and set the type to UTC
for Spectrum-2 and above. This configuration can be done as part of the
preparations to PTP support, as the type of the time stamp will not break
any existing behavior.

Signed-off-by: Danielle Ratson <danieller@nvidia.com>
Reviewed-by: Petr Machata <petrm@nvidia.com>
Signed-off-by: Amit Cohen <amcohen@nvidia.com>
Signed-off-by: Ido Schimmel <idosch@nvidia.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
drivers/net/ethernet/mellanox/mlxsw/cmd.h
drivers/net/ethernet/mellanox/mlxsw/core.h
drivers/net/ethernet/mellanox/mlxsw/pci.c
drivers/net/ethernet/mellanox/mlxsw/spectrum.c

index e5ac5d2..60232fb 100644 (file)
@@ -689,6 +689,12 @@ MLXSW_ITEM32(cmd_mbox, config_profile, set_kvd_hash_double_size, 0x0C, 26, 1);
  */
 MLXSW_ITEM32(cmd_mbox, config_profile, set_cqe_version, 0x08, 0, 1);
 
+/* cmd_mbox_config_set_cqe_time_stamp_type
+ * Capability bit. Setting a bit to 1 configures the profile
+ * according to the mailbox contents.
+ */
+MLXSW_ITEM32(cmd_mbox, config_profile, set_cqe_time_stamp_type, 0x08, 2, 1);
+
 /* cmd_mbox_config_profile_max_vepa_channels
  * Maximum number of VEPA channels per port (0 through 16)
  * 0 - multi-channel VEPA is disabled
@@ -884,6 +890,26 @@ MLXSW_ITEM32_INDEXED(cmd_mbox, config_profile, swid_config_type,
 MLXSW_ITEM32_INDEXED(cmd_mbox, config_profile, swid_config_properties,
                     0x60, 0, 8, 0x08, 0x00, false);
 
+enum mlxsw_cmd_mbox_config_profile_cqe_time_stamp_type {
+       /* uSec - 1.024uSec (default). Only bits 15:0 are valid. */
+       MLXSW_CMD_MBOX_CONFIG_PROFILE_CQE_TIME_STAMP_TYPE_USEC,
+       /* FRC - Free Running Clock, units of 1nSec.
+        * Reserved when SwitchX/-2, Switch-IB/2 and Spectrum-1.
+        */
+       MLXSW_CMD_MBOX_CONFIG_PROFILE_CQE_TIME_STAMP_TYPE_FRC,
+       /* UTC. time_stamp[37:30] = Sec, time_stamp[29:0] = nSec.
+        * Reserved when SwitchX/2, Switch-IB/2 and Spectrum-1.
+        */
+       MLXSW_CMD_MBOX_CONFIG_PROFILE_CQE_TIME_STAMP_TYPE_UTC,
+};
+
+/* cmd_mbox_config_profile_cqe_time_stamp_type
+ * CQE time_stamp_type for non-mirror-packets.
+ * Configured if set_cqe_time_stamp_type is set.
+ * Reserved when SwitchX/-2, Switch-IB/2 and Spectrum-1.
+ */
+MLXSW_ITEM32(cmd_mbox, config_profile, cqe_time_stamp_type, 0xB0, 8, 2);
+
 /* cmd_mbox_config_profile_cqe_version
  * CQE version:
  * 0: CQE version is 0
index a3491ef..6b05586 100644 (file)
@@ -296,7 +296,8 @@ struct mlxsw_config_profile {
                used_ar_sec:1,
                used_adaptive_routing_group_cap:1,
                used_ubridge:1,
-               used_kvd_sizes:1;
+               used_kvd_sizes:1,
+               used_cqe_time_stamp_type:1;
        u8      max_vepa_channels;
        u16     max_mid;
        u16     max_pgt;
@@ -319,6 +320,7 @@ struct mlxsw_config_profile {
        u32     kvd_linear_size;
        u8      kvd_hash_single_parts;
        u8      kvd_hash_double_parts;
+       u8      cqe_time_stamp_type;
        struct mlxsw_swid_config swid_config[MLXSW_CONFIG_PROFILE_SWID_COUNT];
 };
 
index 41f0f68..57792e8 100644 (file)
@@ -1267,6 +1267,13 @@ static int mlxsw_pci_config_profile(struct mlxsw_pci *mlxsw_pci, char *mbox,
                mlxsw_cmd_mbox_config_profile_cqe_version_set(mbox, 1);
        }
 
+       if (profile->used_cqe_time_stamp_type) {
+               mlxsw_cmd_mbox_config_profile_set_cqe_time_stamp_type_set(mbox,
+                                                                         1);
+               mlxsw_cmd_mbox_config_profile_cqe_time_stamp_type_set(mbox,
+                                       profile->cqe_time_stamp_type);
+       }
+
        return mlxsw_cmd_config_profile_set(mlxsw_pci->core, mbox);
 }
 
index 209587c..fa48b26 100644 (file)
@@ -3411,6 +3411,8 @@ static const struct mlxsw_config_profile mlxsw_sp2_config_profile = {
                        .type           = MLXSW_PORT_SWID_TYPE_ETH,
                }
        },
+       .used_cqe_time_stamp_type       = 1,
+       .cqe_time_stamp_type            = MLXSW_CMD_MBOX_CONFIG_PROFILE_CQE_TIME_STAMP_TYPE_UTC,
 };
 
 static void