arm64: dts: imx8mp: Add MEDIA_BLK_CTRL

Add a DT node for the MEDIA_BLK_CTRL, which provides power domains for
the camera and display devices.

Signed-off-by: Paul Elder <paul.elder@ideasonboard.com>
Signed-off-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
Reviewed-by: Marek Vasut <marex@denx.de>
Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>

diff --git a/arch/arm64/boot/dts/freescale/imx8mp.dtsi b/arch/arm64/boot/dts/freescale/imx8mp.dtsi
index a0b4957..ed75bd3 100644 (file)
--- a/arch/arm64/boot/dts/freescale/imx8mp.dtsi
+++ b/arch/arm64/boot/dts/freescale/imx8mp.dtsi
@@ -1025,6 +1025,44 @@
                        #size-cells = <1>;
                        ranges;
 
+                       media_blk_ctrl: blk-ctrl@32ec0000 {
+                               compatible = "fsl,imx8mp-media-blk-ctrl",
+                                            "syscon";
+                               reg = <0x32ec0000 0x10000>;
+                               power-domains = <&pgc_mediamix>,
+                                               <&pgc_mipi_phy1>,
+                                               <&pgc_mipi_phy1>,
+                                               <&pgc_mediamix>,
+                                               <&pgc_mediamix>,
+                                               <&pgc_mipi_phy2>,
+                                               <&pgc_mediamix>,
+                                               <&pgc_ispdwp>,
+                                               <&pgc_ispdwp>,
+                                               <&pgc_mipi_phy2>;
+                               power-domain-names = "bus", "mipi-dsi1", "mipi-csi1",
+                                                    "lcdif1", "isi", "mipi-csi2",
+                                                    "lcdif2", "isp", "dwe",
+                                                    "mipi-dsi2";
+                               clocks = <&clk IMX8MP_CLK_MEDIA_APB_ROOT>,
+                                        <&clk IMX8MP_CLK_MEDIA_AXI_ROOT>,
+                                        <&clk IMX8MP_CLK_MEDIA_CAM1_PIX_ROOT>,
+                                        <&clk IMX8MP_CLK_MEDIA_CAM2_PIX_ROOT>,
+                                        <&clk IMX8MP_CLK_MEDIA_DISP1_PIX_ROOT>,
+                                        <&clk IMX8MP_CLK_MEDIA_DISP2_PIX_ROOT>,
+                                        <&clk IMX8MP_CLK_MEDIA_ISP_ROOT>,
+                                        <&clk IMX8MP_CLK_MEDIA_MIPI_PHY1_REF_ROOT>;
+                               clock-names = "apb", "axi", "cam1", "cam2",
+                                             "disp1", "disp2", "isp", "phy";
+
+                               assigned-clocks = <&clk IMX8MP_CLK_MEDIA_AXI>,
+                                                 <&clk IMX8MP_CLK_MEDIA_APB>;
+                               assigned-clock-parents = <&clk IMX8MP_SYS_PLL2_1000M>,
+                                                        <&clk IMX8MP_SYS_PLL1_800M>;
+                               assigned-clock-rates = <500000000>, <200000000>;
+
+                               #power-domain-cells = <1>;
+                       };
+
                        hsio_blk_ctrl: blk-ctrl@32f10000 {
                                compatible = "fsl,imx8mp-hsio-blk-ctrl", "syscon";
                                reg = <0x32f10000 0x24>;