drm/amd/display: Use actual TG instance instead of pipe instance

Signed-off-by: Jerry (Fangzhi) Zuo <Jerry.Zuo@amd.com>
Reviewed-by: Tony Cheng <Tony.Cheng@amd.com>
Acked-by: Harry Wentland <harry.wentland@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.c b/drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.c
index 4b8e7ce..4877243 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.c
+++ b/drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.c
@@ -56,7 +56,7 @@ void dce_pipe_control_lock(struct dc *dc,
        if (lock && pipe->stream_res.tg->funcs->is_blanked(pipe->stream_res.tg))
                return;
 
-       val = REG_GET_4(BLND_V_UPDATE_LOCK[pipe->pipe_idx],
+       val = REG_GET_4(BLND_V_UPDATE_LOCK[pipe->stream_res.tg->inst],
                        BLND_DCP_GRPH_V_UPDATE_LOCK, &dcp_grph,
                        BLND_SCL_V_UPDATE_LOCK, &scl,
                        BLND_BLND_V_UPDATE_LOCK, &blnd,
@@ -67,19 +67,19 @@ void dce_pipe_control_lock(struct dc *dc,
        blnd = lock_val;
        update_lock_mode = lock_val;
 
-       REG_SET_2(BLND_V_UPDATE_LOCK[pipe->pipe_idx], val,
+       REG_SET_2(BLND_V_UPDATE_LOCK[pipe->stream_res.tg->inst], val,
                        BLND_DCP_GRPH_V_UPDATE_LOCK, dcp_grph,
                        BLND_SCL_V_UPDATE_LOCK, scl);
 
        if (hws->masks->BLND_BLND_V_UPDATE_LOCK != 0)
-               REG_SET_2(BLND_V_UPDATE_LOCK[pipe->pipe_idx], val,
+               REG_SET_2(BLND_V_UPDATE_LOCK[pipe->stream_res.tg->inst], val,
                                BLND_BLND_V_UPDATE_LOCK, blnd,
                                BLND_V_UPDATE_LOCK_MODE, update_lock_mode);
 
        if (hws->wa.blnd_crtc_trigger) {
                if (!lock) {
-                       uint32_t value = REG_READ(CRTC_H_BLANK_START_END[pipe->pipe_idx]);
-                       REG_WRITE(CRTC_H_BLANK_START_END[pipe->pipe_idx], value);
+                       uint32_t value = REG_READ(CRTC_H_BLANK_START_END[pipe->stream_res.tg->inst]);
+                       REG_WRITE(CRTC_H_BLANK_START_END[pipe->stream_res.tg->inst], value);
                }
        }
 }

diff --git a/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c b/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c
index 206569e..3e9cd1b 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c
+++ b/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c
@@ -1132,7 +1132,7 @@ static void build_audio_output(
 static void get_surface_visual_confirm_color(const struct pipe_ctx *pipe_ctx,
                struct tg_color *color)
 {
-       uint32_t color_value = MAX_TG_COLOR_VALUE * (4 - pipe_ctx->pipe_idx) / 4;
+       uint32_t color_value = MAX_TG_COLOR_VALUE * (4 - pipe_ctx->stream_res.tg->inst) / 4;
 
        switch (pipe_ctx->plane_res.scl_data.format) {
        case PIXEL_FORMAT_ARGB8888: