drm/rockchip: Add per-pixel alpha support for the PX30 VOP

Compared to its predecessors, the PX30 VOP has a different register layout
for enabling per-pixel alpha. Instead of src_alpha_ctl and dst_alpha_ctl,
there is a single alpha control register. This register takes some fields
from src_alpha_ctl, but with a different layout.

Add support for the required fields to the PX30 VOP window descriptions,
which makes per-pixel-alpha formats behave correctly.

Signed-off-by: Paul Kocialkowski <paul.kocialkowski@bootlin.com>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Link: https://patchwork.freedesktop.org/patch/msgid/20200416140526.262533-1-paul.kocialkowski@bootlin.com

diff --git a/drivers/gpu/drm/rockchip/rockchip_drm_vop.c b/drivers/gpu/drm/rockchip/rockchip_drm_vop.c
index 1d76455..c80f7d9 100644 (file)
--- a/drivers/gpu/drm/rockchip/rockchip_drm_vop.c
+++ b/drivers/gpu/drm/rockchip/rockchip_drm_vop.c
@@ -1007,6 +1007,10 @@ static void vop_plane_atomic_update(struct drm_plane *plane,
                        SRC_ALPHA_CAL_M0(ALPHA_NO_SATURATION) |
                        SRC_FACTOR_M0(ALPHA_ONE);
                VOP_WIN_SET(vop, win, src_alpha_ctl, val);
+
+               VOP_WIN_SET(vop, win, alpha_pre_mul, ALPHA_SRC_PRE_MUL);
+               VOP_WIN_SET(vop, win, alpha_mode, ALPHA_PER_PIX);
+               VOP_WIN_SET(vop, win, alpha_en, 1);
        } else {
                VOP_WIN_SET(vop, win, src_alpha_ctl, SRC_ALPHA_EN(0));
        }

diff --git a/drivers/gpu/drm/rockchip/rockchip_drm_vop.h b/drivers/gpu/drm/rockchip/rockchip_drm_vop.h
index d03bdb5..4a2099c 100644 (file)
--- a/drivers/gpu/drm/rockchip/rockchip_drm_vop.h
+++ b/drivers/gpu/drm/rockchip/rockchip_drm_vop.h
@@ -167,6 +167,9 @@ struct vop_win_phy {
 
        struct vop_reg dst_alpha_ctl;
        struct vop_reg src_alpha_ctl;
+       struct vop_reg alpha_pre_mul;
+       struct vop_reg alpha_mode;
+       struct vop_reg alpha_en;
        struct vop_reg channel;
 };
 

diff --git a/drivers/gpu/drm/rockchip/rockchip_vop_reg.c b/drivers/gpu/drm/rockchip/rockchip_vop_reg.c
index 2413ded..80053d9 100644 (file)
--- a/drivers/gpu/drm/rockchip/rockchip_vop_reg.c
+++ b/drivers/gpu/drm/rockchip/rockchip_vop_reg.c
@@ -264,6 +264,9 @@ static const struct vop_win_phy px30_win0_data = {
        .uv_mst = VOP_REG(PX30_WIN0_CBR_MST0, 0xffffffff, 0),
        .yrgb_vir = VOP_REG(PX30_WIN0_VIR, 0x1fff, 0),
        .uv_vir = VOP_REG(PX30_WIN0_VIR, 0x1fff, 16),
+       .alpha_pre_mul = VOP_REG(PX30_WIN0_ALPHA_CTRL, 0x1, 2),
+       .alpha_mode = VOP_REG(PX30_WIN0_ALPHA_CTRL, 0x1, 1),
+       .alpha_en = VOP_REG(PX30_WIN0_ALPHA_CTRL, 0x1, 0),
 };
 
 static const struct vop_win_phy px30_win1_data = {
@@ -277,6 +280,9 @@ static const struct vop_win_phy px30_win1_data = {
        .dsp_st = VOP_REG(PX30_WIN1_DSP_ST, 0xffffffff, 0),
        .yrgb_mst = VOP_REG(PX30_WIN1_MST, 0xffffffff, 0),
        .yrgb_vir = VOP_REG(PX30_WIN1_VIR, 0x1fff, 0),
+       .alpha_pre_mul = VOP_REG(PX30_WIN1_ALPHA_CTRL, 0x1, 2),
+       .alpha_mode = VOP_REG(PX30_WIN1_ALPHA_CTRL, 0x1, 1),
+       .alpha_en = VOP_REG(PX30_WIN1_ALPHA_CTRL, 0x1, 0),
 };
 
 static const struct vop_win_phy px30_win2_data = {
@@ -291,6 +297,9 @@ static const struct vop_win_phy px30_win2_data = {
        .dsp_st = VOP_REG(PX30_WIN2_DSP_ST0, 0x1fff1fff, 0),
        .yrgb_mst = VOP_REG(PX30_WIN2_MST0, 0xffffffff, 0),
        .yrgb_vir = VOP_REG(PX30_WIN2_VIR0_1, 0x1fff, 0),
+       .alpha_pre_mul = VOP_REG(PX30_WIN2_ALPHA_CTRL, 0x1, 2),
+       .alpha_mode = VOP_REG(PX30_WIN2_ALPHA_CTRL, 0x1, 1),
+       .alpha_en = VOP_REG(PX30_WIN2_ALPHA_CTRL, 0x1, 0),
 };
 
 static const struct vop_win_data px30_vop_big_win_data[] = {