2008-03-19 Andreas Krebbel <krebbel1@de.ibm.com>

	* opcodes/s390-mkopc.c (s390_opcode_cpu_val): S390_OPCODE_Z10 added.
	(s390_cond_extensions): Reduced extensions to the compare related.
	(main): z10 cpu type option added.
	(expandConditionalJump): Renamed to ...
	(insertExpandedMnemonic): ... this.

	* opcodes/s390-opc.c: Re-group the operand format makros.
	(INSTR_RIE_RRPU, INSTR_RIE_RRP0, INSTR_RIE_RUPI,
	INSTR_RIE_R0PI, INSTR_RIE_RUPU, INSTR_RIE_R0PU, INSTR_RIE_R0IU,
	INSTR_RIE_R0I0, INSTR_RIE_R0UU, INSTR_RIE_R0U0,
	INSTR_RIE_RRUUU, INSTR_RIS_RURDI, INSTR_RIS_R0RDI, INSTR_RIS_RURDU,
	INSTR_RIS_R0RDU, INSTR_RRF_U0RR, INSTR_RRF_00RR, INSTR_RRS_RRRDU,
	INSTR_RRS_RRRD0, INSTR_RXY_URRD, INSTR_SIY_IRD, INSTR_SIL_RDI,
	INSTR_SIL_RDU): New instruction formats added.
	(MASK_RIE_RRPU, MASK_RIE_RRP0, MASK_RIE_RUPI, MASK_RIE_R0PI,
	MASK_RIE_RUPU, MASK_RIE_R0PU, MASK_RIE_R0IU, MASK_RIE_R0I0,
	MASK_RIE_R0UU, MASK_RIE_R0U0, MASK_RIE_RRUUU, MASK_RIS_RURDI,
	MASK_RIS_R0RDI, MASK_RIS_RURDU, MASK_RIS_R0RDU, MASK_RRF_U0RR,
	MASK_RRF_00RR, MASK_RRS_RRRDU, MASK_RRS_RRRD0, MASK_RXY_URRD,
	MASK_SIY_IRD, MASK_SIL_RDI, MASK_SIL_RDU): New instruction format
	masks added.
	(s390_opformats): New formats added "ris", "rrs", "sil".
	* opcodes/s390-opc.txt: Add the conditional jumps with the
	extensions removed from automatic expansion in s390-mkopc.c manually.
	(asi - trtre): Add new System z10 EC instructions.
	* include/opcode/s390.h (s390_opcode_cpu_val): S390_OPCODE_Z10 added.

2008-03-19  Andreas Krebbel  <krebbel1@de.ibm.com>

	* config/tc-s390.c (md_parse_option): z10 option added.

2008-03-19  Andreas Krebbel  <krebbel1@de.ibm.com>

	* gas/s390/zarch-z10.d: New file.
	* gas/s390/zarch-z10.s: New file.
	* gas/s390/s390.exp: Run the z10 testcases.

diff --git a/ChangeLog b/ChangeLog
index fbbb9bb..c64c0b0 100644 (file)
--- a/ChangeLog
+++ b/ChangeLog
@@ -1,3 +1,32 @@
+2008-03-19  Andreas Krebbel  <krebbel1@de.ibm.com>
+
+       * opcodes/s390-mkopc.c (s390_opcode_cpu_val): S390_OPCODE_Z10 added.
+       (s390_cond_extensions): Reduced extensions to the compare related.
+       (main): z10 cpu type option added.
+       (expandConditionalJump): Renamed to ...
+       (insertExpandedMnemonic): ... this.
+
+       * opcodes/s390-opc.c: Re-group the operand format makros.
+       (INSTR_RIE_RRPU, INSTR_RIE_RRP0, INSTR_RIE_RUPI,
+       INSTR_RIE_R0PI, INSTR_RIE_RUPU, INSTR_RIE_R0PU, INSTR_RIE_R0IU,
+       INSTR_RIE_R0I0, INSTR_RIE_R0UU, INSTR_RIE_R0U0,
+       INSTR_RIE_RRUUU, INSTR_RIS_RURDI, INSTR_RIS_R0RDI, INSTR_RIS_RURDU,
+       INSTR_RIS_R0RDU, INSTR_RRF_U0RR, INSTR_RRF_00RR, INSTR_RRS_RRRDU,
+       INSTR_RRS_RRRD0, INSTR_RXY_URRD, INSTR_SIY_IRD, INSTR_SIL_RDI,
+       INSTR_SIL_RDU): New instruction formats added.
+       (MASK_RIE_RRPU, MASK_RIE_RRP0, MASK_RIE_RUPI, MASK_RIE_R0PI,
+       MASK_RIE_RUPU, MASK_RIE_R0PU, MASK_RIE_R0IU, MASK_RIE_R0I0,
+       MASK_RIE_R0UU, MASK_RIE_R0U0, MASK_RIE_RRUUU, MASK_RIS_RURDI,
+       MASK_RIS_R0RDI, MASK_RIS_RURDU, MASK_RIS_R0RDU, MASK_RRF_U0RR,
+       MASK_RRF_00RR, MASK_RRS_RRRDU, MASK_RRS_RRRD0, MASK_RXY_URRD,
+       MASK_SIY_IRD, MASK_SIL_RDI, MASK_SIL_RDU): New instruction format
+       masks added.
+       (s390_opformats): New formats added "ris", "rrs", "sil".
+       * opcodes/s390-opc.txt: Add the conditional jumps with the
+       extensions removed from automatic expansion in s390-mkopc.c manually.
+       (asi - trtre): Add new System z10 EC instructions.
+       * include/opcode/s390.h (s390_opcode_cpu_val): S390_OPCODE_Z10 added.
+
 2008-03-17  Ralf Wildenhues  <Ralf.Wildenhues@gmx.de>
 
        * configure.ac: m4_include config/proginstall.m4.

diff --git a/include/opcode/s390.h b/include/opcode/s390.h
index ae039ef..2c00f4b 100644 (file)
--- a/include/opcode/s390.h
+++ b/include/opcode/s390.h
@@ -37,7 +37,8 @@ enum s390_opcode_cpu_val
     S390_OPCODE_Z900,
     S390_OPCODE_Z990,
     S390_OPCODE_Z9_109,
-    S390_OPCODE_Z9_EC
+    S390_OPCODE_Z9_EC,
+    S390_OPCODE_Z10
   };
 
 /* The opcode table is an array of struct s390_opcode.  */

diff --git a/opcodes/s390-mkopc.c b/opcodes/s390-mkopc.c
index 6461507..24951db 100644 (file)
--- a/opcodes/s390-mkopc.c
+++ b/opcodes/s390-mkopc.c
@@ -37,7 +37,8 @@ enum s390_opcode_cpu_val
     S390_OPCODE_Z900,
     S390_OPCODE_Z990,
     S390_OPCODE_Z9_109,
-    S390_OPCODE_Z9_EC
+    S390_OPCODE_Z9_EC,
+    S390_OPCODE_Z10
   };
 
 struct op_struct
@@ -121,82 +122,82 @@ struct s390_cond_ext_format
   char extension[4];
 };
 
-#define NUM_COND_EXTENSIONS 20
-
+/* The mnemonic extensions for conditional branches used to replace
+   the '*' tag.  */
+#define NUM_COND_EXTENSIONS 12
 const struct s390_cond_ext_format s390_cond_extensions[NUM_COND_EXTENSIONS] =
-  {
-    { '1', "o" },    /* jump on overflow / if ones */
-    { '2', "h" },    /* jump on A high */
-    { '2', "p" },    /* jump on plus */
-    { '3', "nle" },  /* jump on not low or equal */
-    { '4', "l" },    /* jump on A low */
-    { '4', "m" },    /* jump on minus / if mixed */
-    { '5', "nhe" },  /* jump on not high or equal */
-    { '6', "lh" },   /* jump on low or high */
-    { '7', "ne" },   /* jump on A not equal B */
-    { '7', "nz" },   /* jump on not zero / if not zeros */
-    { '8', "e" },    /* jump on A equal B */
-    { '8', "z" },    /* jump on zero / if zeros */
-    { '9', "nlh" },  /* jump on not low or high */
-    { 'a', "he" },   /* jump on high or equal */
-    { 'b', "nl" },   /* jump on A not low */
-    { 'b', "nm" },   /* jump on not minus / if not mixed */
-    { 'c', "le" },   /* jump on low or equal */
-    { 'd', "nh" },   /* jump on A not high */
-    { 'd', "np" },   /* jump on not plus */
-    { 'e', "no" },   /* jump on not overflow / if not ones */
-  };
+{ { '2', "h" },    /* jump on A high */
+  { '3', "nle" },  /* jump on not low or equal */
+  { '4', "l" },    /* jump on A low */
+  { '5', "nhe" },  /* jump on not high or equal */
+  { '6', "lh" },   /* jump on low or high */
+  { '7', "ne" },   /* jump on A not equal B */
+  { '8', "e" },    /* jump on A equal B */
+  { '9', "nlh" },  /* jump on not low or high */
+  { 'a', "he" },   /* jump on high or equal */
+  { 'b', "nl" },   /* jump on A not low */
+  { 'c', "le" },   /* jump on low or equal */
+  { 'd', "nh" },   /* jump on A not high */
+};
 
 /* As with insertOpcode instructions are added to the sorted opcode
    array.  Additionally mnemonics containing the '*<number>' tag are
    expanded to the set of conditional instructions described by
-   s390_cond_extensions with the '*<number>' tag replaced by the
-   respective mnemonic extensions.  */
+   s390_cond_extensions with the tag replaced by the respective
+   mnemonic extensions.  */
 
 static void
-expandConditionalJump (char *opcode, char *mnemonic, char *format,
-                      int min_cpu, int mode_bits)
+insertExpandedMnemonic (char *opcode, char *mnemonic, char *format,
+                       int min_cpu, int mode_bits)
 {
+  char *tag;
   char prefix[5];
   char suffix[5];
   char number[5];
-  int mask_start, i = 0, star_found = 0, reading_number = 0;
+  int mask_start, i = 0, tag_found = 0, reading_number = 0;
   int number_p = 0, suffix_p = 0, prefix_p = 0;
 
+  if (!(tag = strchr (mnemonic, '*')))
+    {
+      insertOpcode (opcode, mnemonic, format, min_cpu, mode_bits);
+      return;
+    }
+
   while (mnemonic[i] != '\0')
     {
-      switch (mnemonic[i])
+      if (mnemonic[i] == *tag)
        {
-       case '*':
-         if (star_found)
+         if (tag_found)
            goto malformed_mnemonic;
 
-         star_found = 1;
+         tag_found = 1;
          reading_number = 1;
-         break;
-
-       case '0': case '1': case '2': case '3': case '4':
-       case '5': case '6': case '7': case '8': case '9':
-         if (!star_found || !reading_number)
-           goto malformed_mnemonic;
-
-         number[number_p++] = mnemonic[i];
-         break;
-
-       default:
-         if (reading_number)
-           {
-             if (!number_p)
-               goto malformed_mnemonic;
-             else
-               reading_number = 0;
-           }
-
-         if (star_found)
-           suffix[suffix_p++] = mnemonic[i];
-         else
-           prefix[prefix_p++] = mnemonic[i];
        }
+      else
+       switch (mnemonic[i])
+         {
+         case '0': case '1': case '2': case '3': case '4':
+         case '5': case '6': case '7': case '8': case '9':
+           if (!tag_found || !reading_number)
+             goto malformed_mnemonic;
+
+           number[number_p++] = mnemonic[i];
+           break;
+
+         default:
+           if (reading_number)
+             {
+               if (!number_p)
+                 goto malformed_mnemonic;
+               else
+                 reading_number = 0;
+             }
+
+           if (tag_found)
+             suffix[suffix_p++] = mnemonic[i];
+           else
+             prefix[prefix_p++] = mnemonic[i];
+         }
       i++;
     }
 
@@ -221,9 +222,9 @@ expandConditionalJump (char *opcode, char *mnemonic, char *format,
       char new_mnemonic[15];
 
       strcpy (new_mnemonic, prefix);
+      opcode[mask_start] = s390_cond_extensions[i].nibble;
       strcat (new_mnemonic, s390_cond_extensions[i].extension);
       strcat (new_mnemonic, suffix);
-      opcode[mask_start] = s390_cond_extensions[i].nibble;
       insertOpcode (opcode, new_mnemonic, format, min_cpu, mode_bits);
     }
   return;
@@ -318,6 +319,8 @@ main (void)
            min_cpu = S390_OPCODE_Z9_109;
          else if (strcmp (cpu_string, "z9-ec") == 0)
            min_cpu = S390_OPCODE_Z9_EC;
+         else if (strcmp (cpu_string, "z10") == 0)
+           min_cpu = S390_OPCODE_Z10;
          else {
            fprintf (stderr, "Couldn't parse cpu string %s\n", cpu_string);
            exit (1);
@@ -343,11 +346,7 @@ main (void)
              str++;
          } while (*str != 0);
 
-         if (!strchr (mnemonic, '*'))
-           insertOpcode (opcode, mnemonic, format, min_cpu, mode_bits);
-         else
-           expandConditionalJump (opcode, mnemonic, format,
-                                  min_cpu, mode_bits);
+         insertExpandedMnemonic (opcode, mnemonic, format, min_cpu, mode_bits);
        }
       else
         fprintf (stderr, "Couldn't scan line %s\n", currentLine);

diff --git a/opcodes/s390-opc.c b/opcodes/s390-opc.c
index 3e35f63..0da1229 100644 (file)
--- a/opcodes/s390-opc.c
+++ b/opcodes/s390-opc.c
@@ -42,6 +42,8 @@ const struct s390_operand s390_operands[] =
 #define UNUSED 0
   { 0, 0, 0 },                    /* Indicates the end of the operand list */
 
+/* General purpose register operands.  */
+
 #define R_8    1                  /* GPR starting at position 8 */
   { 4, 8, S390_OPERAND_GPR },
 #define R_12   2                  /* GPR starting at position 12 */
@@ -54,88 +56,125 @@ const struct s390_operand s390_operands[] =
   { 4, 24, S390_OPERAND_GPR },
 #define R_28   6                  /* GPR starting at position 28 */
   { 4, 28, S390_OPERAND_GPR },
-#define R_32   7                  /* GPR starting at position 32 */
+#define RO_28  7                  /* optional GPR starting at position 28 */
+  { 4, 28, (S390_OPERAND_GPR | S390_OPERAND_OPTIONAL) },
+#define R_32   8                  /* GPR starting at position 32 */
   { 4, 32, S390_OPERAND_GPR },
 
-#define F_8    8                  /* FPR starting at position 8 */
+/* Floating point register operands.  */
+
+#define F_8    9                  /* FPR starting at position 8 */
   { 4, 8, S390_OPERAND_FPR },
-#define F_12   9                  /* FPR starting at position 12 */
+#define F_12   10                 /* FPR starting at position 12 */
   { 4, 12, S390_OPERAND_FPR },
-#define F_16   10                 /* FPR starting at position 16 */
+#define F_16   11                 /* FPR starting at position 16 */
   { 4, 16, S390_OPERAND_FPR },
-#define F_20   11                 /* FPR starting at position 16 */
+#define F_20   12                 /* FPR starting at position 16 */
   { 4, 16, S390_OPERAND_FPR },
-#define F_24   12                 /* FPR starting at position 24 */
+#define F_24   13                 /* FPR starting at position 24 */
   { 4, 24, S390_OPERAND_FPR },
-#define F_28   13                 /* FPR starting at position 28 */
+#define F_28   14                 /* FPR starting at position 28 */
   { 4, 28, S390_OPERAND_FPR },
-#define F_32   14                 /* FPR starting at position 32 */
+#define F_32   15                 /* FPR starting at position 32 */
   { 4, 32, S390_OPERAND_FPR },
 
-#define A_8    15                 /* Access reg. starting at position 8 */
+/* Access register operands.  */
+
+#define A_8    16                 /* Access reg. starting at position 8 */
   { 4, 8, S390_OPERAND_AR },
-#define A_12   16                 /* Access reg. starting at position 12 */
+#define A_12   17                 /* Access reg. starting at position 12 */
   { 4, 12, S390_OPERAND_AR },
-#define A_24   17                 /* Access reg. starting at position 24 */
+#define A_24   18                 /* Access reg. starting at position 24 */
   { 4, 24, S390_OPERAND_AR },
-#define A_28   18                 /* Access reg. starting at position 28 */
+#define A_28   19                 /* Access reg. starting at position 28 */
   { 4, 28, S390_OPERAND_AR },
 
-#define C_8    19                 /* Control reg. starting at position 8 */
+/* Control register operands.  */
+
+#define C_8    20                 /* Control reg. starting at position 8 */
   { 4, 8, S390_OPERAND_CR },
-#define C_12   20                 /* Control reg. starting at position 12 */
+#define C_12   21                 /* Control reg. starting at position 12 */
   { 4, 12, S390_OPERAND_CR },
 
-#define B_16   21                 /* Base register starting at position 16 */
+/* Base register operands.  */
+
+#define B_16   22                 /* Base register starting at position 16 */
   { 4, 16, S390_OPERAND_BASE|S390_OPERAND_GPR },
-#define B_32   22                 /* Base register starting at position 32 */
+#define B_32   23                 /* Base register starting at position 32 */
   { 4, 32, S390_OPERAND_BASE|S390_OPERAND_GPR },
 
-#define X_12   23                 /* Index register starting at position 12 */
+#define X_12   24                 /* Index register starting at position 12 */
   { 4, 12, S390_OPERAND_INDEX|S390_OPERAND_GPR },
 
-#define D_20   24                 /* Displacement starting at position 20 */
+/* Address displacement operands.  */
+
+#define D_20   25                 /* Displacement starting at position 20 */
   { 12, 20, S390_OPERAND_DISP },
-#define D_36   25                 /* Displacement starting at position 36 */
+#define D_36   26                 /* Displacement starting at position 36 */
   { 12, 36, S390_OPERAND_DISP },
-#define D20_20 26                /* 20 bit displacement starting at 20 */
+#define D20_20 27                /* 20 bit displacement starting at 20 */
   { 20, 20, S390_OPERAND_DISP|S390_OPERAND_SIGNED },
 
-#define L4_8   27                 /* 4 bit length starting at position 8 */
+/* Length operands.  */
+
+#define L4_8   28                 /* 4 bit length starting at position 8 */
   { 4, 8, S390_OPERAND_LENGTH },
-#define L4_12  28                 /* 4 bit length starting at position 12 */
+#define L4_12  29                 /* 4 bit length starting at position 12 */
   { 4, 12, S390_OPERAND_LENGTH },
-#define L8_8   29                 /* 8 bit length starting at position 8 */
+#define L8_8   30                 /* 8 bit length starting at position 8 */
   { 8, 8, S390_OPERAND_LENGTH },
 
-#define U4_8   30                 /* 4 bit unsigned value starting at 8 */
+/* Signed immediate operands.  */
+
+#define I8_8   31                /* 8 bit signed value starting at 8 */
+  { 8, 8, S390_OPERAND_SIGNED },
+#define I8_32  32                /* 8 bit signed value starting at 32 */
+  { 8, 32, S390_OPERAND_SIGNED },
+#define I16_16 33                 /* 16 bit signed value starting at 16 */
+  { 16, 16, S390_OPERAND_SIGNED },
+#define I16_32 34                 /* 16 bit signed value starting at 32 */
+  { 16, 32, S390_OPERAND_SIGNED },
+#define I32_16 35                /* 32 bit signed value starting at 16 */
+  { 32, 16, S390_OPERAND_SIGNED },
+
+/* Unsigned immediate operands.  */
+
+#define U4_8   36                 /* 4 bit unsigned value starting at 8 */
   { 4, 8, 0 },
-#define U4_12  31                 /* 4 bit unsigned value starting at 12 */
+#define U4_12  37                 /* 4 bit unsigned value starting at 12 */
   { 4, 12, 0 },
-#define U4_16  32                 /* 4 bit unsigned value starting at 16 */
+#define U4_16  38                 /* 4 bit unsigned value starting at 16 */
   { 4, 16, 0 },
-#define U4_20  33                 /* 4 bit unsigned value starting at 20 */
+#define U4_20  39                 /* 4 bit unsigned value starting at 20 */
   { 4, 20, 0 },
-#define U8_8   34                 /* 8 bit unsigned value starting at 8 */
+#define U4_32  40                 /* 4 bit unsigned value starting at 32 */
+  { 4, 32, 0 },
+#define U8_8   41                 /* 8 bit unsigned value starting at 8 */
   { 8, 8, 0 },
-#define U8_16  35                 /* 8 bit unsigned value starting at 16 */
+#define U8_16  42                 /* 8 bit unsigned value starting at 16 */
   { 8, 16, 0 },
-#define I16_16 36                 /* 16 bit signed value starting at 16 */
-  { 16, 16, S390_OPERAND_SIGNED },
-#define U16_16 37                 /* 16 bit unsigned value starting at 16 */
+#define U8_24  43                 /* 8 bit unsigned value starting at 24 */
+  { 8, 24, 0 },
+#define U8_32  44                 /* 8 bit unsigned value starting at 32 */
+  { 8, 32, 0 },
+#define U16_16 45                 /* 16 bit unsigned value starting at 16 */
   { 16, 16, 0 },
-#define J16_16 38                 /* PC relative jump offset at 16 */
+#define U16_32 46                /* 16 bit unsigned value starting at 32 */
+  { 16, 32, 0 },
+#define U32_16 47                /* 32 bit unsigned value starting at 16 */
+  { 32, 16, 0 },
+
+/* PC-relative address operands.  */
+
+#define J16_16 48                 /* PC relative jump offset at 16 */
   { 16, 16, S390_OPERAND_PCREL },
-#define J32_16 39                 /* PC relative long offset at 16 */
+#define J32_16 49                 /* PC relative long offset at 16 */
   { 32, 16, S390_OPERAND_PCREL },
-#define I32_16 40                /* 32 bit signed value starting at 16 */
-  { 32, 16, S390_OPERAND_SIGNED },
-#define U32_16 41                /* 32 bit unsigned value starting at 16 */
-  { 32, 16, 0 },
-#define M_16   42                 /* 4 bit optional mask starting at 16 */
+
+/* Conditional mask operands.  */
+
+#define M_16   50                 /* 4 bit optional mask starting at 16 */
   { 4, 16, S390_OPERAND_OPTIONAL },
-#define RO_28  43                 /* optional GPR starting at position 28 */
-  { 4, 28, (S390_OPERAND_GPR | S390_OPERAND_OPTIONAL) }
 
 };
 
@@ -185,6 +224,17 @@ const struct s390_operand s390_operands[] =
 
 #define INSTR_E          2, { 0,0,0,0,0,0 }                    /* e.g. pr    */
 #define INSTR_RIE_RRP    6, { R_8,R_12,J16_16,0,0,0 }          /* e.g. brxhg */
+#define INSTR_RIE_RRPU   6, { R_8,R_12,U4_32,J16_16,0,0 }      /* e.g. crj   */
+#define INSTR_RIE_RRP0   6, { R_8,R_12,J16_16,0,0,0 }          /* e.g. crjne */
+#define INSTR_RIE_RUPI   6, { R_8,I8_32,U4_12,J16_16,0,0 }     /* e.g. cij   */
+#define INSTR_RIE_R0PI   6, { R_8,I8_32,J16_16,0,0,0 }         /* e.g. cijne */
+#define INSTR_RIE_RUPU   6, { R_8,U8_32,U4_12,J16_16,0,0 }     /* e.g. clij  */
+#define INSTR_RIE_R0PU   6, { R_8,U8_32,J16_16,0,0,0 }         /* e.g. clijne */
+#define INSTR_RIE_R0IU   6, { R_8,I16_16,U4_32,0,0,0 }         /* e.g. cit   */
+#define INSTR_RIE_R0I0   6, { R_8,I16_16,0,0,0,0 }             /* e.g. citne */
+#define INSTR_RIE_R0UU   6, { R_8,U16_16,U4_32,0,0,0 }         /* e.g. clfit */
+#define INSTR_RIE_R0U0   6, { R_8,U16_16,0,0,0,0 }             /* e.g. clfitne */
+#define INSTR_RIE_RRUUU  6, { R_8,R_12,U8_16,U8_24,U8_32,0 }   /* e.g. rnsbg */
 #define INSTR_RIL_0P     6, { J32_16,0,0,0,0 }                 /* e.g. jg    */
 #define INSTR_RIL_RP     6, { R_8,J32_16,0,0,0,0 }             /* e.g. brasl */
 #define INSTR_RIL_UP     6, { U4_8,J32_16,0,0,0,0 }            /* e.g. brcl  */
@@ -195,6 +245,10 @@ const struct s390_operand s390_operands[] =
 #define INSTR_RI_RP      4, { R_8,J16_16,0,0,0,0 }             /* e.g. brct  */
 #define INSTR_RI_RU      4, { R_8,U16_16,0,0,0,0 }             /* e.g. tml   */
 #define INSTR_RI_UP      4, { U4_8,J16_16,0,0,0,0 }            /* e.g. brc   */
+#define INSTR_RIS_RURDI  6, { R_8,I8_32,U4_12,D_20,B_16,0 }    /* e.g. cib   */
+#define INSTR_RIS_R0RDI  6, { R_8,I8_32,D_20,B_16,0,0 }        /* e.g. cibne */
+#define INSTR_RIS_RURDU  6, { R_8,U8_32,U4_12,D_20,B_16,0 }    /* e.g. clib  */
+#define INSTR_RIS_R0RDU  6, { R_8,U8_32,D_20,B_16,0,0 }        /* e.g. clibne*/
 #define INSTR_RRE_00     4, { 0,0,0,0,0,0 }                    /* e.g. palb  */
 #define INSTR_RRE_0R     4, { R_28,0,0,0,0,0 }                 /* e.g. tb    */
 #define INSTR_RRE_AA     4, { A_24,A_28,0,0,0,0 }              /* e.g. cpya  */
@@ -221,6 +275,8 @@ const struct s390_operand s390_operands[] =
 #define INSTR_RRF_0UFF   4, { F_24,F_28,U4_20,0,0,0 }          /* e.g. ldetr */
 #define INSTR_RRF_FFFU   4, { F_24,F_16,F_28,U4_20,0,0 }       /* e.g. qadtr */
 #define INSTR_RRF_M0RR   4, { R_24,R_28,M_16,0,0,0 }           /* e.g. sske  */
+#define INSTR_RRF_U0RR   4, { R_24,R_28,U4_16,0,0,0 }          /* e.g. clrt  */
+#define INSTR_RRF_00RR   4, { R_24,R_28,0,0,0,0 }              /* e.g. clrtne */
 #define INSTR_RR_0R      2, { R_12, 0,0,0,0,0 }                /* e.g. br    */
 #define INSTR_RR_FF      2, { F_8,F_12,0,0,0,0 }               /* e.g. adr   */
 #define INSTR_RR_R0      2, { R_8, 0,0,0,0,0 }                 /* e.g. spm   */
@@ -228,6 +284,8 @@ const struct s390_operand s390_operands[] =
 #define INSTR_RR_U0      2, { U8_8, 0,0,0,0,0 }                /* e.g. svc   */
 #define INSTR_RR_UR      2, { U4_8,R_12,0,0,0,0 }              /* e.g. bcr   */
 #define INSTR_RRR_F0FF   4, { F_24,F_28,F_16,0,0,0 }           /* e.g. ddtr  */
+#define INSTR_RRS_RRRDU  6, { R_8,R_12,U4_32,D_20,B_16 }       /* e.g. crb   */
+#define INSTR_RRS_RRRD0  6, { R_8,R_12,D_20,B_16,0 }           /* e.g. crbne */
 #define INSTR_RSE_RRRD   6, { R_8,R_12,D_20,B_16,0,0 }         /* e.g. lmh   */
 #define INSTR_RSE_CCRD   6, { C_8,C_12,D_20,B_16,0,0 }         /* e.g. lmh   */
 #define INSTR_RSE_RURD   6, { R_8,U4_12,D_20,B_16,0,0 }        /* e.g. icmh  */
@@ -248,12 +306,16 @@ const struct s390_operand s390_operands[] =
 #define INSTR_RXF_RRRDR  6, { R_32,R_8,D_20,X_12,B_16,0 }      /* e.g. .insn */
 #define INSTR_RXY_RRRD   6, { R_8,D20_20,X_12,B_16,0,0 }       /* e.g. ly    */
 #define INSTR_RXY_FRRD   6, { F_8,D20_20,X_12,B_16,0,0 }       /* e.g. ley   */
+#define INSTR_RXY_URRD   6, { U4_8,D20_20,X_12,B_16,0,0 }      /* e.g. pfd   */
 #define INSTR_RX_0RRD    4, { D_20,X_12,B_16,0,0,0 }           /* e.g. be    */
 #define INSTR_RX_FRRD    4, { F_8,D_20,X_12,B_16,0,0 }         /* e.g. ae    */
 #define INSTR_RX_RRRD    4, { R_8,D_20,X_12,B_16,0,0 }         /* e.g. l     */
 #define INSTR_RX_URRD    4, { U4_8,D_20,X_12,B_16,0,0 }        /* e.g. bc    */
 #define INSTR_SI_URD     4, { D_20,B_16,U8_8,0,0,0 }           /* e.g. cli   */
 #define INSTR_SIY_URD    6, { D20_20,B_16,U8_8,0,0,0 }         /* e.g. tmy   */
+#define INSTR_SIY_IRD    6, { D20_20,B_16,I8_8,0,0,0 }         /* e.g. asi   */
+#define INSTR_SIL_RDI    6, { D_20,B_16,I16_32,0,0,0 }         /* e.g. chhsi */
+#define INSTR_SIL_RDU    6, { D_20,B_16,U16_32,0,0,0 }         /* e.g. clfhsi */
 #define INSTR_SSE_RDRD   6, { D_20,B_16,D_36,B_32,0,0 }        /* e.g. mvsdk */
 #define INSTR_SS_L0RDRD  6, { D_20,L8_8,B_16,D_36,B_32,0     } /* e.g. mvc   */
 #define INSTR_SS_L2RDRD  6, { D_20,B_16,D_36,L8_8,B_32,0     } /* e.g. pka   */
@@ -262,12 +324,23 @@ const struct s390_operand s390_operands[] =
 #define INSTR_SS_RRRDRD  6, { D_20,R_8,B_16,D_36,B_32,R_12 }   /* e.g. mvck  */
 #define INSTR_SS_RRRDRD2 6, { R_8,D_20,B_16,R_12,D_36,B_32 }   /* e.g. plo   */
 #define INSTR_SS_RRRDRD3 6, { R_8,R_12,D_20,B_16,D_36,B_32 }   /* e.g. lmd   */
+#define INSTR_SSF_RRDRD  6, { D_20,B_16,D_36,B_32,R_8,0 }      /* e.g. mvcos */
 #define INSTR_S_00       4, { 0,0,0,0,0,0 }                    /* e.g. hsch  */
 #define INSTR_S_RD       4, { D_20,B_16,0,0,0,0 }              /* e.g. lpsw  */
-#define INSTR_SSF_RRDRD  6, { D_20,B_16,D_36,B_32,R_8,0 }      /* e.g. mvcos */
 
 #define MASK_E           { 0xff, 0xff, 0x00, 0x00, 0x00, 0x00 }
 #define MASK_RIE_RRP     { 0xff, 0x00, 0x00, 0x00, 0x00, 0xff }
+#define MASK_RIE_RRPU    { 0xff, 0x00, 0x00, 0x00, 0x00, 0xff }
+#define MASK_RIE_RRP0    { 0xff, 0x00, 0x00, 0x00, 0xf0, 0xff }
+#define MASK_RIE_RUPI    { 0xff, 0x00, 0x00, 0x00, 0x00, 0xff }
+#define MASK_RIE_R0PI    { 0xff, 0x00, 0x00, 0x00, 0xf0, 0xff }
+#define MASK_RIE_RUPU    { 0xff, 0x00, 0x00, 0x00, 0x00, 0xff }
+#define MASK_RIE_R0PU    { 0xff, 0x00, 0x00, 0x00, 0xf0, 0xff }
+#define MASK_RIE_R0IU    { 0xff, 0x0f, 0x00, 0x00, 0x0f, 0xff }
+#define MASK_RIE_R0I0    { 0xff, 0x0f, 0x00, 0x00, 0xff, 0xff }
+#define MASK_RIE_R0UU    { 0xff, 0x0f, 0x00, 0x00, 0x0f, 0xff }
+#define MASK_RIE_R0U0    { 0xff, 0x0f, 0x00, 0x00, 0xff, 0xff }
+#define MASK_RIE_RRUUU   { 0xff, 0x00, 0x00, 0x00, 0x00, 0xff }
 #define MASK_RIL_0P      { 0xff, 0xff, 0x00, 0x00, 0x00, 0x00 }
 #define MASK_RIL_RP      { 0xff, 0x0f, 0x00, 0x00, 0x00, 0x00 }
 #define MASK_RIL_UP      { 0xff, 0x0f, 0x00, 0x00, 0x00, 0x00 }
@@ -278,6 +351,10 @@ const struct s390_operand s390_operands[] =
 #define MASK_RI_RP       { 0xff, 0x0f, 0x00, 0x00, 0x00, 0x00 }
 #define MASK_RI_RU       { 0xff, 0x0f, 0x00, 0x00, 0x00, 0x00 }
 #define MASK_RI_UP       { 0xff, 0x0f, 0x00, 0x00, 0x00, 0x00 }
+#define MASK_RIS_RURDI   { 0xff, 0x00, 0x00, 0x00, 0x00, 0xff }
+#define MASK_RIS_R0RDI   { 0xff, 0x0f, 0x00, 0x00, 0x00, 0xff }
+#define MASK_RIS_RURDU   { 0xff, 0x00, 0x00, 0x00, 0x00, 0xff }
+#define MASK_RIS_R0RDU   { 0xff, 0x0f, 0x00, 0x00, 0x00, 0xff }
 #define MASK_RRE_00      { 0xff, 0xff, 0xff, 0xff, 0x00, 0x00 }
 #define MASK_RRE_0R      { 0xff, 0xff, 0xff, 0xf0, 0x00, 0x00 }
 #define MASK_RRE_AA      { 0xff, 0xff, 0xff, 0x00, 0x00, 0x00 }
@@ -302,6 +379,8 @@ const struct s390_operand s390_operands[] =
 #define MASK_RRF_0UFF    { 0xff, 0xff, 0xf0, 0x00, 0x00, 0x00 }
 #define MASK_RRF_FFFU    { 0xff, 0xff, 0x00, 0x00, 0x00, 0x00 }
 #define MASK_RRF_M0RR    { 0xff, 0xff, 0x0f, 0x00, 0x00, 0x00 }
+#define MASK_RRF_U0RR    { 0xff, 0xff, 0x0f, 0x00, 0x00, 0x00 }
+#define MASK_RRF_00RR    { 0xff, 0xff, 0xff, 0x00, 0x00, 0x00 }
 #define MASK_RR_0R       { 0xff, 0xf0, 0x00, 0x00, 0x00, 0x00 }
 #define MASK_RR_FF       { 0xff, 0x00, 0x00, 0x00, 0x00, 0x00 }
 #define MASK_RR_R0       { 0xff, 0x0f, 0x00, 0x00, 0x00, 0x00 }
@@ -309,6 +388,8 @@ const struct s390_operand s390_operands[] =
 #define MASK_RR_U0       { 0xff, 0x00, 0x00, 0x00, 0x00, 0x00 }
 #define MASK_RR_UR       { 0xff, 0x00, 0x00, 0x00, 0x00, 0x00 }
 #define MASK_RRR_F0FF    { 0xff, 0xff, 0x0f, 0x00, 0x00, 0x00 }
+#define MASK_RRS_RRRDU   { 0xff, 0x00, 0x00, 0x00, 0x0f, 0xff }
+#define MASK_RRS_RRRD0   { 0xff, 0x00, 0x00, 0x00, 0xff, 0xff }
 #define MASK_RSE_RRRD    { 0xff, 0x00, 0x00, 0x00, 0x00, 0xff }
 #define MASK_RSE_CCRD    { 0xff, 0x00, 0x00, 0x00, 0x00, 0xff }
 #define MASK_RSE_RURD    { 0xff, 0x00, 0x00, 0x00, 0x00, 0xff }
@@ -329,12 +410,16 @@ const struct s390_operand s390_operands[] =
 #define MASK_RXF_RRRDR   { 0xff, 0x00, 0x00, 0x00, 0x00, 0xff }
 #define MASK_RXY_RRRD    { 0xff, 0x00, 0x00, 0x00, 0x00, 0xff }
 #define MASK_RXY_FRRD    { 0xff, 0x00, 0x00, 0x00, 0x00, 0xff }
+#define MASK_RXY_URRD    { 0xff, 0x00, 0x00, 0x00, 0x00, 0xff }
 #define MASK_RX_0RRD     { 0xff, 0xf0, 0x00, 0x00, 0x00, 0x00 }
 #define MASK_RX_FRRD     { 0xff, 0x00, 0x00, 0x00, 0x00, 0x00 }
 #define MASK_RX_RRRD     { 0xff, 0x00, 0x00, 0x00, 0x00, 0x00 }
 #define MASK_RX_URRD     { 0xff, 0x00, 0x00, 0x00, 0x00, 0x00 }
 #define MASK_SI_URD      { 0xff, 0x00, 0x00, 0x00, 0x00, 0x00 }
 #define MASK_SIY_URD     { 0xff, 0x00, 0x00, 0x00, 0x00, 0xff }
+#define MASK_SIY_IRD     { 0xff, 0x00, 0x00, 0x00, 0x00, 0xff }
+#define MASK_SIL_RDI     { 0xff, 0xff, 0x00, 0x00, 0x00, 0x00 }
+#define MASK_SIL_RDU     { 0xff, 0xff, 0x00, 0x00, 0x00, 0x00 }
 #define MASK_SSE_RDRD    { 0xff, 0xff, 0x00, 0x00, 0x00, 0x00 }
 #define MASK_SS_L0RDRD   { 0xff, 0x00, 0x00, 0x00, 0x00, 0x00 }
 #define MASK_SS_L2RDRD   { 0xff, 0x00, 0x00, 0x00, 0x00, 0x00 }
@@ -343,9 +428,10 @@ const struct s390_operand s390_operands[] =
 #define MASK_SS_RRRDRD   { 0xff, 0x00, 0x00, 0x00, 0x00, 0x00 }
 #define MASK_SS_RRRDRD2  { 0xff, 0x00, 0x00, 0x00, 0x00, 0x00 }
 #define MASK_SS_RRRDRD3  { 0xff, 0x00, 0x00, 0x00, 0x00, 0x00 }
+#define MASK_SSF_RRDRD   { 0xff, 0x0f, 0x00, 0x00, 0x00, 0x00 }
 #define MASK_S_00        { 0xff, 0xff, 0xff, 0xff, 0x00, 0x00 }
 #define MASK_S_RD        { 0xff, 0xff, 0x00, 0x00, 0x00, 0x00 }
-#define MASK_SSF_RRDRD   { 0xff, 0x0f, 0x00, 0x00, 0x00, 0x00 }
+
 
 /* The opcode formats table (blueprints for .insn pseudo mnemonic).  */
 
@@ -356,9 +442,11 @@ const struct s390_opcode s390_opformats[] =
   { "rie",     OP8(0x00LL),    MASK_RIE_RRP,   INSTR_RIE_RRP,  3, 0 },
   { "ril",     OP8(0x00LL),    MASK_RIL_RP,    INSTR_RIL_RP,   3, 0 },
   { "rilu",    OP8(0x00LL),    MASK_RIL_RU,    INSTR_RIL_RU,   3, 0 },
+  { "ris",     OP8(0x00LL),    MASK_RIS_RURDI, INSTR_RIS_RURDI,3, 6 },
   { "rr",      OP8(0x00LL),    MASK_RR_RR,     INSTR_RR_RR,    3, 0 },
   { "rre",     OP8(0x00LL),    MASK_RRE_RR,    INSTR_RRE_RR,   3, 0 },
   { "rrf",     OP8(0x00LL),    MASK_RRF_RURR,  INSTR_RRF_RURR, 3, 0 },
+  { "rrs",     OP8(0x00LL),    MASK_RRS_RRRDU, INSTR_RRS_RRRDU,3, 6 },
   { "rs",      OP8(0x00LL),    MASK_RS_RRRD,   INSTR_RS_RRRD,  3, 0 },
   { "rse",     OP8(0x00LL),    MASK_RSE_RRRD,  INSTR_RSE_RRRD, 3, 0 },
   { "rsi",     OP8(0x00LL),    MASK_RSI_RRP,   INSTR_RSI_RRP,  3, 0 },
@@ -370,6 +458,7 @@ const struct s390_opcode s390_opformats[] =
   { "s",       OP8(0x00LL),    MASK_S_RD,      INSTR_S_RD,     3, 0 },
   { "si",      OP8(0x00LL),    MASK_SI_URD,    INSTR_SI_URD,   3, 0 },
   { "siy",     OP8(0x00LL),    MASK_SIY_URD,   INSTR_SIY_URD,  3, 3 },
+  { "sil",     OP8(0x00LL),    MASK_SIL_RDI,   INSTR_SIL_RDI,  3, 6 },
   { "ss",      OP8(0x00LL),    MASK_SS_RRRDRD, INSTR_SS_RRRDRD,3, 0 },
   { "sse",     OP8(0x00LL),    MASK_SSE_RDRD,  INSTR_SSE_RDRD, 3, 0 },
   { "ssf",     OP8(0x00LL),    MASK_SSF_RRDRD, INSTR_SSF_RRDRD,3, 0 },

diff --git a/opcodes/s390-opc.txt b/opcodes/s390-opc.txt
index 2c77d4b..4b78f24 100644 (file)
--- a/opcodes/s390-opc.txt
+++ b/opcodes/s390-opc.txt
@@ -262,11 +262,35 @@ a700 tmh RI_RU "test under mask high" g5 esa,zarch
 a701 tml RI_RU "test under mask low" g5 esa,zarch
 0700 nopr RR_0R "no operation" g5 esa,zarch
 0700 b*8r RR_0R "conditional branch" g5 esa,zarch
+0710 bor RR_0R "branch on overflow / if ones" g5 esa,zarch
+0720 bpr RR_0R "branch on plus" g5 esa,zarch
+0740 bmr RR_0R "branch on minus / if mixed" g5 esa,zarch
+0770 bnzr RR_0R "branch on not zero / if not zeros" g5 esa,zarch
+0780 bzr RR_0R "branch on zero / if zeros" g5 esa,zarch
+07b0 bnmr RR_0R "branch on not minus / if not mixed" g5 esa,zarch
+07d0 bnpr RR_0R "branch on not plus" g5 esa,zarch
+07e0 bnor RR_0R "branch on not overflow / if not ones" g5 esa,zarch
 07f0 br RR_0R "unconditional branch" g5 esa,zarch
 4700 nop RX_0RRD "no operation" g5 esa,zarch
 4700 b*8 RX_0RRD "conditional branch" g5 esa,zarch
+4710 bo RX_0RRD "branch on overflow / if ones" g5 esa,zarch
+4720 bp RX_0RRD "branch on plus" g5 esa,zarch
+4740 bm RX_0RRD "branch on minus / if mixed" g5 esa,zarch
+4770 bnz RX_0RRD "branch on not zero / if not zeros" g5 esa,zarch
+4780 bz RX_0RRD "branch on zero / if zeros" g5 esa,zarch
+47b0 bnm RX_0RRD "branch on not minus / if not mixed" g5 esa,zarch
+47d0 bnp RX_0RRD "branch on not plus" g5 esa,zarch
+47e0 bno RX_0RRD "branch on not overflow / if not ones" g5 esa,zarch
 47f0 b RX_0RRD "unconditional branch" g5 esa,zarch
 a704 j*8 RI_0P "conditional jump" g5 esa,zarch
+a714 jo RI_0P "jump on overflow / if ones" g5 esa,zarch
+a724 jp RI_0P "jump on plus" g5 esa,zarch
+a744 jm RI_0P "jump on minus / if mixed" g5 esa,zarch
+a774 jnz RI_0P "jump on not zero / if not zeros" g5 esa,zarch
+a784 jz RI_0P "jump on zero / if zeros" g5 esa,zarch
+a7b4 jnm RI_0P "jump on not minus / if not mixed" g5 esa,zarch
+a7d4 jnp RI_0P "jump on not plus" g5 esa,zarch
+a7e4 jno RI_0P "jump on not overflow / if not ones" g5 esa,zarch
 a7f4 j RI_0P "unconditional jump" g5 esa,zarch
 b34a axbr RRE_FF "add extended bfp" g5 esa,zarch
 b31a adbr RRE_FF "add long bfp" g5 esa,zarch
@@ -463,6 +487,14 @@ a702 tmhh RI_RU "test under mask high high" z900 zarch
 a703 tmhl RI_RU "test under mask high low" z900 zarch
 c004 brcl RIL_UP "branch relative on condition long" z900 esa,zarch
 c004 jg*8 RIL_0P "conditional jump long" z900 esa,zarch
+c014 jgo RIL_0P "jump long on overflow / if ones" z900 esa,zarch
+c024 jgp RIL_0P "jump long on plus" z900 esa,zarch
+c044 jgm RIL_0P "jump long on minus / if mixed" z900 esa,zarch
+c074 jgnz RIL_0P "jump long on not zero / if not zeros" z900 esa,zarch
+c084 jgz RIL_0P "jump long on zero / if zeros" z900 esa,zarch
+c0b4 jgnm RIL_0P "jump long on not minus / if not mixed" z900 esa,zarch
+c0d4 jgnp RIL_0P "jump long on not plus" z900 esa,zarch
+c0e4 jgno RIL_0P "jump long on not overflow / if not ones" z900 esa,zarch
 c0f4 jg RIL_0P "unconditional jump long" z900 esa,zarch
 c005 brasl RIL_RP "branch relative and save long" z900 esa,zarch
 a707 brctg RI_RP "branch relative on count 64" z900 zarch
@@ -852,3 +884,105 @@ ed0000000059 tdgxt RXE_FRRD "test data group extended dfp" z9-ec zarch
 010a pfpo E "perform floating point operation" z9-ec zarch
 c801 ectg SSF_RRDRD "extract cpu time" z9-ec zarch
 c802 csst SSF_RRDRD "compare and swap and store" z9-ec zarch
+eb000000006a asi SIY_IRD "add immediate (32<8)" z10 zarch
+eb000000007a agsi SIY_IRD "add immediate (64<8)" z10 zarch
+eb000000006e alsi SIY_IRD "add logical with signed immediate (32<8)" z10 zarch
+eb000000007e algsi SIY_IRD "add logical with signed immediate (64<8)" z10 zarch
+c60d crl RIL_RP "compare relative long (32)" z10 zarch
+c608 cgrl RIL_RP "compare relative long (64)" z10 zarch
+c60c cgfrl RIL_RP "compare relative long (64<32)" z10 zarch
+ec00000000f6 crb*32 RRS_RRRD0 "compare and branch (32)" z10 zarch
+ec00000000f6 crb RRS_RRRDU "compare and branch (32)" z10 zarch
+ec00000000e4 cgrb*32 RRS_RRRD0 "compare and branch (64)" z10 zarch
+ec00000000e4 cgrb RRS_RRRDU "compare and branch (64)" z10 zarch
+ec0000000076 crj*32 RIE_RRP "compare and branch relative (32)" z10 zarch
+ec0000000076 crj RIE_RRPU "compare and branch relative (32)" z10 zarch
+ec0000000064 cgrj*32 RIE_RRP0 "compare and branch relative (64)" z10 zarch
+ec0000000064 cgrj RIE_RRPU "compare and branch relative (64)" z10 zarch
+ec00000000fe cib*12 RIS_R0RDI "compare immediate and branch (32<8)" z10 zarch
+ec00000000fe cib RIS_RURDI "compare immediate and branch (32<8)" z10 zarch
+ec00000000fc cgib*12 RIS_R0RDI "compare immediate and branch (64<8)" z10 zarch
+ec00000000fc cgib RIS_RURDI "compare immediate and branch (64<8)" z10 zarch
+ec000000007e cij*12 RIE_R0PI "compare immediate and branch relative (32<8)" z10 zarch
+ec000000007e cij RIE_RUPI "compare immediate and branch relative (32<8)" z10 zarch
+ec000000007c cgij*12 RIE_R0PI "compare immediate and branch relative (64<8)" z10 zarch
+ec000000007c cgij RIE_RUPI "compare immediate and branch relative (64<8)" z10 zarch
+b97200000000 crt*16 RRF_00RR "compare and trap" z10 zarch
+b972 crt RRF_U0RR "compare and trap" z10 zarch
+b96000000000 cgrt*16 RRF_00RR "compare and trap 64" z10 zarch
+b960 cgrt RRF_U0RR "compare and trap 64" z10 zarch
+ec0000000072 cit*32 RIE_R0I0 "compare immediate and trap (32<16)" z10 zarch
+ec0000000072 cit RIE_R0IU "compare immediate and trap (32<16)" z10 zarch
+ec0000000070 cgit*32 RIE_R0I0 "compare immediate and trap (64<16)" z10 zarch
+ec0000000070 cgit RIE_R0IU "compare immediate and trap (64<16)" z10 zarch
+e30000000034 cgh RXY_RRRD "compare halfword (64<16)" z10 zarch
+e554 chhsi SIL_RDI "compare halfword immediate (16<16)" z10 zarch
+e55c chsi SIL_RDI "compare halfword immediate (32<16)" z10 zarch
+e558 cghsi SIL_RDI "compare halfword immediate (64<16)" z10 zarch
+c605 chrl RIL_RP "compare halfword relative long (32<8)" z10 zarch
+c604 cghrl RIL_RP "compare halfword relative long (64<8)" z10 zarch
+e555 clhhsi SIL_RDU "compare logical immediate (16<16)" z10 zarch
+e55d clfhsi SIL_RDU "compare logical immediate (32<16)" z10 zarch
+e559 clghsi SIL_RDU "compare logical immediate (64<16)" z10 zarch
+c60f clrl RIL_RP "compare logical relative long (32)" z10 zarch
+c60a clgrl RIL_RP "compare logical relative long (64)" z10 zarch
+c60e clgfrl RIL_RP "compare logical relative long (64<32)" z10 zarch
+c607 clhrl RIL_RP "compare logical relative long (32<16)" z10 zarch
+c606 clghrl RIL_RP "compare logical relative long (64<16)" z10 zarch
+ec00000000f7 clrb*32 RRS_RRRD0 "compare logical and branch (32)" z10 zarch
+ec00000000f7 clrb RRS_RRRDU "compare logical and branch (32)" z10 zarch
+ec00000000e5 clgrb*32 RRS_RRRD0 "compare logical and branch (64)" z10 zarch
+ec00000000e5 clgrb RRS_RRRDU "compare logical and branch (64)" z10 zarch
+ec0000000077 clrj*32 RIE_RRP "compare logical and branch relative (32)" z10 zarch
+ec0000000077 clrj RIE_RRPU "compare logical and branch relative (32)" z10 zarch
+ec0000000065 clgrj*32 RIE_RRP "compare logical and branch relative (64)" z10 zarch
+ec0000000065 clgrj RIE_RRPU "compare logical and branch relative (64)" z10 zarch
+ec00000000ff clib*12 RIS_R0RDU "compare logical immediate and branch (32<8)" z10 zarch
+ec00000000ff clib RIS_RURDU "compare logical immediate and branch (32<8)" z10 zarch
+ec00000000fd clgib*12 RIS_R0RDU "compare logical immediate and branch (64<8)" z10 zarch
+ec00000000fd clgib RIS_RURDU "compare logical immediate and branch (64<8)" z10 zarch
+ec000000007f clij*12 RIE_R0PU "compare logical immediate and branch relative (32<8)" z10 zarch
+ec000000007f clij RIE_RUPU "compare logical immediate and branch relative (32<8)" z10 zarch
+ec000000007d clgij*12 RIE_R0PU "compare logical immediate and branch relative (64<8)" z10 zarch
+ec000000007d clgij RIE_RUPU "compare logical immediate and branch relative (64<8)" z10 zarch
+b97300000000 clrt*16 RRF_00RR "compare logical and trap (32)" z10 zarch
+b973 clrt RRF_U0RR "compare logical and trap (32)" z10 zarch
+b96100000000 clgrt*16 RRF_00RR "compare logical and trap (64)" z10 zarch
+b961 clgrt RRF_U0RR "compare logical and trap (64)" z10 zarch
+ec0000000073 clfit*32 RIE_R0U0 "compare logical and trap (32<16)" z10 zarch
+ec0000000073 clfit RIE_R0UU "compare logical and trap (32<16)" z10 zarch
+ec0000000071 clgit*32 RIE_R0U0 "compare logical and trap (64<16)" z10 zarch
+ec0000000071 clgit RIE_R0UU "compare logical and trap (64<16)" z10 zarch
+eb000000004c ecag RSY_RRRD "extract cache attribute" z10 zarch
+c40d lrl RIL_RP "load relative long (32)" z10 zarch
+c408 lgrl RIL_RP "load relative long (64)" z10 zarch
+c40c lgfrl RIL_RP "load relative long (64<32)" z10 zarch
+e30000000075 laey RXY_RRRD "load address extended" z10 zarch
+e30000000032 ltgf RXY_RRRD "load and test (64<32)" z10 zarch
+c405 lhrl RIL_RP "load halfword relative long (32<16)" z10 zarch
+c404 lghrl RIL_RP "load halfword relative long (64<16)" z10 zarch
+c40e llgfrl RIL_RP "load logical relative long (64<32)" z10 zarch
+c402 llhrl RIL_RP "load logical halfword relative long (32<16)" z10 zarch
+c406 llghrl RIL_RP "load logical halfword relative long (64<16)" z10 zarch
+e544 mvhhi SIL_RDI "move (16<16)" z10 zarch
+e54c mvhi SIL_RDI "move (32<16)" z10 zarch
+e548 mvghi SIL_RDI "move (64<16)" z10 zarch
+e3000000005c mfy RXY_RRRD "multiply" z10 zarch
+e3000000007c mhy RXY_RRRD "multiply halfword" z10 zarch
+c201 msfi RIL_RI "multiply single immediate (32)" z10 zarch
+c200 msgfi RIL_RI "multiply single immediate (64)" z10 zarch
+e30000000036 pfd RXY_URRD "prefetch data" z10 zarch
+c602 pfdrl RIL_UP "prefetch data relative long" z10 zarch
+ec0000000054 rnsbg RIE_RRUUU "rotate then and selected bits" z10 zarch
+ec0000000057 rxsbg RIE_RRUUU "rotate then exclusive or selected bits" z10 zarch
+ec0000000056 rosbg RIE_RRUUU "rotate then or selected bits" z10 zarch
+ec0000000055 risbg RIE_RRUUU "rotate then insert selected bits" z10 zarch
+c40f strl RIL_RP "store relative long (32)" z10 zarch
+c40b stgrl RIL_RP "store relative long (64)" z10 zarch
+c407 sthrl RIL_RP "store halfword relative long" z10 zarch
+c600 exrl RIL_RP "execute relative long" z10 zarch
+af00 mc SI_URD "monitor call" z10 zarch
+b9a2 ptf RRE_R0 "perform topology function" z10 zarch
+b9af pfmf RRE_RR "perform frame management function" z10 zarch
+b9bf trte RRF_M0RR "translate and test extended" z10 zarch
+b9bd trtre RRF_M0RR "translate and test reverse extended" z10 zarch