drm/amd/display: replace msleep with udelay in fbc path

FBC enabling and disabling path has msleep which leads to
BUG hit when called in atomic context, hence this patch
replaces msleeps with udelays appropriately.

Signed-off-by: Shirish S <shirish.s@amd.com>
Signed-off-by: Roman Li <Roman.Li@amd.com>
Reviewed-by: Tony Cheng <Tony.Cheng@amd.com>
Acked-by: Harry Wentland <harry.wentland@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

diff --git a/drivers/gpu/drm/amd/display/dc/dce110/dce110_compressor.c b/drivers/gpu/drm/amd/display/dc/dce110/dce110_compressor.c
index 9150d26..e2994d3 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/dce110/dce110_compressor.c
+++ b/drivers/gpu/drm/amd/display/dc/dce110/dce110_compressor.c
@@ -121,10 +121,10 @@ static void reset_lb_on_vblank(struct dc_context *ctx)
                frame_count = dm_read_reg(ctx, mmCRTC_STATUS_FRAME_COUNT);
 
 
-               for (retry = 100; retry > 0; retry--) {
+               for (retry = 10000; retry > 0; retry--) {
                        if (frame_count != dm_read_reg(ctx, mmCRTC_STATUS_FRAME_COUNT))
                                break;
-                       msleep(1);
+                       udelay(10);
                }
                if (!retry)
                        dm_error("Frame count did not increase for 100ms.\n");
@@ -147,14 +147,14 @@ static void wait_for_fbc_state_changed(
        uint32_t addr = mmFBC_STATUS;
        uint32_t value;
 
-       while (counter < 10) {
+       while (counter < 1000) {
                value = dm_read_reg(cp110->base.ctx, addr);
                if (get_reg_field_value(
                        value,
                        FBC_STATUS,
                        FBC_ENABLE_STATUS) == enabled)
                        break;
-               msleep(10);
+               udelay(100);
                counter++;
        }