ARM: dts: imx7d: cl-som-imx7: fix pinctrl_enet

The missing last digit of the CONFIG values is added. Looks like a typo
of some sort when comparing to the downstream dt. This fixes
intermittent behavior behaviour of the ethernet controllers.

Signed-off-by: Aapo Vienamo <aapo@tuxera.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>

diff --git a/arch/arm/boot/dts/imx7d-cl-som-imx7.dts b/arch/arm/boot/dts/imx7d-cl-som-imx7.dts
index c1a3d62..7f64568 100644 (file)
--- a/arch/arm/boot/dts/imx7d-cl-som-imx7.dts
+++ b/arch/arm/boot/dts/imx7d-cl-som-imx7.dts
@@ -213,37 +213,37 @@
 &iomuxc {
        pinctrl_enet1: enet1grp {
                fsl,pins = <
-                       MX7D_PAD_SD2_CD_B__ENET1_MDIO                   0x3
-                       MX7D_PAD_SD2_WP__ENET1_MDC                      0x3
-                       MX7D_PAD_ENET1_RGMII_TXC__ENET1_RGMII_TXC       0x1
-                       MX7D_PAD_ENET1_RGMII_TD0__ENET1_RGMII_TD0       0x1
-                       MX7D_PAD_ENET1_RGMII_TD1__ENET1_RGMII_TD1       0x1
-                       MX7D_PAD_ENET1_RGMII_TD2__ENET1_RGMII_TD2       0x1
-                       MX7D_PAD_ENET1_RGMII_TD3__ENET1_RGMII_TD3       0x1
-                       MX7D_PAD_ENET1_RGMII_TX_CTL__ENET1_RGMII_TX_CTL 0x1
-                       MX7D_PAD_ENET1_RGMII_RXC__ENET1_RGMII_RXC       0x1
-                       MX7D_PAD_ENET1_RGMII_RD0__ENET1_RGMII_RD0       0x1
-                       MX7D_PAD_ENET1_RGMII_RD1__ENET1_RGMII_RD1       0x1
-                       MX7D_PAD_ENET1_RGMII_RD2__ENET1_RGMII_RD2       0x1
-                       MX7D_PAD_ENET1_RGMII_RD3__ENET1_RGMII_RD3       0x1
-                       MX7D_PAD_ENET1_RGMII_RX_CTL__ENET1_RGMII_RX_CTL 0x1
+                       MX7D_PAD_SD2_CD_B__ENET1_MDIO                   0x30
+                       MX7D_PAD_SD2_WP__ENET1_MDC                      0x30
+                       MX7D_PAD_ENET1_RGMII_TXC__ENET1_RGMII_TXC       0x11
+                       MX7D_PAD_ENET1_RGMII_TD0__ENET1_RGMII_TD0       0x11
+                       MX7D_PAD_ENET1_RGMII_TD1__ENET1_RGMII_TD1       0x11
+                       MX7D_PAD_ENET1_RGMII_TD2__ENET1_RGMII_TD2       0x11
+                       MX7D_PAD_ENET1_RGMII_TD3__ENET1_RGMII_TD3       0x11
+                       MX7D_PAD_ENET1_RGMII_TX_CTL__ENET1_RGMII_TX_CTL 0x11
+                       MX7D_PAD_ENET1_RGMII_RXC__ENET1_RGMII_RXC       0x11
+                       MX7D_PAD_ENET1_RGMII_RD0__ENET1_RGMII_RD0       0x11
+                       MX7D_PAD_ENET1_RGMII_RD1__ENET1_RGMII_RD1       0x11
+                       MX7D_PAD_ENET1_RGMII_RD2__ENET1_RGMII_RD2       0x11
+                       MX7D_PAD_ENET1_RGMII_RD3__ENET1_RGMII_RD3       0x11
+                       MX7D_PAD_ENET1_RGMII_RX_CTL__ENET1_RGMII_RX_CTL 0x11
                >;
        };
 
        pinctrl_enet2: enet2grp {
                fsl,pins = <
-                       MX7D_PAD_EPDC_GDSP__ENET2_RGMII_TXC             0x1
-                       MX7D_PAD_EPDC_SDCE2__ENET2_RGMII_TD0            0x1
-                       MX7D_PAD_EPDC_SDCE3__ENET2_RGMII_TD1            0x1
-                       MX7D_PAD_EPDC_GDCLK__ENET2_RGMII_TD2            0x1
-                       MX7D_PAD_EPDC_GDOE__ENET2_RGMII_TD3             0x1
-                       MX7D_PAD_EPDC_GDRL__ENET2_RGMII_TX_CTL          0x1
-                       MX7D_PAD_EPDC_SDCE1__ENET2_RGMII_RXC            0x1
-                       MX7D_PAD_EPDC_SDCLK__ENET2_RGMII_RD0            0x1
-                       MX7D_PAD_EPDC_SDLE__ENET2_RGMII_RD1             0x1
-                       MX7D_PAD_EPDC_SDOE__ENET2_RGMII_RD2             0x1
-                       MX7D_PAD_EPDC_SDSHR__ENET2_RGMII_RD3            0x1
-                       MX7D_PAD_EPDC_SDCE0__ENET2_RGMII_RX_CTL         0x1
+                       MX7D_PAD_EPDC_GDSP__ENET2_RGMII_TXC             0x11
+                       MX7D_PAD_EPDC_SDCE2__ENET2_RGMII_TD0            0x11
+                       MX7D_PAD_EPDC_SDCE3__ENET2_RGMII_TD1            0x11
+                       MX7D_PAD_EPDC_GDCLK__ENET2_RGMII_TD2            0x11
+                       MX7D_PAD_EPDC_GDOE__ENET2_RGMII_TD3             0x11
+                       MX7D_PAD_EPDC_GDRL__ENET2_RGMII_TX_CTL          0x11
+                       MX7D_PAD_EPDC_SDCE1__ENET2_RGMII_RXC            0x11
+                       MX7D_PAD_EPDC_SDCLK__ENET2_RGMII_RD0            0x11
+                       MX7D_PAD_EPDC_SDLE__ENET2_RGMII_RD1             0x11
+                       MX7D_PAD_EPDC_SDOE__ENET2_RGMII_RD2             0x11
+                       MX7D_PAD_EPDC_SDSHR__ENET2_RGMII_RD3            0x11
+                       MX7D_PAD_EPDC_SDCE0__ENET2_RGMII_RX_CTL         0x11
                >;
        };