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arm64: dts: rockchip: move rk3399-sapphire PCIe to excavator baseboard
authorVicente Bergas <vicencb@gmail.com>
Mon, 26 Feb 2018 18:57:21 +0000 (19:57 +0100)
committerHeiko Stuebner <heiko@sntech.de>
Mon, 16 Apr 2018 12:13:13 +0000 (14:13 +0200)
The PCIe signals are routed through the connector to the baseboard.

Signed-off-by: Vicente Bergas <vicencb@gmail.com>
Reviewed-by: Shawn Lin <shawn.lin@rock-chips.com>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
arch/arm64/boot/dts/rockchip/rk3399-sapphire-excavator.dts
arch/arm64/boot/dts/rockchip/rk3399-sapphire.dtsi

index 56952d1..2ce7ce7 100644 (file)
        status = "okay";
 };
 
+&pcie_phy {
+       status = "okay";
+};
+
+&pcie0 {
+       assigned-clocks = <&cru SCLK_PCIEPHY_REF>;
+       assigned-clock-parents = <&cru SCLK_PCIEPHY_REF100M>;
+       assigned-clock-rates = <100000000>;
+       ep-gpios = <&gpio2 RK_PA4 GPIO_ACTIVE_HIGH>;
+       num-lanes = <4>;
+       pinctrl-names = "default";
+       pinctrl-0 = <&pcie_clkreqn_cpm>;
+       status = "okay";
+};
+
 &pinctrl {
        sdio-pwrseq {
                wifi_enable_h: wifi-enable-h {
index 96c097b..941b627 100644 (file)
        gpio1830-supply = <&vcc_3v0>;
 };
 
-&pcie_phy {
-       status = "okay";
-};
-
-&pcie0 {
-       assigned-clocks = <&cru SCLK_PCIEPHY_REF>;
-       assigned-clock-parents = <&cru SCLK_PCIEPHY_REF100M>;
-       assigned-clock-rates = <100000000>;
-       ep-gpios = <&gpio2 RK_PA4 GPIO_ACTIVE_HIGH>;
-       num-lanes = <4>;
-       pinctrl-names = "default";
-       pinctrl-0 = <&pcie_clkreqn_cpm>;
-       status = "okay";
-};
-
 &pmu_io_domains {
        pmu1830-supply = <&vcc_3v0>;
        status = "okay";