void ide_ioport_write(void *opaque, uint32_t addr, uint32_t val)
{
IDEBus *bus = opaque;
- IDEState *s = idebus_active_if(bus);
+ IDEState *s = ide_bus_active_if(bus);
int reg_num = addr & 7;
trace_ide_ioport_write(addr, ATA_IOPORT_WR_lookup[reg_num], val, bus, s);
IDEState *s;
bool complete;
- s = idebus_active_if(bus);
+ s = ide_bus_active_if(bus);
trace_ide_bus_exec_cmd(bus, s, val);
/* ignore commands to non existent slave */
uint32_t ide_ioport_read(void *opaque, uint32_t addr)
{
IDEBus *bus = opaque;
- IDEState *s = idebus_active_if(bus);
+ IDEState *s = ide_bus_active_if(bus);
uint32_t reg_num;
int ret, hob;
uint32_t ide_status_read(void *opaque, uint32_t addr)
{
IDEBus *bus = opaque;
- IDEState *s = idebus_active_if(bus);
+ IDEState *s = ide_bus_active_if(bus);
int ret;
if ((!bus->ifs[0].blk && !bus->ifs[1].blk) ||
void ide_data_writew(void *opaque, uint32_t addr, uint32_t val)
{
IDEBus *bus = opaque;
- IDEState *s = idebus_active_if(bus);
+ IDEState *s = ide_bus_active_if(bus);
uint8_t *p;
trace_ide_data_writew(addr, val, bus, s);
uint32_t ide_data_readw(void *opaque, uint32_t addr)
{
IDEBus *bus = opaque;
- IDEState *s = idebus_active_if(bus);
+ IDEState *s = ide_bus_active_if(bus);
uint8_t *p;
int ret;
void ide_data_writel(void *opaque, uint32_t addr, uint32_t val)
{
IDEBus *bus = opaque;
- IDEState *s = idebus_active_if(bus);
+ IDEState *s = ide_bus_active_if(bus);
uint8_t *p;
trace_ide_data_writel(addr, val, bus, s);
uint32_t ide_data_readl(void *opaque, uint32_t addr)
{
IDEBus *bus = opaque;
- IDEState *s = idebus_active_if(bus);
+ IDEState *s = ide_bus_active_if(bus);
uint8_t *p;
int ret;
return;
}
- s = idebus_active_if(bus);
+ s = ide_bus_active_if(bus);
is_read = (bus->error_status & IDE_RETRY_READ) != 0;
/* The error status must be cleared before resubmitting the request: The
{
DBDMA_io *io = opaque;
MACIOIDEState *m = io->opaque;
- IDEState *s = idebus_active_if(&m->bus);
+ IDEState *s = ide_bus_active_if(&m->bus);
int64_t offset;
MACIO_DPRINTF("pmac_ide_atapi_transfer_cb\n");
{
DBDMA_io *io = opaque;
MACIOIDEState *m = io->opaque;
- IDEState *s = idebus_active_if(&m->bus);
+ IDEState *s = ide_bus_active_if(&m->bus);
int64_t offset;
MACIO_DPRINTF("pmac_ide_transfer_cb\n");
static void pmac_ide_transfer(DBDMA_io *io)
{
MACIOIDEState *m = io->opaque;
- IDEState *s = idebus_active_if(&m->bus);
+ IDEState *s = ide_bus_active_if(&m->bus);
MACIO_DPRINTF("\n");
static void pmac_ide_flush(DBDMA_io *io)
{
MACIOIDEState *m = io->opaque;
- IDEState *s = idebus_active_if(&m->bus);
+ IDEState *s = ide_bus_active_if(&m->bus);
if (s->bus->dma->aiocb) {
blk_drain(s->blk);
case 0xd: /* Error */
return ide_ioport_read(&s->bus, 0x1);
case 0xe: /* Alternate Status */
- ifs = idebus_active_if(&s->bus);
+ ifs = ide_bus_active_if(&s->bus);
if (ifs->blk) {
return ifs->status;
} else {
return 0;
}
case 0xf: /* Device Address */
- ifs = idebus_active_if(&s->bus);
+ ifs = ide_bus_active_if(&s->bus);
return 0xc2 | ((~ifs->select << 2) & 0x3c);
default:
return ide_ioport_read(&s->bus, at);