}
void hubp1_dcc_control(struct hubp *hubp, bool enable,
- bool independent_64b_blks)
+ enum hubp_ind_block_size independent_64b_blks)
{
uint32_t dcc_en = enable ? 1 : 0;
uint32_t dcc_ind_64b_blk = independent_64b_blks ? 1 : 0;
void hubp1_dcc_control(struct hubp *hubp,
bool enable,
- bool independent_64b_blks);
+ enum hubp_ind_block_size independent_64b_blks);
#ifdef CONFIG_DRM_AMD_DC_DCN2_0
bool hubp1_program_surface_flip_and_addr(
}
void hubp2_dcc_control(struct hubp *hubp, bool enable,
- bool independent_64b_blks)
+ enum hubp_ind_block_size independent_64b_blks)
{
uint32_t dcc_en = enable ? 1 : 0;
uint32_t dcc_ind_64b_blk = independent_64b_blks ? 1 : 0;
bool flip_immediate);
void hubp2_dcc_control(struct hubp *hubp, bool enable,
- bool independent_64b_blks);
+ enum hubp_ind_block_size independent_64b_blks);
void hubp2_program_size(
struct hubp *hubp,
CURSOR_LINE_PER_CHUNK_16
};
+enum hubp_ind_block_size {
+ hubp_ind_block_unconstrained = 0,
+ hubp_ind_block_64b,
+};
+
struct hubp {
const struct hubp_funcs *funcs;
struct dc_context *ctx;
struct _vcs_dpi_display_ttu_regs_st *ttu_regs);
void (*dcc_control)(struct hubp *hubp, bool enable,
- bool independent_64b_blks);
+ enum hubp_ind_block_size blk_size);
+
void (*mem_program_viewport)(
struct hubp *hubp,
const struct rect *viewport,